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Reel/Frame:	036550/0001			Pages:	983
		Recorded:	09/03/2015
Attorney Dkt #:	3718.266
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14793
Page 41 of 148
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Patent #:	7411252	Issue Dt:	08/12/2008	Application #:	11160361	Filing Dt:	06/21/2005
Publication #:	US20060286724	Pub Dt:	12/21/2006
Title:	SUBSTRATE BACKGATE FOR TRIGATE FET

Patent #:	7065425	Issue Dt:	06/20/2006	Application #:	11160404	Filing Dt:	06/22/2005
Title:	METROLOGY TOOL ERROR LOG ANALYSIS METHODOLOGY AND SYSTEM

Patent #:	8299775	Issue Dt:	10/30/2012	Application #:	11160428	Filing Dt:	06/23/2005
Publication #:	US20060292855	Pub Dt:	12/28/2006
Title:	CURRENT-ALIGNED AUTO-GENERATED NON-EQUIAXIAL HOLE SHAPE FOR WIRING

Patent #:	7960791	Issue Dt:	06/14/2011	Application #:	11160457	Filing Dt:	06/24/2005
Publication #:	US20060292772	Pub Dt:	12/28/2006
Title:	DENSE PITCH BULK FINFET PROCESS BY SELECTIVE EPI AND ETCH

Patent #:	7482675	Issue Dt:	01/27/2009	Application #:	11160461	Filing Dt:	06/24/2005
Publication #:	US20070013071	Pub Dt:	01/18/2007
Title:	PROBING PADS IN KERF AREA FOR WAFER TESTING

Patent #:	7414275	Issue Dt:	08/19/2008	Application #:	11160463	Filing Dt:	06/24/2005
Publication #:	US20060289994	Pub Dt:	12/28/2006
Title:	MULTI-LEVEL INTERCONNECTIONS FOR AN INTEGRATED CIRCUIT CHIP

Patent #:	7445966	Issue Dt:	11/04/2008	Application #:	11160468	Filing Dt:	06/24/2005
Publication #:	US20070013072	Pub Dt:	01/18/2007
Title:	METHOD AND STRUCTURE FOR CHARGE DISSIPATION DURING FABRICATION OF INTEGRATED CIRCUITS AND ISOLATION THEREOF

Patent #:	7205237	Issue Dt:	04/17/2007	Application #:	11160667	Filing Dt:	07/05/2005
Publication #:	US20070010097	Pub Dt:	01/11/2007
Title:	APPARATUS AND METHOD FOR SELECTED SITE BACKSIDE UNDERLAYING OF Si, GaAs, Gax Aly Asz OF SOI TECHNOLOGIES FOR SCANNING PROBE MICROSCOPY AND ATOMIC FORCE PROBING CHARACTERIZATION

Patent #:	7312529	Issue Dt:	12/25/2007	Application #:	11160669	Filing Dt:	07/05/2005
Publication #:	US20070007665	Pub Dt:	01/11/2007
Title:	STRUCTURE AND METHOD FOR PRODUCING MULTIPLE SIZE INTERCONNECTIONS

Patent #:	7288478	Issue Dt:	10/30/2007	Application #:	11160670	Filing Dt:	07/05/2005
Publication #:	US20070010091	Pub Dt:	01/11/2007
Title:	METHOD FOR PERFORMING CHEMICAL SHRINK PROCESS OVER BARC (BOTTOM ANTI-REFLECTIVE COATING)

Patent #:	7674697	Issue Dt:	03/09/2010	Application #:	11160698	Filing Dt:	07/06/2005
Publication #:	US20070010081	Pub Dt:	01/11/2007
Title:	MOSFET WITH MULTIPLE FULLY SILICIDED GATE AND METHOD FOR MAKING THE SAME

Patent #:	7456115	Issue Dt:	11/25/2008	Application #:	11160700	Filing Dt:	07/06/2005
Publication #:	US20070010050	Pub Dt:	01/11/2007
Title:	METHOD FOR FORMING SEMICONDUCTOR DEVICES HAVING REDUCED GATE EDGE LEAKAGE CURRENT

Patent #:	7475372	Issue Dt:	01/06/2009	Application #:	11160701	Filing Dt:	07/06/2005
Publication #:	US20070011630	Pub Dt:	01/11/2007
Title:	METHODS FOR COMPUTING MILLER-FACTOR USING COUPLED PEAK NOISE

Patent #:	7510619	Issue Dt:	03/31/2009	Application #:	11160786	Filing Dt:	07/08/2005
Publication #:	US20070006695	Pub Dt:	01/11/2007
Title:	GREENSHEET VIA REPAIR/FILL TOOL

Patent #:	7972919	Issue Dt:	07/05/2011	Application #:	11160956	Filing Dt:	07/18/2005
Publication #:	US20070013031	Pub Dt:	01/18/2007
Title:	VERTICAL PNP TRANSISTOR AND METHOD OF MAKING SAME

Patent #:	7268428	Issue Dt:	09/11/2007	Application #:	11160997	Filing Dt:	07/19/2005
Publication #:	US20070045819	Pub Dt:	03/01/2007
Title:	THERMAL PASTE CONTAINMENT FOR SEMICONDUCTOR MODULES

Patent #:	7709313	Issue Dt:	05/04/2010	Application #:	11160999	Filing Dt:	07/19/2005
Publication #:	US20070020837	Pub Dt:	01/25/2007
Title:	HIGH PERFORMANCE CAPACITORS IN PLANAR BACK GATES CMOS

Patent #:	7358551	Issue Dt:	04/15/2008	Application #:	11161066	Filing Dt:	07/21/2005
Publication #:	US20070018205	Pub Dt:	01/25/2007
Title:	STRUCTURE AND METHOD FOR IMPROVED STRESS AND YIELD IN PFETS WITH EMBEDDED SIGE SOURCE/DRAIN REGIONS

Patent #:	7838943	Issue Dt:	11/23/2010	Application #:	11161146	Filing Dt:	07/25/2005
Publication #:	US20070021293	Pub Dt:	01/25/2007
Title:	SHARED GATE FOR CONVENTIONAL PLANAR DEVICE AND HORIZONTAL CNT

Patent #:	7526743	Issue Dt:	04/28/2009	Application #:	11161159	Filing Dt:	07/25/2005
Publication #:	US20060044932	Pub Dt:	03/02/2006
Title:	METHOD FOR ROUTING DATA PATHS IN A SEMICONDUCTOR CHIP WITH A PLURALITY OF LAYERS

Patent #:	7629192	Issue Dt:	12/08/2009	Application #:	11161181	Filing Dt:	10/13/2005
Publication #:	US20070085156	Pub Dt:	04/19/2007
Title:	PASSIVE ELECTRICALLY TESTABLE ACCELERATION AND VOLTAGE MEASUREMENT DEVICES

Patent #:	7352607	Issue Dt:	04/01/2008	Application #:	11161183	Filing Dt:	07/26/2005
Publication #:	US20070025138	Pub Dt:	02/01/2007
Title:	NON-VOLATILE SWITCHING AND MEMORY DEVICES USING VERTICAL NANOTUBES

Patent #:	7288802	Issue Dt:	10/30/2007	Application #:	11161213	Filing Dt:	07/27/2005
Publication #:	US20070023756	Pub Dt:	02/01/2007
Title:	VIRTUAL BODY-CONTACTED TRIGATE

Patent #:	7384878	Issue Dt:	06/10/2008	Application #:	11161214	Filing Dt:	07/27/2005
Publication #:	US20060003468	Pub Dt:	01/05/2006
Title:	METHOD FOR APPLYING A LAYER TO A HYDROPHOBIC SURFACE

Patent #:	7459367	Issue Dt:	12/02/2008	Application #:	11161239	Filing Dt:	07/27/2005
Publication #:	US20070023811	Pub Dt:	02/01/2007
Title:	METHOD OF FORMING A VERTICAL P-N JUNCTION DEVICE

Patent #:	7170772	Issue Dt:	01/30/2007	Application #:	11161321	Filing Dt:	07/29/2005
Publication #:	US20070035981	Pub Dt:	02/15/2007
Title:	APPARATUS AND METHOD FOR DYNAMIC CONTROL OF DOUBLE GATE DEVICES

Patent #:	7873961	Issue Dt:	01/18/2011	Application #:	11161330	Filing Dt:	07/29/2005
Publication #:	US20070028151	Pub Dt:	02/01/2007
Title:	SUPERVISORY OPERATING SYSTEM FOR RUNNING MULTIPLE CHILD OPERATING SYSTEMS SIMULTANEOUSLY AND OPTIMIZING RESOURCE USAGE

Patent #:	7382029	Issue Dt:	06/03/2008	Application #:	11161337	Filing Dt:	07/29/2005
Publication #:	US20070026598	Pub Dt:	02/01/2007
Title:	METHOD AND APPARATUS FOR IMPROVING INTEGRATED CIRCUIT DEVICE PERFORMANCE USING HYBRID CRYSTAL ORIENTATIONS

Patent #:	7151023	Issue Dt:	12/19/2006	Application #:	11161372	Filing Dt:	08/01/2005
Title:	METAL GATE MOSFET BY FULL SEMICONDUCTOR METAL ALLOY CONVERSION

Patent #:	7535105	Issue Dt:	05/19/2009	Application #:	11161414	Filing Dt:	08/02/2005
Publication #:	US20070029646	Pub Dt:	02/08/2007
Title:	INTER-CHIP ESD PROTECTION STRUCTURE FOR HIGH SPEED AND HIGH FREQUENCY DEVICES

Patent #:	7399696	Issue Dt:	07/15/2008	Application #:	11161415	Filing Dt:	08/02/2005
Publication #:	US20070032030	Pub Dt:	02/08/2007
Title:	METHOD FOR HIGH PERFORMANCE INDUCTOR FABRICATION USING A TRIPLE DAMASCENE PROCESS WITH COPPER BEOL

Patent #:	7348642	Issue Dt:	03/25/2008	Application #:	11161442	Filing Dt:	08/03/2005
Publication #:	US20070029624	Pub Dt:	02/08/2007
Title:	FIN-TYPE FIELD EFFECT TRANSISTOR

Patent #:	7253482	Issue Dt:	08/07/2007	Application #:	11161447	Filing Dt:	08/03/2005
Publication #:	US20070032028	Pub Dt:	02/08/2007
Title:	STRUCTURE FOR REDUCING OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS

Patent #:	7323410	Issue Dt:	01/29/2008	Application #:	11161538	Filing Dt:	08/08/2005
Publication #:	US20070032055	Pub Dt:	02/08/2007
Title:	DRY ETCHBACK OF INTERCONNECT CONTACTS

Patent #:	7585764	Issue Dt:	09/08/2009	Application #:	11161599	Filing Dt:	08/09/2005
Publication #:	US20070037403	Pub Dt:	02/15/2007
Title:	VIA BOTTOM CONTACT AND METHOD OF MANUFACTURING SAME

Patent #:	7230287	Issue Dt:	06/12/2007	Application #:	11161623	Filing Dt:	08/10/2005
Publication #:	US20070034971	Pub Dt:	02/15/2007
Title:	CHEVRON CMOS TRIGATE STRUCTURE

Patent #:	7473523	Issue Dt:	01/06/2009	Application #:	11161624	Filing Dt:	08/10/2005
Publication #:	US20070037098	Pub Dt:	02/15/2007
Title:	SYSTEMS AND METHODS FOR MODIFYING FEATURES IN A SEMI-CONDUCTOR DEVICE

Patent #:	7136317	Issue Dt:	11/14/2006	Application #:	11161628	Filing Dt:	08/10/2005
Title:	DRAM WITH SELF-RESETTING DATA PATH FOR REDUCED POWER CONSUMPTION

Patent #:	7351348	Issue Dt:	04/01/2008	Application #:	11161630	Filing Dt:	08/10/2005
Publication #:	US20070034605	Pub Dt:	02/15/2007
Title:	EVAPORATION CONTROL USING COATING

Patent #:	7437277	Issue Dt:	10/14/2008	Application #:	11161651	Filing Dt:	08/11/2005
Publication #:	US20070038416	Pub Dt:	02/15/2007
Title:	MODEL INDEPENDENT SIMULATION

Patent #:	7352609	Issue Dt:	04/01/2008	Application #:	11161742	Filing Dt:	08/15/2005
Publication #:	US20070035985	Pub Dt:	02/15/2007
Title:	VOLTAGE CONTROLLED STATIC RANDOM ACCESS MEMORY

Patent #:	7485540	Issue Dt:	02/03/2009	Application #:	11161832	Filing Dt:	08/18/2005
Publication #:	US20070040239	Pub Dt:	02/22/2007
Title:	INTEGRATED BEOL THIN FILM RESISTOR

Patent #:	8294505	Issue Dt:	10/23/2012	Application #:	11161932	Filing Dt:	08/23/2005
Publication #:	US20070103228	Pub Dt:	05/10/2007
Title:	STACKABLE PROGRAMMABLE PASSIVE DEVICE AND A TESTING METHOD

Patent #:	8299500	Issue Dt:	10/30/2012	Application #:	11161936	Filing Dt:	08/23/2005
Publication #:	US20070051980	Pub Dt:	03/08/2007
Title:	SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR HAVING INTERSTITIAL TRAPPING LAYER IN BASE REGION

Patent #:	7459743	Issue Dt:	12/02/2008	Application #:	11161962	Filing Dt:	08/24/2005
Publication #:	US20070047293	Pub Dt:	03/01/2007
Title:	DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR

Patent #:	7442585	Issue Dt:	10/28/2008	Application #:	11162126	Filing Dt:	08/30/2005
Publication #:	US20070045611	Pub Dt:	03/01/2007
Title:	MOSFET WITH LATERALLY GRADED CHANNEL REGION AND METHOD FOR MANUFACTURING SAME

Patent #:	7380233	Issue Dt:	05/27/2008	Application #:	11162196	Filing Dt:	08/31/2005
Publication #:	US20070050736	Pub Dt:	03/01/2007
Title:	METHOD OF FACILITATING INTEGRATED CIRCUIT DESIGN USING MANUFACTURED PROPERTY VALUES

Patent #:	NONE	Issue Dt:		Application #:	11162218	Filing Dt:	09/01/2005
Publication #:	US20070046421	Pub Dt:	03/01/2007
Title:	STRUCTURE AND METHOD FOR FORMING THIN FILM RESISTOR WITH TOPOGRAPHY CONTROLLED RESISTANCE DENSITY

Patent #:	NONE	Issue Dt:		Application #:	11162219	Filing Dt:	09/01/2005
Publication #:	US20070048981	Pub Dt:	03/01/2007
Title:	METHOD FOR PROTECTING A SEMICONDUCTOR DEVICE FROM CARBON DEPLETION BASED DAMAGE

Patent #:	NONE	Issue Dt:		Application #:	11162369	Filing Dt:	09/08/2005
Publication #:	US20070054115	Pub Dt:	03/08/2007
Title:	METHOD FOR CLEANING PARTICULATE FOREIGN MATTER FROM THE SURFACES OF SEMICONDUCTOR WAFERS

Patent #:	7436057	Issue Dt:	10/14/2008	Application #:	11162389	Filing Dt:	09/08/2005
Publication #:	US20070052111	Pub Dt:	03/08/2007
Title:	ELASTOMER INTERPOSER WITH VOIDS IN A COMPRESSIVE LOADING SYSTEM

Patent #:	7276751	Issue Dt:	10/02/2007	Application #:	11162413	Filing Dt:	09/09/2005
Publication #:	US20070057302	Pub Dt:	03/15/2007
Title:	TRENCH METAL-INSULATOR-METAL (MIM) CAPACITORS INTEGRATED WITH MIDDLE-OF-LINE METAL CONTACTS, AND METHOD OF FABRICATING SAME

Patent #:	7361950	Issue Dt:	04/22/2008	Application #:	11162471	Filing Dt:	09/12/2005
Publication #:	US20070057343	Pub Dt:	03/15/2007
Title:	INTEGRATION OF A MIM CAPACITOR WITH A PLATE FORMED IN A WELL REGION AND WITH A HIGH-K DIELECTRIC

Patent #:	7227233	Issue Dt:	06/05/2007	Application #:	11162472	Filing Dt:	09/12/2005
Publication #:	US20070057323	Pub Dt:	03/15/2007
Title:	SILICON-ON-INSULATOR (SOI) READ ONLY MEMORY (ROM) ARRAY AND METHOD OF MAKING A SOI ROM

Patent #:	7776725	Issue Dt:	08/17/2010	Application #:	11162478	Filing Dt:	09/12/2005
Publication #:	US20070054480	Pub Dt:	03/08/2007
Title:	ANTI-HALO COMPENSATION

Patent #:	7394154	Issue Dt:	07/01/2008	Application #:	11162513	Filing Dt:	09/13/2005
Publication #:	US20070057374	Pub Dt:	03/15/2007
Title:	EMBEDDED BARRIER FOR DIELECTRIC ENCAPSULATION

Patent #:	NONE	Issue Dt:		Application #:	11162583	Filing Dt:	09/15/2005
Publication #:	US20070061764	Pub Dt:	03/15/2007
Title:	KEYWORD-BASED CONNECTIVITY VERIFICATION

Patent #:	7400031	Issue Dt:	07/15/2008	Application #:	11162660	Filing Dt:	09/19/2005
Publication #:	US20070063230	Pub Dt:	03/22/2007
Title:	ASYMMETRICALLY STRESSED CMOS FINFET

Patent #:	8207568	Issue Dt:	06/26/2012	Application #:	11162661	Filing Dt:	09/19/2005
Publication #:	US20070065966	Pub Dt:	03/22/2007
Title:	PROCESS FOR SINGLE AND MULTIPLE LEVEL METAL-INSULATOR-METAL INTEGRATION WITH A SINGLE MASK

Patent #:	7323374	Issue Dt:	01/29/2008	Application #:	11162663	Filing Dt:	09/19/2005
Publication #:	US20070063276	Pub Dt:	03/22/2007
Title:	DENSE CHEVRON FINFET AND METHOD OF MANUFACTURING SAME

Patent #:	7563704	Issue Dt:	07/21/2009	Application #:	11162666	Filing Dt:	09/19/2005
Publication #:	US20070063348	Pub Dt:	03/22/2007
Title:	METHOD OF FORMING AN INTERCONNECT INCLUDING A DIELECTRIC CAP HAVING A TENSILE STRESS

Patent #:	8202460	Issue Dt:	06/19/2012	Application #:	11162765	Filing Dt:	09/22/2005
Publication #:	US20070063392	Pub Dt:	03/22/2007
Title:	MICROELECTRONIC SUBSTRATE HAVING REMOVABLE EDGE EXTENSION ELEMENT

Patent #:	7279426	Issue Dt:	10/09/2007	Application #:	11162766	Filing Dt:	09/22/2005
Publication #:	US20070066073	Pub Dt:	03/22/2007
Title:	LIKE INTEGRATED CIRCUIT DEVICES WITH DIFFERENT DEPTH

Patent #:	7388244	Issue Dt:	06/17/2008	Application #:	11162776	Filing Dt:	09/22/2005
Publication #:	US20070063244	Pub Dt:	03/22/2007
Title:	TRENCH METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHOD OF FABRICATING SAME

Patent #:	7605447	Issue Dt:	10/20/2009	Application #:	11162780	Filing Dt:	09/22/2005
Publication #:	US20070063278	Pub Dt:	03/22/2007
Title:	HIGHLY MANUFACTURABLE SRAM CELLS IN SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION

Patent #:	7308663	Issue Dt:	12/11/2007	Application #:	11162846	Filing Dt:	09/26/2005
Publication #:	US20070074135	Pub Dt:	03/29/2007
Title:	CIRCUIT DESIGN VERIFICATION USING CHECKPOINTING

Patent #:	7894291	Issue Dt:	02/22/2011	Application #:	11162847	Filing Dt:	09/26/2005
Publication #:	US20070070769	Pub Dt:	03/29/2007
Title:	CIRCUIT AND METHOD FOR CONTROLLING A STANDBY VOLTAGE LEVEL OF A MEMORY

Patent #:	7202513	Issue Dt:	04/10/2007	Application #:	11162953	Filing Dt:	09/29/2005
Publication #:	US20070069294	Pub Dt:	03/29/2007
Title:	STRESS ENGINEERING USING DUAL PAD NITRIDE WITH SELECTIVE SOI DEVICE ARCHITECTURE

Patent #:	NONE	Issue Dt:		Application #:	11162959	Filing Dt:	09/29/2005
Publication #:	US20070069300	Pub Dt:	03/29/2007
Title:	A MOSFET structure formed on buried oxide regions having different depths.

Patent #:	7282949	Issue Dt:	10/16/2007	Application #:	11162997	Filing Dt:	09/30/2005
Publication #:	US20070075733	Pub Dt:	04/05/2007
Title:	FPGA POWERUP TO KNOWN FUNCTIONAL STATE

Patent #:	7495743	Issue Dt:	02/24/2009	Application #:	11163007	Filing Dt:	09/30/2005
Publication #:	US20070076179	Pub Dt:	04/05/2007
Title:	IMMERSION OPTICAL LITHOGRAPHY SYSTEM HAVING PROTECTIVE OPTICAL COATING

Patent #:	7552041	Issue Dt:	06/23/2009	Application #:	11163039	Filing Dt:	10/03/2005
Publication #:	US20070088626	Pub Dt:	04/19/2007
Title:	METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR DETERMINING AN OPTIMAL DATABASE REFRESH RATE

Patent #:	7396713	Issue Dt:	07/08/2008	Application #:	11163165	Filing Dt:	10/07/2005
Publication #:	US20070080401	Pub Dt:	04/12/2007
Title:	STRUCTURE AND METHOD FOR FORMING ASYMMETRICAL OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS

Patent #:	7521950	Issue Dt:	04/21/2009	Application #:	11163167	Filing Dt:	10/07/2005
Publication #:	US20070081410	Pub Dt:	04/12/2007
Title:	WAFER LEVEL I/O TEST AND REPAIR ENABLED BY I/O LAYER

Patent #:	7645620	Issue Dt:	01/12/2010	Application #:	11163229	Filing Dt:	10/11/2005
Publication #:	US20070082417	Pub Dt:	04/12/2007
Title:	METHOD AND STRUCTURE FOR REDUCING PRIOR LEVEL EDGE INTERFERENCE WITH CRITICAL DIMENSION MEASUREMENT

Patent #:	NONE	Issue Dt:		Application #:	11163235	Filing Dt:	10/11/2005
Publication #:	US20070080455	Pub Dt:	04/12/2007
Title:	SEMICONDUCTORS HAVING SACRIFICIAL DIELECTRIC CAP AND METHODS OF MAKING

Patent #:	NONE	Issue Dt:		Application #:	11163292	Filing Dt:	10/13/2005
Publication #:	US20060080626	Pub Dt:	04/13/2006
Title:	VISUALIZATION METHOD AND APPARATUS FOR LOGIC VERIFICATION AND BEHAVIORAL ANALYSIS

Patent #:	7344679	Issue Dt:	03/18/2008	Application #:	11163327	Filing Dt:	10/14/2005
Publication #:	US20070086927	Pub Dt:	04/19/2007
Title:	METHOD AND APPARATUS FOR POINT OF CARE OSMOLARITY TESTING

Patent #:	7602265	Issue Dt:	10/13/2009	Application #:	11163485	Filing Dt:	10/20/2005
Publication #:	US20070090902	Pub Dt:	04/26/2007
Title:	APPARATUS FOR ACCURATE AND EFFICIENT QUALITY AND RELIABILITY EVALUATION OF MICRO ELECTROMECHANICAL SYSTEMS

Patent #:	7696574	Issue Dt:	04/13/2010	Application #:	11163652	Filing Dt:	10/26/2005
Publication #:	US20070090467	Pub Dt:	04/26/2007
Title:	SEMICONDUCTOR SUBSTRATE WITH MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS

Patent #:	7759739	Issue Dt:	07/20/2010	Application #:	11163683	Filing Dt:	10/27/2005
Publication #:	US20070096215	Pub Dt:	05/03/2007
Title:	TRANSISTOR WITH DIELECTRIC STRESSOR ELEMENTS

Patent #:	7221024	Issue Dt:	05/22/2007	Application #:	11163686	Filing Dt:	10/27/2005
Publication #:	US20070096223	Pub Dt:	05/03/2007
Title:	TRANSISTOR HAVING DIELECTRIC STRESSOR ELEMENTS FOR APPLYING IN-PLANE SHEAR STRESS

Patent #:	7348225	Issue Dt:	03/25/2008	Application #:	11163687	Filing Dt:	10/27/2005
Publication #:	US20070099350	Pub Dt:	05/03/2007
Title:	STRUCTURE AND METHOD OF FABRICATING FINFET WITH BURIED CHANNEL

Patent #:	7386815	Issue Dt:	06/10/2008	Application #:	11163696	Filing Dt:	10/27/2005
Publication #:	US20070099236	Pub Dt:	05/03/2007
Title:	TEST YIELD ESTIMATE FOR SEMICONDUCTOR PRODUCTS CREATED FROM A LIBRARY

Patent #:	NONE	Issue Dt:		Application #:	11163741	Filing Dt:	10/28/2005
Publication #:	US20070096260	Pub Dt:	05/03/2007
Title:	REDUCED PARASITIC AND HIGH VALUE RESISTOR AND METHOD OF MANUFACTURE

Patent #:	NONE	Issue Dt:		Application #:	11163791	Filing Dt:	10/31/2005
Publication #:	US20070099386	Pub Dt:	05/03/2007
Title:	INTEGRATION SCHEME FOR HIGH GAIN FET IN STANDARD CMOS PROCESS

Patent #:	7286425	Issue Dt:	10/23/2007	Application #:	11163800	Filing Dt:	10/31/2005
Publication #:	US20070097768	Pub Dt:	05/03/2007
Title:	SYSTEM AND METHOD FOR CAPACITIVE MIS-MATCH BIT-LINE SENSING

Patent #:	7287740	Issue Dt:	10/30/2007	Application #:	11163835	Filing Dt:	11/01/2005
Publication #:	US20070114505	Pub Dt:	05/24/2007
Title:	HOISTING APPARATUS

Patent #:	7655511	Issue Dt:	02/02/2010	Application #:	11163908	Filing Dt:	11/03/2005
Publication #:	US20070096206	Pub Dt:	05/03/2007
Title:	GATE ELECTRODE STRESS CONTROL FOR FINFET PERFORMANCE ENHANCEMENT

Patent #:	7397260	Issue Dt:	07/08/2008	Application #:	11163948	Filing Dt:	11/04/2005
Publication #:	US20070115018	Pub Dt:	05/24/2007
Title:	STRUCTURE AND METHOD FOR MONITORING STRESS-INDUCED DEGRADATION OF CONDUCTIVE INTERCONNECTS

Patent #:	7381610	Issue Dt:	06/03/2008	Application #:	11163966	Filing Dt:	11/04/2005
Publication #:	US20070102766	Pub Dt:	05/10/2007
Title:	SEMICONDUCTOR TRANSISTORS WITH CONTACT HOLES CLOSE TO GATES

Patent #:	7454305	Issue Dt:	11/18/2008	Application #:	11164040	Filing Dt:	11/08/2005
Publication #:	US20070115019	Pub Dt:	05/24/2007
Title:	METHOD AND APPARATUS FOR STORING CIRCUIT CALIBRATION INFORMATION

Patent #:	7627836	Issue Dt:	12/01/2009	Application #:	11164044	Filing Dt:	11/08/2005
Publication #:	US20070106968	Pub Dt:	05/10/2007
Title:	OPC TRIMMING FOR PERFORMANCE

Patent #:	7335563	Issue Dt:	02/26/2008	Application #:	11164070	Filing Dt:	11/09/2005
Publication #:	US20070105326	Pub Dt:	05/10/2007
Title:	ROTATED FIELD EFFECT TRANSISTORS AND METHOD OF MANUFACTURE

Patent #:	NONE	Issue Dt:		Application #:	11164071	Filing Dt:	11/09/2005
Publication #:	US20070102789	Pub Dt:	05/10/2007
Title:	BIPOLAR TRANSISTOR AND BACK-GATED TRANSISTOR STRUCTURE AND METHOD

Patent #:	7633106	Issue Dt:	12/15/2009	Application #:	11164072	Filing Dt:	11/09/2005
Publication #:	US20070102738	Pub Dt:	05/10/2007
Title:	LIGHT SHIELD FOR CMOS IMAGER

Patent #:	7652313	Issue Dt:	01/26/2010	Application #:	11164098	Filing Dt:	11/10/2005
Publication #:	US20070102740	Pub Dt:	05/10/2007
Title:	DEEP TRENCH CONTACT AND ISOLATION OF BURIED PHOTODETECTORS

Patent #:	7323780	Issue Dt:	01/29/2008	Application #:	11164107	Filing Dt:	11/10/2005
Publication #:	US20070105359	Pub Dt:	05/10/2007
Title:	ELECTRICAL INTERCONNECTION STRUCTURE FORMATION

Patent #:	7492015	Issue Dt:	02/17/2009	Application #:	11164109	Filing Dt:	11/10/2005
Publication #:	US20070102747	Pub Dt:	05/10/2007
Title:	COMPLEMENTARY CARBON NANOTUBE TRIPLE GATE TECHNOLOGY

100

Patent #:	7785950	Issue Dt:	08/31/2010	Application #:	11164114	Filing Dt:	11/10/2005
Publication #:	US20070105299	Pub Dt:	05/10/2007
Title:	DUAL STRESS MEMORY TECHNIQUE METHOD AND RELATED STRUCTURE

Assignor

INTERNATIONAL BUSINESS MACHINES CORPORATION

Exec Dt:

06/29/2015

Assignee

GLOBALFOUNDRIES U.S. 2 LLC

2070 ROUTE 52

HOPEWELL JUNCTION, NEW YORK 12533

Correspondence name and address
	HESLIN ROTHENBERG FARLEY & MESITI P.C.
	5 COLUMBIA CIRCLE
	ALBANY, NY 12203

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