|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11275035
|
Filing Dt:
|
12/05/2005
|
Publication #:
|
|
Pub Dt:
|
06/07/2007
| | | | |
Title:
|
AUTOMATED SIMULATION TESTBENCH GENERATION FOR SERIALIZER/DESERIALIZER DATAPATH SYSTEMS
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|
Patent #:
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|
Issue Dt:
|
02/09/2010
|
Application #:
|
11275058
|
Filing Dt:
|
12/06/2005
|
Publication #:
|
|
Pub Dt:
|
06/07/2007
| | | | |
Title:
|
ON DEMAND CIRCUIT FUNCTION EXECUTION EMPLOYING OPTICAL SENSING
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|
Patent #:
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|
Issue Dt:
|
02/02/2010
|
Application #:
|
11275076
|
Filing Dt:
|
12/08/2005
|
Publication #:
|
|
Pub Dt:
|
06/14/2007
| | | | |
Title:
|
A METHOD FOR IC WIRING YIELD OPTIMIZATION, INCLUDING WIRE WIDENING DURING AND AFTER ROUTING
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|
|
Patent #:
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|
Issue Dt:
|
06/14/2016
|
Application #:
|
11275091
|
Filing Dt:
|
12/09/2005
|
Publication #:
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|
Pub Dt:
|
06/14/2007
| | | | |
Title:
|
METHOD AND SYSTEM OF COMMUNICATING BETWEEN PEER PROCESSORS IN SoC ENVIRONMENT
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|
Patent #:
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|
Issue Dt:
|
12/07/2010
|
Application #:
|
11275092
|
Filing Dt:
|
12/09/2005
|
Publication #:
|
|
Pub Dt:
|
07/19/2007
| | | | |
Title:
|
METHOD AND SYSTEM OF COHERENT DESIGN VERIFICATION OF INTER-CLUSTER INTERACTIONS
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|
Patent #:
|
|
Issue Dt:
|
02/24/2009
|
Application #:
|
11275275
|
Filing Dt:
|
12/21/2005
|
Publication #:
|
|
Pub Dt:
|
06/21/2007
| | | | |
Title:
|
SEMICONDUCTOR YIELD ESTIMATION
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|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
11275417
|
Filing Dt:
|
12/30/2005
|
Publication #:
|
|
Pub Dt:
|
07/05/2007
| | | | |
Title:
|
PIXEL ARRAY, IMAGING SENSOR INCLUDING THE PIXEL ARRAY AND DIGITAL CAMERA INCLUDING THE IMAGING SENSOR
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|
Patent #:
|
|
Issue Dt:
|
09/21/2010
|
Application #:
|
11275481
|
Filing Dt:
|
01/09/2006
|
Publication #:
|
|
Pub Dt:
|
08/09/2007
| | | | |
Title:
|
INTEGRATED CIRCUIT STRUCTURES WITH SILICON GERMANIUM FILM INCORPORATED AS LOCAL INTERCONNECT AND/OR CONTACT
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|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
11275482
|
Filing Dt:
|
01/09/2006
|
Publication #:
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|
Pub Dt:
|
04/27/2006
| | | | |
Title:
|
INTEGRATED CIRCUIT STRUCTURES FOR PREVENTING CHARGING DAMAGE
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|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
11275492
|
Filing Dt:
|
01/10/2006
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
SRAM ARRAY AND ANALOG FET WITH DUAL-STRAIN LAYERS COMPRISING RELAXED REGIONS
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|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
11275514
|
Filing Dt:
|
01/11/2006
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
SEMICONDUCTOR TRANSISTORS WITH EXPANDED TOP PORTIONS OF GATES
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|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11275536
|
Filing Dt:
|
01/12/2006
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
METHOD FOR INCREASING THE MANUFACTURING YIELD OF PROGRAMMABLE LOGIC DEVICES
|
|
|
Patent #:
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|
Issue Dt:
|
07/01/2008
|
Application #:
|
11275540
|
Filing Dt:
|
01/13/2006
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
MEMORY ARRAY REPAIR WHERE REPAIR LOGIC CANNOT OPERATE AT SAME OPERATING CONDITION AS ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2009
|
Application #:
|
11275604
|
Filing Dt:
|
01/19/2006
|
Publication #:
|
|
Pub Dt:
|
08/16/2007
| | | | |
Title:
|
DUAL-DAMASCENE PROCESS TO FABRICATE THICK WIRE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
11275611
|
Filing Dt:
|
01/19/2006
|
Publication #:
|
|
Pub Dt:
|
07/19/2007
| | | | |
Title:
|
INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
11275638
|
Filing Dt:
|
01/20/2006
|
Publication #:
|
|
Pub Dt:
|
07/26/2007
| | | | |
Title:
|
ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11275644
|
Filing Dt:
|
01/20/2006
|
Publication #:
|
|
Pub Dt:
|
07/26/2007
| | | | |
Title:
|
STRUCTURE AND METHOD FOR ENHANCED TRIPLE WELL LATCHUP ROBUSTNESS
|
|
|
Patent #:
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|
Issue Dt:
|
05/26/2009
|
Application #:
|
11275694
|
Filing Dt:
|
01/25/2006
|
Publication #:
|
|
Pub Dt:
|
07/26/2007
| | | | |
Title:
|
SYSTEM AND METHOD FOR STORING AND TRANSPORTING PHOTOMASKS IN FLUID
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|
|
Patent #:
|
|
Issue Dt:
|
01/08/2008
|
Application #:
|
11275773
|
Filing Dt:
|
01/27/2006
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
NOISE REDUCTION IN DIGITAL SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2009
|
Application #:
|
11275867
|
Filing Dt:
|
02/01/2006
|
Publication #:
|
|
Pub Dt:
|
08/02/2007
| | | | |
Title:
|
SOLDER WALL STRUCTURE IN FLIP-CHIP TECHNOLOGIES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2007
|
Application #:
|
11276024
|
Filing Dt:
|
02/10/2006
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
Title:
|
METHOD TO ELIMINATE ARSENIC CONTAMINATION IN TRENCH CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
11276085
|
Filing Dt:
|
02/14/2006
|
Publication #:
|
|
Pub Dt:
|
08/16/2007
| | | | |
Title:
|
A CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
11276130
|
Filing Dt:
|
02/15/2006
|
Publication #:
|
|
Pub Dt:
|
08/16/2007
| | | | |
Title:
|
SWITCHING SYSTEM FOR SIGNAL MONITORING AND SWITCH-BACK CONTROL
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11276160
|
Filing Dt:
|
02/16/2006
|
Publication #:
|
|
Pub Dt:
|
08/16/2007
| | | | |
Title:
|
PIXEL SENSOR STRUCTURE INCLUDING LIGHT PIPE AND METHOD FOR FABRICATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2010
|
Application #:
|
11276232
|
Filing Dt:
|
02/20/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
PHASE CALIBRATION FOR ATTENUATING PHASE-SHIFT MASKS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
11276236
|
Filing Dt:
|
02/20/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
PROCESSOR PIPELINE ARCHITECTURE LOGIC STATE RETENTION SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
11276248
|
Filing Dt:
|
02/21/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
METHOD FOR NEUTRALIZING TRAPPED CHARGE IN A CHARGE ACCUMULATION LAYER OF A SEMICONDUCTOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2011
|
Application #:
|
11276282
|
Filing Dt:
|
02/22/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
METHOD OF FABRICATING A PRECISION BURIED RESISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2009
|
Application #:
|
11276366
|
Filing Dt:
|
02/27/2006
|
Publication #:
|
|
Pub Dt:
|
08/30/2007
| | | | |
Title:
|
MULTI-ORIENTATION SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE, AND METHOD OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
|
Application #:
|
11276369
|
Filing Dt:
|
02/27/2006
|
Publication #:
|
|
Pub Dt:
|
08/30/2007
| | | | |
Title:
|
HIGH PERFORMANCE TAPERED VARACTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
11276380
|
Filing Dt:
|
02/27/2006
|
Publication #:
|
|
Pub Dt:
|
08/30/2007
| | | | |
Title:
|
CHIP UNDERFILL IN FLIP-CHIP TECHNOLOGIES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11276413
|
Filing Dt:
|
02/28/2006
|
Publication #:
|
|
Pub Dt:
|
08/30/2007
| | | | |
Title:
|
MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)
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|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
11276433
|
Filing Dt:
|
02/28/2006
|
Publication #:
|
|
Pub Dt:
|
08/30/2007
| | | | |
Title:
|
TESTING OF MULTIPLE ASYNCHRONOUS LOGIC DOMAINS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2008
|
Application #:
|
11276451
|
Filing Dt:
|
02/28/2006
|
Publication #:
|
|
Pub Dt:
|
08/30/2007
| | | | |
Title:
|
INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES
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|
|
Patent #:
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|
Issue Dt:
|
02/10/2009
|
Application #:
|
11276511
|
Filing Dt:
|
03/03/2006
|
Publication #:
|
|
Pub Dt:
|
09/06/2007
| | | | |
Title:
|
IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN
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|
|
Patent #:
|
|
Issue Dt:
|
04/28/2009
|
Application #:
|
11277306
|
Filing Dt:
|
03/23/2006
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
ERROR DETECTION AND CORRECTION IN SEMICONDUCTOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11277315
|
Filing Dt:
|
03/23/2006
|
Publication #:
|
|
Pub Dt:
|
09/27/2007
| | | | |
Title:
|
METHOD OF IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS
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|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11277385
|
Filing Dt:
|
03/24/2006
|
Publication #:
|
|
Pub Dt:
|
09/27/2007
| | | | |
Title:
|
STATIC TIMING SLACKS ANALYSIS AND MODIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2009
|
Application #:
|
11277398
|
Filing Dt:
|
03/24/2006
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
METHOD OF FORMING A CRACK STOP VOID IN A LOW-K DIELECTRIC LAYER BETWEEN ADJACENT FUSEES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
|
Application #:
|
11277677
|
Filing Dt:
|
03/28/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
DUAL-PLANE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
11278118
|
Filing Dt:
|
03/30/2006
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
METHODS OF CREATING A DICTIONARY FOR DATA COMPRESSION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11278162
|
Filing Dt:
|
03/31/2006
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
METHOD FOR IMPLEMENTING OVERLAY-BASED MODIFICATION OF VLSI DESIGN LAYOUT
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|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
11278169
|
Filing Dt:
|
03/31/2006
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
APPARATUS FOR IMPLEMENTING DYNAMIC DATA PATH WITH INTERLOCKED KEEPER AND RESTORE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2008
|
Application #:
|
11278262
|
Filing Dt:
|
03/31/2006
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
METHOD AND ARCHITECTURE FOR POWER MANAGEMENT OF AN ELECTRONIC DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
11278910
|
Filing Dt:
|
04/06/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
PROTECTING SILICON GERMANIUM SIDEWALL WITH SILICON FOR STRAINED SILICON/SILICON MOSFETS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2008
|
Application #:
|
11278924
|
Filing Dt:
|
04/06/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
METHODOLOGY FOR PLACEMENT BASED ON CIRCUIT FUNCTION AND LATCHUP SENSITIVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2009
|
Application #:
|
11279019
|
Filing Dt:
|
04/07/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
LOW LEAKAGE METAL-CONTAINING CAP PROCESS USING OXIDATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
11279063
|
Filing Dt:
|
04/07/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
11279237
|
Filing Dt:
|
04/10/2006
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
METHODS AND READABLE MEDIA FOR USING RELATIVE POSITIONING IN STRUCTURES WITH DYNAMIC RANGES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
11279283
|
Filing Dt:
|
04/11/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
VLSI ARTWORK LEGALIZATION FOR HIERARCHICAL DESIGNS WITH MULTIPLE GRID CONSTRAINTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
11279300
|
Filing Dt:
|
04/11/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
METHOD FOR COMPUTING THE SENSITIVITY OF A VLSI DESIGN TO BOTH RANDOM AND SYSTEMATIC DEFECTS USING A CRITICAL AREA ANALYSIS TOOL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2008
|
Application #:
|
11279312
|
Filing Dt:
|
04/11/2006
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
METHOD FOR VERIFYING PERFORMANCE OF AN ARRAY BY SIMULATING OPERATION OF EDGE CELLS IN A FULL ARRAY MODEL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
|
Application #:
|
11279434
|
Filing Dt:
|
04/12/2006
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
VERTICAL PARALLEL PLATE CAPACITOR USING SPACER SHAPED ELECTRODES AND METHOD FOR FABRICATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
11279507
|
Filing Dt:
|
04/12/2006
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
DETERMINING HISTORY STATE OF DATA BASED ON STATE OF PARTIALLY DEPLETED SILICON-ON-INSULATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
11279639
|
Filing Dt:
|
04/13/2006
|
Publication #:
|
|
Pub Dt:
|
11/08/2007
| | | | |
Title:
|
DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11279659
|
Filing Dt:
|
04/13/2006
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
Field Effect Transistor With Etched-Back Gate Dielectric
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
11279758
|
Filing Dt:
|
04/14/2006
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
MINIMUM LAYOUT PERTURBATION-BASED ARTWORK LEGALIZATION WITH GRID CONSTRAINTS FOR HIERARCHICAL DESIGNS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2010
|
Application #:
|
11279934
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Filing Dt:
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04/17/2006
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Publication #:
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Pub Dt:
|
10/18/2007
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE
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Patent #:
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|
Issue Dt:
|
09/11/2007
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Application #:
|
11279962
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Filing Dt:
|
04/17/2006
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Title:
|
WELL ISOLATION TRENCHES (WIT) FOR CMOS DEVICES
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Patent #:
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|
Issue Dt:
|
07/28/2009
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Application #:
|
11281032
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Filing Dt:
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11/17/2005
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Publication #:
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Pub Dt:
|
06/29/2006
| | | | |
Title:
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DEPOSITION OF HAFNIUM OXIDE AND/OR ZIRCONIUM OXIDE AND FABRICATION OF PASSIVATED ELECTRONIC STRUCTURES
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|
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Patent #:
|
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Issue Dt:
|
04/14/2009
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Application #:
|
11281196
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Filing Dt:
|
11/16/2005
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Publication #:
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Pub Dt:
|
07/19/2007
| | | | |
Title:
|
PLUG-IN PROBLEM RELIEF ACTUATORS
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Patent #:
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Issue Dt:
|
04/08/2008
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Application #:
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11281688
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Filing Dt:
|
11/17/2005
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Publication #:
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Pub Dt:
|
05/17/2007
| | | | |
Title:
|
PRINTED CIRCUIT BOARD AND CHIP MODULE
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Patent #:
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|
Issue Dt:
|
06/22/2010
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Application #:
|
11282041
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Filing Dt:
|
11/17/2005
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Publication #:
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Pub Dt:
|
05/17/2007
| | | | |
Title:
|
CIRCUIT ON A PRINTED CIRCUIT BOARD
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|
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Patent #:
|
|
Issue Dt:
|
11/20/2007
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Application #:
|
11283882
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Filing Dt:
|
11/22/2005
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Publication #:
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Pub Dt:
|
04/06/2006
| | | | |
Title:
|
METHOD FOR REDUCED N+ DIFFUSION IN STRAINED SI ON SIGE SUBSTRATE
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11284358
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Filing Dt:
|
11/21/2005
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Publication #:
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Pub Dt:
|
05/24/2007
| | | | |
Title:
|
Water castable-water strippable top coats for 193 nm immersion lithography
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|
|
Patent #:
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|
Issue Dt:
|
11/16/2010
|
Application #:
|
11285338
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Filing Dt:
|
11/22/2005
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Publication #:
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Pub Dt:
|
05/24/2007
| | | | |
Title:
|
SATISFIABILITY (SAT) BASED BOUNDED MODEL CHECKERS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2009
|
Application #:
|
11286582
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Filing Dt:
|
11/25/2005
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Publication #:
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|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
DATA STORAGE SYSTEMS
|
|
|
Patent #:
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|
Issue Dt:
|
06/10/2008
|
Application #:
|
11289066
|
Filing Dt:
|
11/29/2005
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Publication #:
|
|
Pub Dt:
|
05/31/2007
| | | | |
Title:
|
GENERATION OF HARDWARE THERMAL PROFILES FOR A SET OF PROCESSORS
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|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11293774
|
Filing Dt:
|
12/02/2005
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Publication #:
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|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
ULTRA-THIN, HIGH QUALITY STRAINED SILICON-ON-INSULATOR FORMED BY ELASTIC STRAIN TRANSFER
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11293990
|
Filing Dt:
|
12/05/2005
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
Fabrication of semiconductor dies with micro-pins and structures produced therewith
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
11295936
|
Filing Dt:
|
12/07/2005
|
Publication #:
|
|
Pub Dt:
|
06/07/2007
| | | | |
Title:
|
CLOCK-GATING THROUGH DATA INDEPENDENT LOGIC
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11296780
|
Filing Dt:
|
12/07/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
Method of achieving timing closure in digital integrated circuits by optimizing individual macros
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2008
|
Application #:
|
11297308
|
Filing Dt:
|
12/08/2005
|
Publication #:
|
|
Pub Dt:
|
06/14/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR PERFORMING TEMPORAL CHECKING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
11297730
|
Filing Dt:
|
12/08/2005
|
Publication #:
|
|
Pub Dt:
|
06/14/2007
| | | | |
Title:
|
METHODS AND APPARATUS FOR INLINE VARIABILITY MEASUREMENT OF INTEGRATED CIRCUIT COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
11298800
|
Filing Dt:
|
12/09/2005
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
Title:
|
OUT OF THE BOX VERTICAL TRANSISTOR FOR EDRAM ON SOI
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|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11299497
|
Filing Dt:
|
12/12/2005
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
DATABASE MINING METHOD AND COMPUTER READABLE MEDIUM CARRYING INSTRUCTIONS FOR COVERAGE ANALYSIS OF FUNCTIONAL VERIFICATION OF INTEGRATED CIRCUIT DESIGNS
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|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
11299682
|
Filing Dt:
|
12/13/2005
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND METHOD HAVING MULTIPLE SUBCOLLECTORS FORMED ON A COMMON WAFER
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|
|
Patent #:
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|
Issue Dt:
|
03/24/2009
|
Application #:
|
11301112
|
Filing Dt:
|
12/12/2005
|
Publication #:
|
|
Pub Dt:
|
06/14/2007
| | | | |
Title:
|
EXTENDING INCREMENTAL VERIFICATION OF CIRCUIT DESIGN TO ENCOMPASS VERIFICATION RESTRAINTS
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|
|
Patent #:
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|
Issue Dt:
|
08/04/2009
|
Application #:
|
11303715
|
Filing Dt:
|
12/16/2005
|
Publication #:
|
|
Pub Dt:
|
06/21/2007
| | | | |
Title:
|
DUAL METAL GATE SELF-ALIGNED INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
11303792
|
Filing Dt:
|
12/16/2005
|
Publication #:
|
|
Pub Dt:
|
06/21/2007
| | | | |
Title:
|
SYSTEM AND METHOD OF CRITICALITY PREDICTION IN STATISTICAL TIMING ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
11304799
|
Filing Dt:
|
12/14/2005
|
Publication #:
|
|
Pub Dt:
|
06/14/2007
| | | | |
Title:
|
METHOD AND SYSTEM FOR PERFORMING CHARACTER-BASED STREAMING OF MIXED-BYTE ENCODED DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2008
|
Application #:
|
11304955
|
Filing Dt:
|
12/15/2005
|
Publication #:
|
|
Pub Dt:
|
06/21/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR DIFFUSION BASED CELL PLACEMENT MIGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2010
|
Application #:
|
11305584
|
Filing Dt:
|
12/16/2005
|
Publication #:
|
|
Pub Dt:
|
06/21/2007
| | | | |
Title:
|
FORMATION OF RAISED SOURCE/DRAIN STRUCTURES IN NFET WITH EMBEDDED SIGE IN PFET
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
11306597
|
Filing Dt:
|
01/04/2006
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
ELECTRICAL FUSES COMPRISING THIN FILM TRANSISTORS (TFTS), AND METHODS FOR PROGRAMMING SAME
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|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
11306669
|
Filing Dt:
|
01/06/2006
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
TRENCH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
11306670
|
Filing Dt:
|
01/06/2006
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
TRANSISTORS WITH GATE STACKS HAVING METAL ELECTRODES
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|
|
Patent #:
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|
Issue Dt:
|
09/22/2009
|
Application #:
|
11306708
|
Filing Dt:
|
01/09/2006
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
RETICLE STORAGE POD (RSP) TRANSPORT SYSTEM UTILIZING FOUP ADAPTER PLATE
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|
|
Patent #:
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|
Issue Dt:
|
07/14/2009
|
Application #:
|
11306709
|
Filing Dt:
|
01/09/2006
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE INCLUDING TRENCH CAPACITOR AND TRENCH RESISTOR
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|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
11306716
|
Filing Dt:
|
01/09/2006
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE STRUCTURE HAVING LOW AND HIGH PERFORMANCE DEVICES OF SAME CONDUCTIVE TYPE ON SAME SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2008
|
Application #:
|
11306719
|
Filing Dt:
|
01/09/2006
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
AIR BREAK FOR IMPROVED SILICIDE FORMATION WITH COMPOSITE CAPS
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|
|
Patent #:
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|
Issue Dt:
|
08/31/2010
|
Application #:
|
11306720
|
Filing Dt:
|
01/09/2006
|
Publication #:
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|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
PROBE TIP CLEANING APPARATUS AND METHOD OF USE
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|
|
Patent #:
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|
Issue Dt:
|
01/04/2011
|
Application #:
|
11306721
|
Filing Dt:
|
01/09/2006
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
METHOD OF FORMING A CROSS-SECTION HOURGLASS SHAPED CHANNEL REGION FOR CHARGE CARRIER MOBILITY MODIFICATION
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|
|
Patent #:
|
|
Issue Dt:
|
09/08/2009
|
Application #:
|
11306746
|
Filing Dt:
|
01/10/2006
|
Publication #:
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|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
INTEGRATED CIRCUIT COMB CAPACITOR
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|
|
Patent #:
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|
Issue Dt:
|
03/17/2009
|
Application #:
|
11306748
|
Filing Dt:
|
01/10/2006
|
Publication #:
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|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
CMOS WITH DUAL METAL GATE
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|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
11306749
|
Filing Dt:
|
01/10/2006
|
Publication #:
|
|
Pub Dt:
|
08/16/2007
| | | | |
Title:
|
METHOD OF MANUFACTURING A MULTIPLE PORT MEMORY HAVING A PLURALITY OF PARALLEL CONNECTED TRENCH CAPACITORS IN A CELL
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|
|
Patent #:
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|
Issue Dt:
|
03/10/2009
|
Application #:
|
11306750
|
Filing Dt:
|
01/10/2006
|
Publication #:
|
|
Pub Dt:
|
09/20/2007
| | | | |
Title:
|
MULTILAYER OPC FOR DESIGN AWARE MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
11306825
|
Filing Dt:
|
01/12/2006
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
METHOD TO IMPROVE TIME DEPENDENT DIELECTRIC BREAKDOWN
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
11306827
|
Filing Dt:
|
01/12/2006
|
Publication #:
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|
Pub Dt:
|
07/26/2007
| | | | |
Title:
|
METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING
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|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
11306930
|
Filing Dt:
|
01/17/2006
|
Publication #:
|
|
Pub Dt:
|
07/19/2007
| | | | |
Title:
|
METHOD OF MAKING A SEMICONDUCTOR STRUCTURE WITH A PLATING ENHANCEMENT LAYER
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|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
11306932
|
Filing Dt:
|
01/17/2006
|
Publication #:
|
|
Pub Dt:
|
07/19/2007
| | | | |
Title:
|
METHOD FOR DIRECT ELECTROPLATING OF COPPER ONTO A NON-COPPER PLATEABLE LAYER
|
|