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11/08/2011
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11842206
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08/21/2007
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02/26/2009
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06/22/2010
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11842437
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08/21/2007
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02/26/2009
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SELF-ALIGNED SUPER STRESSED PFET
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06/07/2011
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11842515
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08/21/2007
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02/26/2009
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METHODS FOR NORMALIZING ERROR IN PHOTOLITHOGRAPHIC PROCESSES
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04/15/2008
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11842533
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08/21/2007
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12/13/2007
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07/27/2010
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11843358
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08/22/2007
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07/31/2008
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TRANSISTOR WITH EMBEDDED SILICON/GERMANIUM MATERIAL ON A STRAINED SEMICONDUCTOR ON INSULATOR SUBSTRATE
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08/23/2011
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11843434
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08/22/2007
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02/26/2009
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OPTIMAL SOLUTION TO CONTROL DATA CHANNELS
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01/10/2012
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11843784
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08/23/2007
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09/07/2010
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11843791
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08/23/2007
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02/26/2009
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06/14/2011
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11844109
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08/23/2007
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12/20/2007
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11/19/2013
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11844397
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08/24/2007
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02/26/2009
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ON CHIP SHIELDING STRUCTURE FOR INTEGRATED CIRCUITS OR DEVICES ON A SUBSTRATE AND METHOD OF SHIELDING
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06/21/2011
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11844587
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08/24/2007
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02/26/2009
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ENHANCED MAGNETIC PLATING METHOD
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05/27/2008
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11844831
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08/24/2007
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02/07/2008
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PRECURSORS TO FLUOROALKANOL-CONTAINING OLEFIN MONOMERS, AND ASSOCIATED METHODS OF SYNTHESIS AND USE
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04/07/2009
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11845386
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08/27/2007
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03/05/2009
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SRAM HAVING ACTIVE WRITE ASSIST FOR IMPROVED OPERATIONAL MARGINS
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10/04/2011
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11845852
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08/28/2007
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07/31/2008
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A DESIGN STRUCTURE FOR AN INTEGRATED CIRCUIT DESIGN FOR REDUCING COUPLING BETWEEN WIRES OF AN ELECTRONIC CIRCUIT
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11/04/2008
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11845888
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08/28/2007
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12/20/2007
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DEVICE HAVING DUAL ETCH STOP LINER AND PROTECTIVE LAYER
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07/27/2010
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11846544
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08/29/2007
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12/20/2007
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METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING
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11/09/2010
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11846578
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08/29/2007
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01/31/2008
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METHOD AND ARCHITECTURE FOR POWER MANAGEMENT OF AN ELECTRONIC DEVICE
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06/03/2008
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11846595
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08/29/2007
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12/20/2007
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INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT
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04/12/2011
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11847203
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08/29/2007
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12/27/2007
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Title:
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METHOD AND STRUCTURE TO ISOLATE A QUBIT FROM THE ENVIRONMENT
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12/14/2010
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11847379
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08/30/2007
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09/23/2010
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Title:
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METHODS AND SYSTEMS INVOLVING ELECTRICALLY PROGRAMMABLE FUSES
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12/16/2008
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11847384
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08/30/2007
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12/20/2007
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Title:
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A METHOD OF FORMING A SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK
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12/14/2010
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11847391
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08/30/2007
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01/03/2008
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Title:
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TRANSIENT SIMULATION USING ADAPTIVE PIECEWISE CONSTANT MODEL
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09/30/2008
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11848470
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08/31/2007
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08/07/2008
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Title:
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DESIGN STRUCTURE FOR A FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH
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02/08/2011
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11848599
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08/31/2007
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03/05/2009
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LOW-POWER, LOW-AREA HIGH-SPEED RECEIVER ARCHITECTURE
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09/22/2009
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11849048
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08/31/2007
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02/14/2008
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DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES
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11/02/2010
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11849346
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09/03/2007
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12/27/2007
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EFFICIENT ELECTROMAGNETIC MODELING OF IRREGULAR METAL PLANES
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11/30/2010
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11849409
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09/04/2007
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03/05/2009
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WIRE BOND PADS
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07/19/2011
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11849452
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09/04/2007
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03/05/2009
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SYSTEM AND METHOD FOR PROVIDING DRAM DEVICE-LEVEL REPAIR VIA ADDRESS REMAPPINGS EXTERNAL TO THE DEVICE
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05/04/2010
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11849702
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09/04/2007
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03/05/2009
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METHOD AND APPARATUS FOR RELATIVE TESTING OF INTEGRATED CIRCUIT DEVICES
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08/24/2010
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11849908
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09/04/2007
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01/10/2008
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Title:
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SYSTEM AND METHOD FOR CREATING A STANDARD CELL LIBRARY FOR USE IN CIRCUIT DESIGNS
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10/19/2010
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11850076
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09/05/2007
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12/27/2007
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FIELD EFFECT TRANSISTORS (FETS) WITH MULTIPLE AND/OR STAIRCASE SILICIDE
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11/02/2010
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11850427
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09/05/2007
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03/05/2009
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METHOD FOR INTEGRATION OF MAGNETIC RANDOM ACCESS MEMORIES WITH IMPROVED LITHOGRAPHIC ALIGNMENT TO MAGNETIC TUNNEL JUNCTIONS
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11/02/2010
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11850488
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09/05/2007
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03/05/2009
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Title:
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THRESHOLD VOLTAGE COMPENSATION FOR PIXEL DESIGN OF CMOS IMAGE SENSORS
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09/14/2010
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11850608
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09/05/2007
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03/05/2009
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Title:
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NANOWIRE FIELD-EFFECT TRANSISTORS
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05/19/2009
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11850644
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09/05/2007
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03/05/2009
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Title:
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TECHNIQUES FOR FABRICATING NANOWIRE FIELD-EFFECT TRANSISTORS
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12/15/2009
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11850742
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09/06/2007
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03/12/2009
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Title:
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PROGRAMMABLE FUSE/NON-VOLATILE MEMORY STRUCTURES IN BEOL REGIONS USING EXTERNALLY HEATED PHASE CHANGE MATERIAL
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12/09/2008
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11850840
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09/06/2007
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03/06/2008
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Title:
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DESIGN STRUCTURE FOR CONTENT ADDRESSABLE MEMORY
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02/08/2011
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11850916
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09/06/2007
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12/25/2008
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Title:
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METHOD FOR IMPROVING THE SELECTIVITY OF A CVD PROCESS
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04/19/2011
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11850968
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09/06/2007
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Pub Dt:
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12/27/2007
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Title:
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DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND RELATED METHODS
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02/22/2011
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11851123
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09/06/2007
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Pub Dt:
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02/14/2008
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DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES
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03/08/2011
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11851128
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09/06/2007
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02/14/2008
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Title:
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STRUCTURE FOR POWER-EFFICIENT CACHE MEMORY
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Issue Dt:
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11/23/2010
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11851138
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09/06/2007
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Pub Dt:
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07/17/2008
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Title:
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DESIGN STRUCTURE FOR LOW VOLTAGE APPLICATIONS IN AN INTEGRATED CIRCUIT
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08/04/2009
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11851464
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09/07/2007
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12/27/2007
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Title:
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HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING
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11/08/2011
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11851858
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09/07/2007
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03/12/2009
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STRUCTURES HAVING LATTICE-MISMATCHED SINGLE-CRYSTALLINE SEMICONDUCTOR LAYERS ON THE SAME LITHOGRAPHIC LEVEL AND METHODS OF MANUFACTURING THE SAME
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05/11/2010
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11852317
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09/09/2007
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01/24/2008
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Title:
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SEMICONDUCTOR DEVICE WITH A HIGH THERMAL DISSIPATION EFFICIENCY
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05/10/2011
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11852353
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09/10/2007
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03/12/2009
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METHOD AND STRUCTURES FOR ACCELERATED SOFT-ERROR TESTING
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08/02/2011
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11852493
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09/10/2007
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03/12/2009
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Title:
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TACTILE SURFACE INSPECTION DURING DEVICE FABRICATION OR ASSEMBLY
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04/05/2011
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11852906
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09/10/2007
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03/12/2009
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DIELECTRIC SPACER REMOVAL
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06/17/2008
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11853040
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09/11/2007
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12/27/2007
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Title:
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STRUCTURE AND METHOD FOR ACCURATE DEEP TRENCH RESISTANCE MEASUREMENT
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08/05/2008
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11853045
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09/11/2007
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12/27/2007
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Title:
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STRUCTURE AND METHOD FOR ACCURATE DEEP TRENCH RESISTANCE MEASUREMENT
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03/16/2010
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11853122
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09/11/2007
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Pub Dt:
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03/12/2009
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Title:
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SEMICONDUCTOR CHIP WITH CRACK STOP
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Issue Dt:
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08/23/2011
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11853170
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09/11/2007
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Pub Dt:
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03/12/2009
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SYSTEM AND METHOD FOR TESTING MULTIPLE PROCESSOR MODES FOR PROCESSOR DESIGN VERIFICATION AND VALIDATION
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06/07/2011
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11853284
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09/11/2007
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Pub Dt:
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03/12/2009
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Title:
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FULL SILICIDE GATE FOR CMOS
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Issue Dt:
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08/10/2010
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11853304
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Filing Dt:
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09/11/2007
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Pub Dt:
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03/12/2009
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Title:
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METHOD AND APPARATUS FOR DYNAMICALLY DETERMINING TESTER RECIPES
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12/07/2010
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11854035
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Filing Dt:
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09/12/2007
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Pub Dt:
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03/12/2009
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Title:
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EMERGENCY MACHINE OFF FEATURE WITH SAFETY CONTROL INTERFACE
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Issue Dt:
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01/04/2011
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11855325
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09/14/2007
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Pub Dt:
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02/21/2008
| | | | |
Title:
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PLANAR ARRAY CONTACT MEMORY CARDS
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Issue Dt:
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03/08/2011
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11855345
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Filing Dt:
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09/14/2007
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Pub Dt:
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03/19/2009
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Title:
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METHOD AND APPARATUS FOR SCHEDULING TEST VECTORS IN A MULTIPLE CORE INTEGRATED CIRCUIT
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Issue Dt:
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09/16/2008
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11855507
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Filing Dt:
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09/14/2007
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Pub Dt:
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01/03/2008
| | | | |
Title:
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SELECTIVE SHIELD/MATERIAL FLOW MECHANISM
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Patent #:
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Issue Dt:
|
01/05/2010
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Application #:
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11855979
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Filing Dt:
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09/14/2007
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Publication #:
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Pub Dt:
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03/19/2009
| | | | |
Title:
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PHASE CHANGE MEMORY CELL IN VIA ARRAY WITH SELF-ALIGNED, SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING
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Patent #:
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Issue Dt:
|
05/15/2012
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Application #:
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11855983
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Filing Dt:
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09/14/2007
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Publication #:
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Pub Dt:
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03/19/2009
| | | | |
Title:
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PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING
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Patent #:
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Issue Dt:
|
11/16/2010
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Application #:
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11856033
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Filing Dt:
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09/15/2007
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Title:
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METHOD FOR DECREASING SURFACE DELAMINATION OF GEL-TYPE THERMAL INTERFACE MATERIAL BY MANAGEMENT OF THE MATERIAL CURE TEMPERATURE
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Patent #:
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Issue Dt:
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04/05/2011
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Application #:
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11856335
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Filing Dt:
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09/17/2007
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Publication #:
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Pub Dt:
|
03/19/2009
| | | | |
Title:
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METHOD OF ELECTRODEPOSITING GERMANIUM COMPOUND MATERIALS ON A SUBSTRATE
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Patent #:
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Issue Dt:
|
08/31/2010
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Application #:
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11856799
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Filing Dt:
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09/18/2007
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Publication #:
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Pub Dt:
|
07/03/2008
| | | | |
Title:
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INLINE STRESS EVALUATION IN MICROSTRUCTURE DEVICES
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Patent #:
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Issue Dt:
|
04/03/2012
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Application #:
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11856831
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Filing Dt:
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09/18/2007
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Publication #:
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Pub Dt:
|
03/19/2009
| | | | |
Title:
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TECHNIQUES FOR FORMING SOLDER BUMP INTERCONNECTS
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Patent #:
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Issue Dt:
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10/27/2009
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Application #:
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11857272
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Filing Dt:
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09/18/2007
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Publication #:
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Pub Dt:
|
03/19/2009
| | | | |
Title:
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INTEGRATED CIRCUIT TESTER INFORMATION PROCESSING SYSTEM
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Patent #:
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Issue Dt:
|
07/27/2010
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Application #:
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11857321
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Filing Dt:
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09/18/2007
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Publication #:
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Pub Dt:
|
03/19/2009
| | | | |
Title:
|
MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION
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Patent #:
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Issue Dt:
|
07/28/2009
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Application #:
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11857332
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Filing Dt:
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09/18/2007
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Publication #:
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Pub Dt:
|
03/19/2009
| | | | |
Title:
|
MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION
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Patent #:
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Issue Dt:
|
02/15/2011
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Application #:
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11857596
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Filing Dt:
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09/19/2007
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Publication #:
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Pub Dt:
|
05/28/2009
| | | | |
Title:
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APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES
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Patent #:
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Issue Dt:
|
05/27/2008
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Application #:
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11857632
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Filing Dt:
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09/19/2007
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Publication #:
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Pub Dt:
|
01/10/2008
| | | | |
Title:
|
PROGRAMMABLE LOW-POWER HIGH-FREQUENCY DIVIDER
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Patent #:
|
|
Issue Dt:
|
02/24/2015
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Application #:
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11857806
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Filing Dt:
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09/19/2007
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Publication #:
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Pub Dt:
|
01/10/2008
| | | | |
Title:
|
DENSE CHEVRON finFET AND METHOD OF MANUFACTURING SAME
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Patent #:
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|
Issue Dt:
|
01/11/2011
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Application #:
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11858166
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Filing Dt:
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09/20/2007
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Publication #:
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Pub Dt:
|
03/26/2009
| | | | |
Title:
|
METHOD OF FABRICATING IMPROVED INTERCONNECT STRUCTURE WITH A VIA GOUGING FEATURE ABSENT PROFILE DAMAGE TO THE INTERCONNECT DIELECTRIC
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Patent #:
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Issue Dt:
|
05/04/2010
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Application #:
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11858615
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Filing Dt:
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09/20/2007
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Publication #:
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Pub Dt:
|
03/26/2009
| | | | |
Title:
|
SPIN-ON ANTIREFLECTIVE COATING FOR INTEGRATION OF PATTERNABLE DIELECTRIC MATERIALS AND INTERCONNECT STRUCTURES
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Patent #:
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Issue Dt:
|
12/27/2011
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Application #:
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11858624
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Filing Dt:
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09/20/2007
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Publication #:
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Pub Dt:
|
03/26/2009
| | | | |
Title:
|
INTERCONNECT STRUCTURES WITH PATTERNABLE LOW-K DIELECTRICS AND METHOD OF FABRICATING SAME
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Patent #:
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Issue Dt:
|
12/31/2013
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Application #:
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11858636
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Filing Dt:
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09/20/2007
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Publication #:
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Pub Dt:
|
03/26/2009
| | | | |
Title:
|
PATTERNABLE DIELECTRIC FILM STRUCTURE WITH IMPROVED LITHOGRAPHY AND METHOD OF FABRICATING SAME
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Patent #:
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Issue Dt:
|
12/25/2012
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Application #:
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11859044
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Filing Dt:
|
09/21/2007
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Publication #:
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Pub Dt:
|
03/26/2009
| | | | |
Title:
|
TECHNIQUES FOR ACCESSING A RESOURCE IN A PROCESSOR SYSTEM
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Patent #:
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|
Issue Dt:
|
01/25/2011
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Application #:
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11859351
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Filing Dt:
|
09/21/2007
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Publication #:
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Pub Dt:
|
12/10/2009
| | | | |
Title:
|
DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC
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Patent #:
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Issue Dt:
|
03/18/2014
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Application #:
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11859423
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Filing Dt:
|
09/21/2007
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Publication #:
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|
Pub Dt:
|
03/26/2009
| | | | |
Title:
|
SYSTEM AND METHOD FOR CONTROLLING VIDEO INPUTS TO A COMPUTER
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Patent #:
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Issue Dt:
|
03/02/2010
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Application #:
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11859865
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Filing Dt:
|
09/24/2007
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Publication #:
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|
Pub Dt:
|
01/10/2008
| | | | |
Title:
|
SOI DEVICE WITH REDUCED JUNCTION CAPACITANCE
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Patent #:
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Issue Dt:
|
11/23/2010
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Application #:
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11860226
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Filing Dt:
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09/24/2007
|
Publication #:
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|
Pub Dt:
|
03/26/2009
| | | | |
Title:
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METHOD AND STRUCTURE FOR DISPENSING CHIP UNDERFILL THROUGH AN OPENING IN THE CHIP
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Patent #:
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Issue Dt:
|
02/22/2011
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Application #:
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11860459
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Filing Dt:
|
09/24/2007
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Publication #:
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|
Pub Dt:
|
01/20/2011
| | | | |
Title:
|
METHODS OF MANUFACTURE OF VERTICAL NANOWIRE FET DEVICES
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Patent #:
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Issue Dt:
|
07/27/2010
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Application #:
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11860613
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Filing Dt:
|
09/25/2007
|
Publication #:
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Pub Dt:
|
03/26/2009
| | | | |
Title:
|
STRESS RELIEF STRUCTURES FOR SILICON INTERPOSERS
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Patent #:
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Issue Dt:
|
02/14/2012
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Application #:
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11860851
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Filing Dt:
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09/25/2007
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Publication #:
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|
Pub Dt:
|
03/26/2009
| | | | |
Title:
|
SEMICONDUCTOR-ON-INSULATOR STRUCTURES INCLUDING A TRENCH CONTAINING AN INSULATOR STRESSOR PLUG AND METHOD OF FABRICATING SAME
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Patent #:
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|
Issue Dt:
|
12/29/2009
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Application #:
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11861051
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Filing Dt:
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09/25/2007
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Publication #:
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Pub Dt:
|
03/26/2009
| | | | |
Title:
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STRESS ENHANCED SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING SAME
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Patent #:
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Issue Dt:
|
07/20/2010
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Application #:
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11861492
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Filing Dt:
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09/26/2007
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Publication #:
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Pub Dt:
|
03/26/2009
| | | | |
Title:
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METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EXTENDED STRESS LINER
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Patent #:
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Issue Dt:
|
08/23/2011
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Application #:
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11861614
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Filing Dt:
|
09/26/2007
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Publication #:
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Pub Dt:
|
03/26/2009
| | | | |
Title:
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SHALLOW TRENCH ISOLATION STRUCTURE COMPATIBLE WITH SOI EMBEDDED DRAM
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Patent #:
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Issue Dt:
|
03/13/2012
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Application #:
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11861928
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Filing Dt:
|
09/26/2007
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Publication #:
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Pub Dt:
|
03/26/2009
| | | | |
Title:
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SEMICONDUCTOR DEVICE HAVING DECREASED CONTACT RESISTANCE
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Patent #:
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Issue Dt:
|
06/07/2011
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Application #:
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11862255
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Filing Dt:
|
09/27/2007
|
Publication #:
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Pub Dt:
|
01/24/2008
| | | | |
Title:
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PHOTORESIST TRIMMING PROCESS
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Patent #:
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Issue Dt:
|
04/20/2010
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Application #:
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11862345
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Filing Dt:
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09/27/2007
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Publication #:
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Pub Dt:
|
07/31/2008
| | | | |
Title:
|
METHOD FOR REDUCING ETCH-INDUCED PROCESS UNIFORMITIES BY OMITTING DEPOSITION OF AN ENDPOINT DETECTION LAYER DURING PATTERNING OF STRESSED OVERLAYERS IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
11/02/2010
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Application #:
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11862540
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Filing Dt:
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09/27/2007
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Publication #:
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Pub Dt:
|
04/02/2009
| | | | |
Title:
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SLIP RING POSITIVE Z FORCE LIQUID ISOLATION FIXTURE PERMITTING ZERO NET FORCE ON WORKPIECE
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Patent #:
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Issue Dt:
|
11/16/2010
|
Application #:
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11862545
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Filing Dt:
|
09/27/2007
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Publication #:
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Pub Dt:
|
10/23/2008
| | | | |
Title:
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PRINTED CIRCUIT BOARD MANUFACTURING METHOD AND PRINTED CIRCUIT BOARD
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Patent #:
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Issue Dt:
|
02/15/2011
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Application #:
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11863502
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Filing Dt:
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09/28/2007
|
Publication #:
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Pub Dt:
|
04/02/2009
| | | | |
Title:
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COPPER CONTAMINATION DETECTION METHOD AND SYSTEM FOR MONITORING COPPER CONTAMINATION
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Patent #:
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Issue Dt:
|
06/07/2011
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Application #:
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11863623
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Filing Dt:
|
09/28/2007
|
Publication #:
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|
Pub Dt:
|
04/02/2009
| | | | |
Title:
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COPPER CONTAMINATION DETECTION METHOD AND SYSTEM FOR MONITORING COPPER CONTAMINATION
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Patent #:
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Issue Dt:
|
11/02/2010
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Application #:
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11863724
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Filing Dt:
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09/28/2007
|
Publication #:
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|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
STRUCTURES AND METHODS FOR REDUCTION OF PARASITIC CAPACITANCES IN SEMICONDUCTOR INTEGRATED CIRCUITS
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Patent #:
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|
Issue Dt:
|
09/06/2011
|
Application #:
|
11863757
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Filing Dt:
|
09/28/2007
|
Publication #:
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Pub Dt:
|
10/02/2008
| | | | |
Title:
|
HIGH MOBILITY CMOS CIRCUITS
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|
Patent #:
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Issue Dt:
|
07/17/2012
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Application #:
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11863759
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Filing Dt:
|
09/28/2007
|
Publication #:
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|
Pub Dt:
|
04/02/2009
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
04/22/2008
|
Application #:
|
11865217
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Filing Dt:
|
10/01/2007
|
Publication #:
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|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
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Patent #:
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Issue Dt:
|
05/27/2008
|
Application #:
|
11865231
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Filing Dt:
|
10/01/2007
|
Publication #:
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|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
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|
Patent #:
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Issue Dt:
|
09/13/2011
|
Application #:
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11865252
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Filing Dt:
|
10/01/2007
|
Publication #:
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Pub Dt:
|
04/02/2009
| | | | |
Title:
|
LAYOUT QUALITY GAUGE FOR INTEGRATED CIRCUIT DESIGN
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|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
11865253
|
Filing Dt:
|
10/01/2007
|
Publication #:
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|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
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|
|
Patent #:
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Issue Dt:
|
04/08/2008
|
Application #:
|
11865293
|
Filing Dt:
|
10/01/2007
|
Publication #:
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|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|