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Patent #:
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Issue Dt:
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07/22/2008
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Application #:
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11865305
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Filing Dt:
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10/01/2007
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Publication #:
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Pub Dt:
|
02/07/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
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Patent #:
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Issue Dt:
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05/20/2008
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Application #:
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11865395
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Filing Dt:
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10/01/2007
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Publication #:
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|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
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Patent #:
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Issue Dt:
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04/22/2008
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Application #:
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11865423
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Filing Dt:
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10/01/2007
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Publication #:
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Pub Dt:
|
01/24/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
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Patent #:
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Issue Dt:
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04/22/2008
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Application #:
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11865440
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Filing Dt:
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10/01/2007
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Publication #:
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|
Pub Dt:
|
01/31/2008
| | | | |
Title:
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LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
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Patent #:
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Issue Dt:
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06/14/2011
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Application #:
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11865728
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Filing Dt:
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10/01/2007
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Publication #:
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Pub Dt:
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01/24/2008
| | | | |
Title:
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METHOD AND APPARATUS FOR MANUFACTURING DIAMOND SHAPED CHIPS
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Patent #:
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Issue Dt:
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07/10/2012
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11865780
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Filing Dt:
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10/02/2007
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Publication #:
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Pub Dt:
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12/10/2009
| | | | |
Title:
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HIGH DENSITY STABLE STATIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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12/16/2008
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Application #:
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11865797
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Filing Dt:
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10/02/2007
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Publication #:
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Pub Dt:
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02/07/2008
| | | | |
Title:
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DETERMINING FLEET MATCHING PROBLEM AND ROOT CAUSE ISSUE FOR MEASUREMENT SYSTEM
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Patent #:
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Issue Dt:
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02/22/2011
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11865982
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Filing Dt:
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10/02/2007
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Publication #:
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Pub Dt:
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04/02/2009
| | | | |
Title:
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PHOTOMASK AND METHOD OF MAKING THEREOF
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Patent #:
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Issue Dt:
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02/23/2010
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11866060
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Filing Dt:
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10/02/2007
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Publication #:
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Pub Dt:
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04/02/2009
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Title:
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METHOD AND APPARATUS FOR RANDOMIZING DISPATCH ORDER FOR SINGLE WAFER PROCESSING
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Patent #:
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Issue Dt:
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11/13/2012
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11866110
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Filing Dt:
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10/02/2007
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Publication #:
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Pub Dt:
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03/20/2008
| | | | |
Title:
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RATIOED FEEDBACK BODY VOLTAGE BIAS GENERATOR
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Patent #:
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Issue Dt:
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01/06/2009
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11866435
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Filing Dt:
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10/03/2007
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Publication #:
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Pub Dt:
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04/17/2008
| | | | |
Title:
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CORNER DOMINATED TRIGATE FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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08/30/2011
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11866455
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Filing Dt:
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10/03/2007
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Pub Dt:
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04/09/2009
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Title:
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METHODS FOR FABRICATING CONTACTS TO PILLAR STRUCTURES IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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05/10/2011
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Application #:
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11866461
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Filing Dt:
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10/03/2007
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Publication #:
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Pub Dt:
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08/28/2008
| | | | |
Title:
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SEMICONDUCTOR DEVICE HAVING A STRAINED SEMICONDUCTOR ALLOY CONCENTRATION PROFILE
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Patent #:
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Issue Dt:
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03/02/2010
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Application #:
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11866502
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Filing Dt:
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10/03/2007
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Publication #:
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Pub Dt:
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04/09/2009
| | | | |
Title:
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CIRCUITS AND METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS
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Patent #:
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Issue Dt:
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03/06/2012
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11867235
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Filing Dt:
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10/04/2007
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Publication #:
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Pub Dt:
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04/09/2009
| | | | |
Title:
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FABRICATION OF SOI WITH GETTERING LAYER
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Patent #:
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Issue Dt:
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03/29/2011
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11867428
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Filing Dt:
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10/04/2007
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Publication #:
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Pub Dt:
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04/09/2009
| | | | |
Title:
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MIXED LITHOGRAPHY WITH DUAL RESIST AND A SINGLE PATTERN TRANSFER
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Patent #:
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Issue Dt:
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04/01/2014
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11867743
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Filing Dt:
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10/05/2007
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Publication #:
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Pub Dt:
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04/09/2009
| | | | |
Title:
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ELECTRONIC DEVICE AND METHOD OF BIASING
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Patent #:
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Issue Dt:
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04/13/2010
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Application #:
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11867840
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Filing Dt:
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10/05/2007
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Publication #:
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Pub Dt:
|
11/20/2008
| | | | |
Title:
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SIDEWALL SEMICONDUCTOR TRANSISTORS
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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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11867995
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Filing Dt:
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10/05/2007
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Publication #:
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Pub Dt:
|
01/01/2009
| | | | |
Title:
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STRUCTURES AND METHODS OF FORMING SIGE AND SIGEC BURIED LAYER FOR SOI/SIGE TECHNOLOGY
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Patent #:
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Issue Dt:
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04/28/2009
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Application #:
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11868046
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Filing Dt:
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10/05/2007
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Publication #:
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Pub Dt:
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01/31/2008
| | | | |
Title:
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METHOD FOR IMPROVING SENSING MARGIN OF ELECTRICALLY PROGRAMMABLE FUSES
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Patent #:
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Issue Dt:
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12/21/2010
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Application #:
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11868320
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Filing Dt:
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10/05/2007
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Publication #:
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Pub Dt:
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01/31/2008
| | | | |
Title:
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IMMERSION TOPCOAT MATERIALS WITH IMPROVED PERFORMANCE
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Patent #:
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Issue Dt:
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02/08/2011
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Application #:
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11868789
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Filing Dt:
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10/08/2007
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Publication #:
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Pub Dt:
|
08/28/2008
| | | | |
Title:
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TECHNIQUE FOR PATTERNING DIFFERENTLY STRESSED LAYERS FORMED ABOVE TRANSISTORS BY ENHANCED ETCH CONTROL STRATEGIES
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Patent #:
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Issue Dt:
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11/30/2010
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Application #:
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11869145
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Filing Dt:
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10/09/2007
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Publication #:
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Pub Dt:
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01/22/2009
| | | | |
Title:
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ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
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Patent #:
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Issue Dt:
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01/31/2012
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Application #:
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11869178
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Filing Dt:
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10/09/2007
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Publication #:
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Pub Dt:
|
04/09/2009
| | | | |
Title:
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SELF-ASSEMBLED SIDEWALL SPACER
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Patent #:
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Issue Dt:
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10/16/2012
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Application #:
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11869179
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Filing Dt:
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10/09/2007
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Publication #:
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Pub Dt:
|
04/09/2009
| | | | |
Title:
|
AN ON-CHIP IDENTIFICATION CIRCUIT INCORPORATING PAIRS OF CONDUCTORS, EACH HAVING AN ESSENTIALLY RANDOM CHANCE OF BEING SHORTED TOGETHER AS A RESULT OF PROCESS VARIATIONS
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Patent #:
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Issue Dt:
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12/27/2011
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Application #:
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11869216
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Filing Dt:
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10/09/2007
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Publication #:
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Pub Dt:
|
01/31/2008
| | | | |
Title:
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STRUCTURE FOR DYNAMICALLY ADJUSTING PIPELINED DATA PATHS FOR IMPROVED POWER MANAGEMENT
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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11869306
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Filing Dt:
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10/09/2007
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Publication #:
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Pub Dt:
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04/09/2009
| | | | |
Title:
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METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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06/14/2011
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Application #:
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11869373
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Filing Dt:
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10/09/2007
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Publication #:
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Pub Dt:
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02/07/2008
| | | | |
Title:
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PHOTORESIST TRIMMING PROCESS
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Patent #:
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Issue Dt:
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01/17/2012
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Application #:
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11869522
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Filing Dt:
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10/09/2007
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Publication #:
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Pub Dt:
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04/09/2009
| | | | |
Title:
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TWO-STEP SIMULATION METHODOLOGY FOR AGING SIMULATIONS
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Patent #:
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Issue Dt:
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02/22/2011
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Application #:
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11869593
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Filing Dt:
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10/09/2007
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Publication #:
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Pub Dt:
|
01/31/2008
| | | | |
Title:
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SPIN-CURRENT SWITCHABLE MAGNETIC MEMORY ELEMENT AND METHOD OF FABRICATING THE MEMORY ELEMENT
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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11869841
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Filing Dt:
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10/10/2007
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Publication #:
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Pub Dt:
|
10/30/2008
| | | | |
Title:
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IMPLEMENTING APS VOLTAGE LEVEL ACTIVATION WITH SECONDARY CHIP IN STACKED-CHIP TECHNOLOGY
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Patent #:
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Issue Dt:
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06/08/2010
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11870167
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Filing Dt:
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10/10/2007
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Pub Dt:
|
04/16/2009
| | | | |
Title:
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PHOTOSENSITIVE SELF-ASSEMBLED MONOLAYER FOR SELECTIVE PLACEMENT OF HYDROPHILIC STRUCTURES
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Patent #:
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Issue Dt:
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06/17/2008
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Application #:
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11870437
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Filing Dt:
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10/11/2007
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Pub Dt:
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04/10/2008
| | | | |
Title:
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LOCAL COLLECTOR IMPLANT STRUCTURE FOR HETEROJUNCTION BIPOLAR TRANSISTORS
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Patent #:
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Issue Dt:
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02/03/2009
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Application #:
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11870463
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Filing Dt:
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10/11/2007
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Publication #:
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Pub Dt:
|
07/24/2008
| | | | |
Title:
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WAVEGUIDE POLARIZATION BEAM SPLITTERS AND METHOD OF FABRICATING A WAVEGUIDE WIRE-GRID POLARIZATION BEAM SPLITTER
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Patent #:
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Issue Dt:
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09/01/2009
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Application #:
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11870567
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Filing Dt:
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10/11/2007
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Pub Dt:
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02/14/2008
| | | | |
Title:
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SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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11870575
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Filing Dt:
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10/11/2007
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Pub Dt:
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01/22/2009
| | | | |
Title:
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STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS
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Patent #:
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Issue Dt:
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10/09/2012
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Application #:
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11870875
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Filing Dt:
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10/11/2007
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Pub Dt:
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07/19/2012
| | | | |
Title:
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SOLID STATE KLYSTRON
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Patent #:
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Issue Dt:
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02/01/2011
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Application #:
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11871179
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Filing Dt:
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10/12/2007
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Publication #:
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Pub Dt:
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04/16/2009
| | | | |
Title:
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METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR AUTOMATICALLY WAIVING NON-COMPUTE INDICATIONS FOR A TIMING ANALYSIS PROCESS
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Issue Dt:
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11/30/2010
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11871204
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Filing Dt:
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10/12/2007
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Pub Dt:
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04/16/2009
| | | | |
Title:
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SEMICONDUCTOR CHIP PACKAGES HAVING REDUCED STRESS
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Patent #:
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Issue Dt:
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05/17/2011
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Application #:
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11871713
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Filing Dt:
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10/12/2007
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Pub Dt:
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10/16/2008
| | | | |
Title:
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APPARATUS AND METHOD FOR ELECTRONIC FUSE WITH IMPROVED ESD TOLERANCE
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Patent #:
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Issue Dt:
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11/18/2008
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Application #:
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11872060
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Filing Dt:
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10/15/2007
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Publication #:
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Pub Dt:
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02/07/2008
| | | | |
Title:
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METHOD OF INSPECTING INTEGRATED CIRCUITS DURING FABRICATION
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Patent #:
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Issue Dt:
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07/29/2008
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Application #:
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11872085
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Filing Dt:
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10/15/2007
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Publication #:
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Pub Dt:
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02/14/2008
| | | | |
Title:
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METHOD AND APPARATUS FOR IN-SYSTEM REDUNDANT ARRAY REPAIR ON INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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07/08/2008
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Application #:
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11872088
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Filing Dt:
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10/15/2007
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Publication #:
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Pub Dt:
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04/03/2008
| | | | |
Title:
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METHOD AND APPARATUS FOR IN-SYSTEM REDUNDANT ARRAY REPAIR ON INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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11872168
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Filing Dt:
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10/15/2007
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Publication #:
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Pub Dt:
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04/16/2009
| | | | |
Title:
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DISPLAY OF DATA USED FOR SYSTEM PERFORMANCE ANALYSIS
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Patent #:
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Issue Dt:
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10/27/2009
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Application #:
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11872273
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Filing Dt:
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10/15/2007
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Publication #:
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Pub Dt:
|
02/07/2008
| | | | |
Title:
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DESIGN STRUCTURE FOR IMPROVING SENSING MARGIN OF ELECTRICALLY PROGRAMMABLE FUSES
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Patent #:
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Issue Dt:
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10/30/2012
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Application #:
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11872291
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Filing Dt:
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10/15/2007
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Publication #:
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Pub Dt:
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05/31/2012
| | | | |
Title:
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SEMICONDUCTOR STRUCTURES HAVING IMPROVED CONTACT RESISTANCE
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Patent #:
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Issue Dt:
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10/13/2009
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Application #:
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11872399
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Filing Dt:
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10/15/2007
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Publication #:
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Pub Dt:
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07/31/2008
| | | | |
Title:
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METHODS FOR FABRICATING DEVICE FEATURES HAVING SMALL DIMENSIONS
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Patent #:
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Issue Dt:
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02/08/2011
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Application #:
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11872731
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Filing Dt:
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10/16/2007
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Publication #:
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Pub Dt:
|
04/16/2009
| | | | |
Title:
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DESIGN STRUCTURE FOR PERFORMING ITERATIVE SYNTHESIS OF AN INTEGRATED CIRCUIT DESIGN TO ATTAIN POWER CLOSURE
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Patent #:
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Issue Dt:
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02/08/2011
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Application #:
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11872796
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Filing Dt:
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10/16/2007
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Publication #:
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Pub Dt:
|
04/16/2009
| | | | |
Title:
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CONDUCTOR STRUCTURE INCLUDING MANGANESE OXIDE CAPPING LAYER
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Patent #:
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Issue Dt:
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03/22/2011
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Application #:
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11872870
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Filing Dt:
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10/16/2007
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Publication #:
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Pub Dt:
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04/16/2009
| | | | |
Title:
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CURRENT DISTRIBUTION STRUCTURE AND METHOD
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Patent #:
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Issue Dt:
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12/28/2010
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Application #:
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11872924
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Filing Dt:
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10/16/2007
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Publication #:
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Pub Dt:
|
04/16/2009
| | | | |
Title:
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DESIGN STRUCTURE FOR PARTITIONED DUMMY FILL SHAPES FOR REDUCED MASK BIAS WITH ALTERNATING PHASE SHIFT MASKS
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Patent #:
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Issue Dt:
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05/31/2011
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Application #:
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11872970
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Filing Dt:
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10/16/2007
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Publication #:
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Pub Dt:
|
04/16/2009
| | | | |
Title:
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DEEP TRENCH CAPACITOR AND METHOD
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Patent #:
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Issue Dt:
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02/15/2011
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Application #:
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11873092
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Filing Dt:
|
10/16/2007
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Publication #:
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Pub Dt:
|
04/16/2009
| | | | |
Title:
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METHOD FOR CREATING WAFER BATCHES IN AN AUTOMATED BATCH PROCESS TOOL
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Patent #:
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Issue Dt:
|
07/12/2011
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Application #:
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11873316
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Filing Dt:
|
10/16/2007
|
Publication #:
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Pub Dt:
|
09/04/2008
| | | | |
Title:
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FIELD EFFECT TRANSISTOR DEVICE INCLUDING AN ARRAY OF CHANNEL ELEMENTS
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Patent #:
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Issue Dt:
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10/07/2014
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Application #:
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11873455
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Filing Dt:
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10/17/2007
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Publication #:
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Pub Dt:
|
04/23/2009
| | | | |
Title:
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AUTOMATED INTEGRATION OF FEEDBACK FROM FIELD FAILURE TO ORDER CONFIGURATOR FOR DYNAMIC OPTIMIZATION OF MANUFACTURING TEST PROCESSES
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Patent #:
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Issue Dt:
|
10/12/2010
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Application #:
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11873515
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Filing Dt:
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10/17/2007
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Publication #:
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Pub Dt:
|
04/23/2009
| | | | |
Title:
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DESIGN STRUCTURE FOR MULTIPLE SOURCE-SINGLE DRAIN FIELD EFFECT SEMICONDUCTOR DEVICE AND CIRCUIT
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Patent #:
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|
Issue Dt:
|
12/14/2010
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Application #:
|
11873521
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Filing Dt:
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10/17/2007
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Publication #:
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Pub Dt:
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04/23/2009
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Title:
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FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE
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Patent #:
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Issue Dt:
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10/27/2009
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Application #:
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11873534
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Filing Dt:
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10/17/2007
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Publication #:
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Pub Dt:
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01/29/2009
| | | | |
Title:
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IMPLEMENTING ENHANCED SRAM READ PERFORMANCE SORT RING OSCILLATOR (PSRO)
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Patent #:
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Issue Dt:
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03/08/2011
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Application #:
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11873711
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Filing Dt:
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10/17/2007
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Publication #:
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Pub Dt:
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04/23/2009
| | | | |
Title:
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DESIGN STRUCTURES INCLUDING MEANS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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02/22/2011
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Application #:
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11873919
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Filing Dt:
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10/17/2007
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Publication #:
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Pub Dt:
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04/23/2009
| | | | |
Title:
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SYSTEM FOR IMPROVING A LOGIC CIRCUIT AND ASSOCIATED METHODS
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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11874232
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Filing Dt:
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10/18/2007
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Publication #:
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Pub Dt:
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04/23/2009
| | | | |
Title:
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METHOD AND APPARATUS FOR PARALLEL AND SERIAL DATA TRANSFER
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Patent #:
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Issue Dt:
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11/23/2010
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Application #:
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11874281
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Filing Dt:
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10/18/2007
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Publication #:
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Pub Dt:
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02/14/2008
| | | | |
Title:
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SIMULTANEOUS COMPUTATION OF MULTIPLE POINTS ON ONE OR MULTIPLE CUT LINES
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Patent #:
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Issue Dt:
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02/15/2011
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Application #:
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11874402
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Filing Dt:
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10/18/2007
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Publication #:
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Pub Dt:
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10/02/2008
| | | | |
Title:
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PROCESSOR COMPRISING A FIRST AND A SECOND MODE OF OPERATION AND METHOD OF OPERATING THE SAME
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Patent #:
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Issue Dt:
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02/01/2011
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Application #:
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11874454
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Filing Dt:
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10/18/2007
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Publication #:
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Pub Dt:
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04/23/2009
| | | | |
Title:
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BODY TIE TEST STRUCTURE FOR ACCURATE BODY EFFECT MEASUREMENT
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Patent #:
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Issue Dt:
|
08/23/2011
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Application #:
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11874518
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Filing Dt:
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10/18/2007
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Publication #:
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Pub Dt:
|
04/23/2009
| | | | |
Title:
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METHOD OF OPTIMIZING QUEUE TIMES IN A PRODUCTION CYCLE
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Patent #:
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Issue Dt:
|
06/07/2011
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Application #:
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11874565
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Filing Dt:
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10/18/2007
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Publication #:
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Pub Dt:
|
04/23/2009
| | | | |
Title:
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SEMICONDUCTOR-ON-INSULATOR SUBSTRATE WITH A DIFFUSION BARRIER
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Patent #:
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Issue Dt:
|
03/05/2013
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Application #:
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11874582
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Filing Dt:
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10/18/2007
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Publication #:
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Pub Dt:
|
04/23/2009
| | | | |
Title:
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PROGRAMMABLE VIA DEVICES
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Patent #:
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Issue Dt:
|
01/25/2011
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Application #:
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11874620
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Filing Dt:
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10/18/2007
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Publication #:
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Pub Dt:
|
02/14/2008
| | | | |
Title:
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ACCURATELY MODELING AN ASYNCHRONOUS INTERFACE USING EXPANDED LOGIC ELEMENTS
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Patent #:
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Issue Dt:
|
11/22/2011
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Application #:
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11874861
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Filing Dt:
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10/18/2007
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Publication #:
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Pub Dt:
|
04/23/2009
| | | | |
Title:
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ON-CHIP TEMPERATURE GRADIENT MINIMIZATION USING CARBON NANOTUBE COOLING STRUCTURES WITH VARIABLE COOLING CAPACITY
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Patent #:
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Issue Dt:
|
10/21/2008
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Application #:
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11875004
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Filing Dt:
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10/19/2007
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Publication #:
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Pub Dt:
|
02/14/2008
| | | | |
Title:
|
MEMORY ARRAY HAVING A REDUNDANT MEMORY ELEMENT
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Patent #:
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Issue Dt:
|
05/25/2010
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Application #:
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11875011
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Filing Dt:
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10/19/2007
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Publication #:
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Pub Dt:
|
02/14/2008
| | | | |
Title:
|
ENABLING MEMORY REDUNDANCY DURING TESTING
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Patent #:
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Issue Dt:
|
07/19/2011
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Application #:
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11875013
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Filing Dt:
|
10/19/2007
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Publication #:
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Pub Dt:
|
02/07/2008
| | | | |
Title:
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DESIGN STRUCTURES INCORPORATING SEMICONDUCTOR DEVICE STRUCTURES WITH REDUCED JUNCTION CAPACITANCE AND DRAIN INDUCED BARRIER LOWERING
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Patent #:
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Issue Dt:
|
10/26/2010
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Application #:
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11875032
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Filing Dt:
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10/19/2007
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Publication #:
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Pub Dt:
|
04/23/2009
| | | | |
Title:
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TRANSITION BALANCING FOR NOISE REDUCTION/DI/DT REDUCTION DURING DESIGN, SYNTHESIS, AND PHYSICAL DESIGN
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Patent #:
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Issue Dt:
|
07/19/2011
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Application #:
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11875193
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Filing Dt:
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10/19/2007
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Publication #:
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Pub Dt:
|
05/22/2008
| | | | |
Title:
|
DESIGN STRUCTURES INCORPORATING INTERCONNECT STRUCTURES WITH IMPROVED ELECTROMIGRATION RESISTANCE
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Patent #:
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Issue Dt:
|
02/28/2012
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Application #:
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11876035
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Filing Dt:
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10/22/2007
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Publication #:
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Pub Dt:
|
02/28/2008
| | | | |
Title:
|
IMPROVING DESIGN MANUFACTURING, AND TRANSPORTATION IN MASS MANUFACTURING THROUGH ANALYSIS OF DEFECT DATA
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Patent #:
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Issue Dt:
|
02/17/2009
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Application #:
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11876605
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Filing Dt:
|
10/22/2007
|
Publication #:
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|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
HIGH SPEED DATA CHANNEL INCLUDING A CMOS VCSEL DRIVER AND A HIGH PERFORMANCE PHOTODETECTOR AND CMOS PHOTORECEIVER
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|
Patent #:
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|
Issue Dt:
|
03/29/2011
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Application #:
|
11877016
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Filing Dt:
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10/23/2007
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Publication #:
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Pub Dt:
|
04/23/2009
| | | | |
Title:
|
CONTROLLED DOPING OF SEMICONDUCTOR NANOWIRES
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|
Patent #:
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|
Issue Dt:
|
06/17/2008
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Application #:
|
11877859
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Filing Dt:
|
10/24/2007
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Title:
|
MECHANICALLY DECOUPLED OPTO-MECHANICAL CONNECTOR FOR FLEXIBLE OPTICAL WAVEGUIDES EMBEDDED AND/OR ATTACHED TO A PRINTED CIRCUIT BOARD
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|
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Patent #:
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|
Issue Dt:
|
08/19/2008
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Application #:
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11877898
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Filing Dt:
|
10/24/2007
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Title:
|
LIMITED SWITCH DYNAMIC LOGIC CELL BASED REGISTER
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Patent #:
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Issue Dt:
|
11/13/2012
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Application #:
|
11879937
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Filing Dt:
|
07/18/2007
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Publication #:
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Pub Dt:
|
01/22/2009
| | | | |
Title:
|
TEST STRUCTURE FOR DETERMINING GATE-TO-BODY TUNNELING CURRENT IN A FLOATING BODY FET
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|
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Patent #:
|
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Issue Dt:
|
09/07/2010
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Application #:
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11882163
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Filing Dt:
|
07/30/2007
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Publication #:
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Pub Dt:
|
02/05/2009
| | | | |
Title:
|
METHOD AND MATERIALS FOR PATTERNING A NEUTRAL SURFACE
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|
Patent #:
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Issue Dt:
|
11/16/2010
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Application #:
|
11891165
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Filing Dt:
|
08/09/2007
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Publication #:
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|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
TIME STAMPING TRANSACTIONS TO VALIDATE ATOMIC OPERATIONS IN MULTIPROCESSOR SYSTEMS
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|
|
Patent #:
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|
Issue Dt:
|
03/23/2010
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Application #:
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11923152
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Filing Dt:
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10/24/2007
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Publication #:
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Pub Dt:
|
07/31/2008
| | | | |
Title:
|
PHASE SHIFTING AND COMBINING ARCHITECTURE FOR PHASED ARRAYS
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|
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Patent #:
|
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Issue Dt:
|
12/21/2010
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Application #:
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11923413
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Filing Dt:
|
10/24/2007
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Publication #:
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Pub Dt:
|
02/14/2008
| | | | |
Title:
|
METHOD AND STRUCTURE FOR CONTROLLED IMPEDANCE WIRE BONDS USING CO-DISPENSING OF DIELECTRIC SPACERS
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|
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Patent #:
|
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Issue Dt:
|
08/09/2011
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Application #:
|
11923663
|
Filing Dt:
|
12/03/2007
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Publication #:
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|
Pub Dt:
|
06/04/2009
| | | | |
Title:
|
DESIGN VERIFICATION TECHNIQUE
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|
|
Patent #:
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|
Issue Dt:
|
05/29/2012
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Application #:
|
11923686
|
Filing Dt:
|
10/25/2007
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Publication #:
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Pub Dt:
|
03/27/2008
| | | | |
Title:
|
STRUCTURE AND LAYOUT OF A FET PRIME CELL
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|
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Patent #:
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Issue Dt:
|
02/23/2010
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Application #:
|
11923701
|
Filing Dt:
|
10/25/2007
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Publication #:
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Pub Dt:
|
04/30/2009
| | | | |
Title:
|
METHOD AND CIRCUIT FOR DETECTING AND COMPENSATING FOR A DEGRADATION OF A SEMICONDUCTOR DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
06/30/2015
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Application #:
|
11923864
|
Filing Dt:
|
10/25/2007
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Publication #:
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Pub Dt:
|
04/30/2009
| | | | |
Title:
|
TUNABLE CAPACITOR
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|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
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Application #:
|
11923900
|
Filing Dt:
|
10/25/2007
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Publication #:
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Pub Dt:
|
02/28/2008
| | | | |
Title:
|
RADIATION HARDENED PROGRAMMABLE PHASE FREQUENCY DIVIDER
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|
|
Patent #:
|
|
Issue Dt:
|
05/26/2009
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Application #:
|
11923956
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Filing Dt:
|
10/25/2007
|
Publication #:
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Pub Dt:
|
05/29/2008
| | | | |
Title:
|
OPTICALLY CONNECTABLE CIRCUIT BOARD WITH OPTICAL COMPONENT(S) MOUNTED THEREON
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|
Patent #:
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|
Issue Dt:
|
12/09/2008
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Application #:
|
11924024
|
Filing Dt:
|
10/25/2007
|
Publication #:
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Pub Dt:
|
02/21/2008
| | | | |
Title:
|
ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> SI UNDER BIAXIAL COMPRESSIVE STRAIN
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|
|
Patent #:
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|
Issue Dt:
|
03/22/2011
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Application #:
|
11924059
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Filing Dt:
|
10/25/2007
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Publication #:
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Pub Dt:
|
04/30/2009
| | | | |
Title:
|
SRAM CELL HAVING A RECTANGULAR COMBINED ACTIVE AREA FOR PLANAR PASS GATE AND PLANAR PULL-DOWN NFETS
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|
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Patent #:
|
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Issue Dt:
|
11/15/2011
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Application #:
|
11924146
|
Filing Dt:
|
10/25/2007
|
Publication #:
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|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
PROCESSING TASKS WITH FAILURE RECOVERY
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|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
11924207
|
Filing Dt:
|
10/25/2007
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Publication #:
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Pub Dt:
|
02/28/2008
| | | | |
Title:
|
METHOD FOR FABRICATING SIGE-ON-INSULATOR (SGOI) AND GE-ON-INSULATOR (GOI) SUBSTRATES
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|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
11924239
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
HIGH SPEED DATA CHANNEL INCLUDING A CMOS VCSEL DRIVER AND A HIGH PERFORMANCE PHOTODETECTOR AND CMOS PHOTORECEIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2009
|
Application #:
|
11924283
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
HIGH SPEED DATA CHANNEL INCLUDING A CMOS VCSEL DRIVER AND A HIGH PERFORMANCE PHOTODETECTOR AND CMOS PHOTORECEIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
11924650
|
Filing Dt:
|
10/26/2007
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Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH ASYMMETRIC GATE DIELECTRIC PROFILE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
11924662
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
SUBSTRATE ANCHOR STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
11924735
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
TECHNIQUES FOR IMPEDING REVERSE ENGINEERING
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|
|
Patent #:
|
|
Issue Dt:
|
09/29/2009
|
Application #:
|
11924825
|
Filing Dt:
|
10/26/2007
|
Publication #:
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|
Pub Dt:
|
03/06/2008
| | | | |
Title:
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METHOD FOR PRODUCING A DOPED NITRIDE FILM, DOPED OXIDE FILM AND OTHER DOPED FILMS
|
|