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Patent #:
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Issue Dt:
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12/17/2013
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Application #:
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13623893
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Filing Dt:
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09/21/2012
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Title:
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REPLACEMENT METAL GATE DIFFUSION BREAK FORMATION
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Patent #:
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Issue Dt:
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05/14/2013
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13624235
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Filing Dt:
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09/21/2012
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Publication #:
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Pub Dt:
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01/17/2013
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Title:
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WORK FUNCTION ADJUSTMENT IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY SELECTIVELY REMOVING A BARRIER LAYER
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Patent #:
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12/17/2013
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13624251
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Filing Dt:
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09/21/2012
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Publication #:
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Pub Dt:
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06/20/2013
| | | | |
Title:
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V-GROOVE SOURCE/DRAIN MOSFET AND PROCESS FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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03/31/2015
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Application #:
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13625294
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Filing Dt:
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09/24/2012
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Publication #:
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Pub Dt:
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01/24/2013
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Title:
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SILICIDE MICROMECHANICAL DEVICE AND METHODS TO FABRICATE SAME
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Patent #:
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Issue Dt:
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11/25/2014
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13625440
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Filing Dt:
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09/24/2012
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Publication #:
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Pub Dt:
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03/27/2014
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Title:
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LATERAL SILICON-ON-INSULATOR BIPOLAR JUNCTION TRANSISTOR RADIATION DOSIMETER
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Patent #:
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Issue Dt:
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07/29/2014
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13626025
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Filing Dt:
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09/25/2012
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Publication #:
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Pub Dt:
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03/27/2014
| | | | |
Title:
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THROUGH SILICON VIA WAFER, CONTACTS AND DESIGN STRUCTURES
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Patent #:
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01/06/2015
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13626032
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Filing Dt:
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09/25/2012
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Publication #:
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Pub Dt:
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03/27/2014
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Title:
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OVERCOMING CHIP WARPING TO ENHANCE WETTING OF SOLDER BUMPS AND FLIP CHIP ATTACHES IN A FLIP CHIP PACKAGE
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Patent #:
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07/23/2013
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13626242
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Filing Dt:
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09/25/2012
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Publication #:
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Pub Dt:
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07/11/2013
| | | | |
Title:
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INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME
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Patent #:
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06/03/2014
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13628468
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Filing Dt:
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09/27/2012
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Publication #:
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Pub Dt:
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01/31/2013
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Title:
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SEMICONDUCTOR DEVICE COMPRISING METAL GATES AND A SILICON CONTAINING RESISTOR FORMED ON AN ISOLATION STRUCTURE
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Patent #:
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03/25/2014
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13628726
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Filing Dt:
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09/27/2012
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Publication #:
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Pub Dt:
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03/27/2014
| | | | |
Title:
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STACKED NANOWIRE FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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09/30/2014
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Application #:
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13628914
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Filing Dt:
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09/27/2012
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Publication #:
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Pub Dt:
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03/27/2014
| | | | |
Title:
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METHODS OF FORMING 3-D SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND A NOVEL 3-D DEVICE
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Patent #:
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07/01/2014
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13629910
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Filing Dt:
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09/28/2012
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Publication #:
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Pub Dt:
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04/03/2014
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Title:
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STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND SI NANOPHOTONICS
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Patent #:
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Issue Dt:
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12/17/2013
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13633234
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Filing Dt:
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10/02/2012
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Title:
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DOUBLE-SIDED SEMICONDUCTOR STRUCTURE USING THROUGH-SILICON VIAS
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Patent #:
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Issue Dt:
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05/20/2014
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Application #:
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13644234
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Filing Dt:
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10/03/2012
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Publication #:
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Pub Dt:
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06/27/2013
| | | | |
Title:
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Techniques for Thermal Modeling of Data Centers to Improve Energy Efficiency
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Patent #:
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Issue Dt:
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05/06/2014
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Application #:
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13644683
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Filing Dt:
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10/04/2012
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Publication #:
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Pub Dt:
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04/10/2014
| | | | |
Title:
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SIMULTANEOUS PHOTORESIST DEVELOPMENT AND NEUTRAL POLYMER LAYER FORMATION
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Patent #:
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Issue Dt:
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11/18/2014
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Application #:
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13644742
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Filing Dt:
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10/04/2012
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Publication #:
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Pub Dt:
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04/10/2014
| | | | |
Title:
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SEMICONDUCTOR ALLOY FIN FIELD EFFECT TRANSISTOR
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Patent #:
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NONE
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Application #:
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13644788
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Filing Dt:
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10/04/2012
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Publication #:
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Pub Dt:
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04/10/2014
| | | | |
Title:
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METHOD AND APPARATUS FOR MATCHING TOOLS BASED ON TIME TRACE DATA
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Patent #:
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Issue Dt:
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08/19/2014
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Application #:
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13644918
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Filing Dt:
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10/04/2012
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Publication #:
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Pub Dt:
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04/10/2014
| | | | |
Title:
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BACK-END-OF-LINE METAL-OXIDE-SEMICONDUCTOR VARACTORS
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Patent #:
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Issue Dt:
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03/18/2014
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Application #:
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13646760
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Filing Dt:
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10/08/2012
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Publication #:
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Pub Dt:
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04/10/2014
| | | | |
Title:
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DOUBLE PATTERNING COMPATIBLE COLORLESS M1 ROUTE
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Patent #:
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Issue Dt:
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07/14/2015
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Application #:
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13647538
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Filing Dt:
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10/09/2012
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Publication #:
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Pub Dt:
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02/07/2013
| | | | |
Title:
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METHODS FOR NORMALIZING STRAIN IN SEMICONDCUTOR DEVICES AND STRAIN NORMALIZED SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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12/16/2014
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Application #:
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13647547
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Filing Dt:
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10/09/2012
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Publication #:
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Pub Dt:
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03/27/2014
| | | | |
Title:
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METHOD FOR RADIATION MONITORING
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Patent #:
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Issue Dt:
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12/09/2014
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Application #:
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13648321
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Filing Dt:
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10/10/2012
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Publication #:
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Pub Dt:
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04/10/2014
| | | | |
Title:
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SINGLE FIN CUT EMPLOYING ANGLED PROCESSING METHODS
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Patent #:
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Issue Dt:
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12/09/2014
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Application #:
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13648433
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Filing Dt:
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10/10/2012
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Publication #:
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Pub Dt:
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04/10/2014
| | | | |
Title:
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SEMICONDUCTOR DEVICE HAVING A SELF-FORMING BARRIER LAYER AT VIA BOTTOM
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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13648555
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Filing Dt:
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10/10/2012
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Publication #:
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Pub Dt:
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02/07/2013
| | | | |
Title:
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COLLECTING FAILURE INFORMATION ON ERROR CORRECTION CODE (ECC) PROTECTED DATA
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Patent #:
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Issue Dt:
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10/28/2014
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Application #:
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13649284
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Filing Dt:
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10/11/2012
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Publication #:
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Pub Dt:
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06/20/2013
| | | | |
Title:
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FINFET WITH VERTICAL SILICIDE STRUCTURE
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Patent #:
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Issue Dt:
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02/21/2017
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13649699
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Filing Dt:
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10/11/2012
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Publication #:
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Pub Dt:
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04/17/2014
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Title:
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METHODOLOGY OF GRADING RELIABILITY AND PERFORMANCE OF CHIPS ACROSS WAFER
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Patent #:
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Issue Dt:
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09/30/2014
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Application #:
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13649760
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Filing Dt:
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10/11/2012
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Publication #:
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Pub Dt:
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02/07/2013
| | | | |
Title:
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THERMAL EXPANSION CONTROL EMPLOYING PLATELET FILLERS
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Patent #:
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Issue Dt:
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10/21/2014
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Application #:
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13649769
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Filing Dt:
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10/11/2012
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Publication #:
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Pub Dt:
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04/17/2014
| | | | |
Title:
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MULTI-FINGER TRANSISTOR LAYOUT FOR REDUCING CROSS-FINGER ELECTRIC VARIATIONS AND FOR FULLY UTILIZING AVAILABLE BREAKDOWN VOLTAGES
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Patent #:
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Issue Dt:
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06/23/2015
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13650233
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Filing Dt:
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10/12/2012
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Pub Dt:
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04/17/2014
| | | | |
Title:
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ADVANCED FARADAY SHIELD FOR A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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11/18/2014
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Application #:
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13651874
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Filing Dt:
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10/15/2012
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Publication #:
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Pub Dt:
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04/17/2014
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Title:
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EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT
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Patent #:
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Issue Dt:
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10/01/2013
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Application #:
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13651918
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Filing Dt:
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10/15/2012
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Publication #:
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Pub Dt:
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02/14/2013
| | | | |
Title:
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SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX)
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Patent #:
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Issue Dt:
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05/14/2013
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Application #:
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13652804
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Filing Dt:
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10/16/2012
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Publication #:
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Pub Dt:
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02/28/2013
| | | | |
Title:
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NANOPILLAR E-FUSE STRUCTURE AND PROCESS
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Patent #:
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Issue Dt:
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12/09/2014
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Application #:
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13653291
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Filing Dt:
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10/16/2012
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Publication #:
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Pub Dt:
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04/17/2014
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Title:
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BLOCK-INTERLEAVED AND ERROR CORRECTION CODE (ECC)-ENCODED SUB DATA SET (SDS) FORMAT
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Patent #:
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Issue Dt:
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11/04/2014
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Application #:
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13653606
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Filing Dt:
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10/17/2012
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Publication #:
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Pub Dt:
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04/17/2014
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Title:
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DIRECTED SELF-ASSEMBLY OF BLOCK COPOLYMERS USING LASER ANNEALING
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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13653665
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Filing Dt:
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10/17/2012
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Publication #:
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Pub Dt:
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05/09/2013
| | | | |
Title:
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METAL ALLOY CAP INTEGRATION
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Patent #:
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Issue Dt:
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08/26/2014
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Application #:
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13653996
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Filing Dt:
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10/17/2012
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Publication #:
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Pub Dt:
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04/17/2014
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Title:
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REACTIVE MATERIAL FOR INTEGRATED CIRCUIT TAMPER DETECTION AND RESPONSE
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Patent #:
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Issue Dt:
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07/08/2014
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Application #:
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13654987
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Filing Dt:
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10/18/2012
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Publication #:
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Pub Dt:
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04/24/2014
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Title:
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STRUCTURE AND METHOD FOR FORMING A LOW GATE RESISTANCE HIGH-K METAL GATE TRANSISTOR DEVICE
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Patent #:
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Issue Dt:
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09/03/2013
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Application #:
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13655426
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Filing Dt:
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10/18/2012
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Title:
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FORMING AN ARRAY OF METAL BALLS OR SHAPES ON A SUBSTRATE
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Patent #:
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Issue Dt:
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05/26/2015
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Application #:
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13655520
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Filing Dt:
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10/19/2012
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Publication #:
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Pub Dt:
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04/11/2013
| | | | |
Title:
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USER-COORDINATED RESOURCE RECOVERY
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Patent #:
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Issue Dt:
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05/06/2014
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Application #:
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13655844
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Filing Dt:
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10/19/2012
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Publication #:
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Pub Dt:
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04/24/2014
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Title:
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METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A WET ETCH PROCESS FOR REMOVING SILICON NITRIDE
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Patent #:
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Issue Dt:
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09/02/2014
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Application #:
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13655980
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Filing Dt:
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10/19/2012
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Publication #:
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Pub Dt:
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02/21/2013
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Title:
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VISUALIZATION INTERFACE OF CONTINUOUS WAVEFORM MULTI-SPEAKER IDENTIFICATION
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Patent #:
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Issue Dt:
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06/23/2015
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Application #:
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13656794
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Filing Dt:
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10/22/2012
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Publication #:
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Pub Dt:
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04/24/2014
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Title:
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METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH LOW-K SPACERS AND THE RESULTING DEVICE
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Patent #:
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Issue Dt:
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11/25/2014
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Application #:
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13656819
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Filing Dt:
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10/22/2012
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Publication #:
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Pub Dt:
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04/24/2014
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Title:
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FIELD EFFECT TRANSISTOR HAVING PHASE TRANSITION MATERIAL INCORPORATED INTO ONE OR MORE COMPONENTS FOR REDUCED LEAKAGE CURRENT
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Patent #:
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Issue Dt:
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09/30/2014
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Application #:
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13656829
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Filing Dt:
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10/22/2012
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Publication #:
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Pub Dt:
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04/24/2014
| | | | |
Title:
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MEMORY SYSTEM INCORPORATING A CIRCUIT TO GENERATE A DELAY SIGNAL AND AN ASSOCIATED METHOD OF OPERATING A MEMORY SYSTEM
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Patent #:
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Issue Dt:
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01/07/2014
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Application #:
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13657182
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Filing Dt:
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10/22/2012
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Title:
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SUBTRACTIVE METAL MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13658928
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Filing Dt:
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10/24/2012
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Publication #:
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Pub Dt:
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04/24/2014
| | | | |
Title:
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METHODS OF AVOIDING SHADOWING WHEN FORMING SOURCE/DRAIN IMPLANT REGIONS ON 3D SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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11/03/2015
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Application #:
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13659318
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Filing Dt:
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10/24/2012
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Publication #:
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Pub Dt:
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04/24/2014
| | | | |
Title:
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SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH
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Patent #:
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Issue Dt:
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03/04/2014
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Application #:
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13659453
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Filing Dt:
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10/24/2012
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Title:
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METHODS FOR DIRECTED SELF-ASSEMBLY PROCESS/PROXIMITY CORRECTION
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Patent #:
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Issue Dt:
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06/03/2014
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Application #:
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13660604
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Filing Dt:
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10/25/2012
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Publication #:
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Pub Dt:
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03/27/2014
| | | | |
Title:
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TRANSPARENT CONDUCTIVE ELECTRODE STACK CONTAINING CARBON-CONTAINING MATERIAL
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Patent #:
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Issue Dt:
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10/07/2014
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Application #:
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13661188
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Filing Dt:
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10/26/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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PERFORMANCE ENHANCEMENT IN TRANSISTORS BY PROVIDING A GRADED EMBEDDED STRAIN-INDUCING SEMICONDUCTOR REGION WITH ADAPTED ANGLES WITH RESPECT TO THE SUBSTRATE SURFACE
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Patent #:
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Issue Dt:
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12/30/2014
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Application #:
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13661359
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Filing Dt:
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10/26/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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ISOLATION SCHEME FOR BIPOLAR TRANSISTORS IN BICMOS TECHNOLOGY
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Patent #:
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Issue Dt:
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03/18/2014
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Application #:
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13663589
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Filing Dt:
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10/30/2012
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Publication #:
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Pub Dt:
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05/09/2013
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH REDUCED THRESHOLD VARIABILITY HAVING A THRESHOLD ADJUSTING SEMICONDUCTOR ALLOY IN THE DEVICE ACTIVE REGION
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Patent #:
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Issue Dt:
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06/10/2014
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Application #:
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13663816
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Filing Dt:
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10/30/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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AUTOMATIC WAFER DATA SAMPLE PLANNING AND REVIEW
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Patent #:
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Issue Dt:
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02/16/2016
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Application #:
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13663854
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Filing Dt:
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10/30/2012
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Publication #:
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Pub Dt:
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05/01/2014
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Title:
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METHODS OF FORMING ENHANCED MOBILITY CHANNEL REGIONS ON 3D SEMICONDUCTOR DEVICES, AND DEVICES COMPRISING SAME
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Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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13664062
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Filing Dt:
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10/30/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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FIN ETCH AND FIN REPLACEMENT FOR FINFET INTEGRATION
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Patent #:
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Issue Dt:
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09/16/2014
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Application #:
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13664744
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING REPLACEMENT METAL GATE PROCESS INCORPORATING A CONDUCTIVE DUMMY GATE LAYER
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Patent #:
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Issue Dt:
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01/06/2015
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Application #:
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13664869
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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SELF-ALIGNED CONTACT STRUCTURE FOR REPLACEMENT METAL GATE
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Patent #:
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Issue Dt:
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07/14/2015
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Application #:
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13664873
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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BULK FINFET WITH PUNCHTHROUGH STOPPER REGION AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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09/30/2014
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Application #:
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13665276
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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HIERARCHICAL DESIGN OF INTEGRATED CIRCUITS WITH MULTI-PATTERNING REQUIREMENTS
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Patent #:
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Issue Dt:
|
07/01/2014
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Application #:
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13665315
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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PARASITIC EXTRACTION IN AN INTEGRATED CIRCUIT WITH MULTI-PATTERNING REQUIREMENTS
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Patent #:
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Issue Dt:
|
12/24/2013
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Application #:
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13665334
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Filing Dt:
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10/31/2012
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Title:
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Techniques for Fabricating Janus MEMS Transistors
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Patent #:
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Issue Dt:
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05/13/2014
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Application #:
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13666031
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Filing Dt:
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11/01/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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DUAL GATE FINFET DEVICES
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Patent #:
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Issue Dt:
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03/24/2015
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Application #:
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13666214
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Filing Dt:
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11/01/2012
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Publication #:
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Pub Dt:
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03/07/2013
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Title:
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TRANSISTORS HAVING STRESSED CHANNEL REGIONS AND METHODS OF FORMING TRANSISTORS HAVING STRESSED CHANNEL REGIONS
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Patent #:
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Issue Dt:
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08/11/2015
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Application #:
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13667384
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Filing Dt:
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11/02/2012
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Publication #:
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Pub Dt:
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05/08/2014
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Title:
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FABRICATION OF LOCALIZED SOI ON LOCALIZED THICK BOX USING SELECTIVE EPITAXY ON BULK SEMICONDUCTOR SUBSTRATES FOR PHOTONICS DEVICE INTEGRATION
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Patent #:
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Issue Dt:
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03/18/2014
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Application #:
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13667657
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Filing Dt:
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11/02/2012
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Publication #:
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Pub Dt:
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03/07/2013
| | | | |
Title:
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COMPLEMENTARY STRESS LINER TO IMPROVE DGO/AVT DEVICES AND POLY AND DIFFUSION RESISTORS
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Patent #:
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Issue Dt:
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01/07/2014
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Application #:
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13668401
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Filing Dt:
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11/05/2012
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Publication #:
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Pub Dt:
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12/12/2013
| | | | |
Title:
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SIDE-GATE DEFINED TUNABLE NANOCONSTRICTION IN DOUBLE-GATED GRAPHENE MULTILAYERS
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Patent #:
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Issue Dt:
|
07/01/2014
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Application #:
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13668869
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Filing Dt:
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11/05/2012
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Publication #:
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Pub Dt:
|
05/08/2014
| | | | |
Title:
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MAGNETORESISTIVE RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
|
02/11/2014
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Application #:
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13669651
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Filing Dt:
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11/06/2012
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Title:
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PROCESS FOR CLEANING SEMICONDUCTOR DEVICES AND/OR TOOLING DURING MANUFACTURING THEREOF
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Patent #:
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Issue Dt:
|
08/26/2014
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Application #:
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13670566
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Filing Dt:
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11/07/2012
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Publication #:
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Pub Dt:
|
05/08/2014
| | | | |
Title:
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FABRICATION OF REVERSE SHALLOW TRENCH ISOLATION STRUCTURES WITH SUPER-STEEP RETROGRADE WELLS
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Patent #:
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Issue Dt:
|
03/18/2014
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Application #:
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13670605
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Filing Dt:
|
11/07/2012
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Title:
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METHODS OF FORMING FINS AND ISOLATION REGIONS ON A FINFET SEMICONDUCTOR DEVICE
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|
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Patent #:
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Issue Dt:
|
08/19/2014
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Application #:
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13670674
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Filing Dt:
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11/07/2012
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Publication #:
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Pub Dt:
|
05/08/2014
| | | | |
Title:
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PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
07/08/2014
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Application #:
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13670694
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Filing Dt:
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11/07/2012
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Publication #:
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Pub Dt:
|
05/08/2014
| | | | |
Title:
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ENHANCED CAPTURE PADS FOR THROUGH SEMICONDUCTOR VIAS
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Patent #:
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Issue Dt:
|
08/12/2014
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Application #:
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13670711
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Filing Dt:
|
11/07/2012
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Publication #:
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Pub Dt:
|
05/08/2014
| | | | |
Title:
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COPPER INTERCONNECT STRUCTURES AND METHODS OF MAKING SAME
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Patent #:
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Issue Dt:
|
09/16/2014
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Application #:
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13670748
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Filing Dt:
|
11/07/2012
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Publication #:
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Pub Dt:
|
05/08/2014
| | | | |
Title:
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ROBUST REPLACEMENT GATE INTEGRATION
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|
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Patent #:
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Issue Dt:
|
07/01/2014
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Application #:
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13670768
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Filing Dt:
|
11/07/2012
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Publication #:
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Pub Dt:
|
05/08/2014
| | | | |
Title:
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METHOD AND STRUCTURE FOR FORMING A LOCALIZED SOI FINFET
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|
|
Patent #:
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|
Issue Dt:
|
08/06/2013
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Application #:
|
13670880
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Filing Dt:
|
11/07/2012
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Title:
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FINFET ALIGNMENT STRUCTURES USING A DOUBLE TRENCH FLOW
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|
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Patent #:
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|
Issue Dt:
|
03/25/2014
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Application #:
|
13670921
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Filing Dt:
|
11/07/2012
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Title:
|
SELF-FORMATION OF HIGH-DENSITY DEFECT-FREE AND ALIGNED NANOSTRUCTURES
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Patent #:
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Issue Dt:
|
08/27/2013
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Application #:
|
13671098
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Filing Dt:
|
11/07/2012
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Title:
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WAFER-TO-WAFER PROCESS FOR MANUFACTURING A STACKED STRUCTURE
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Patent #:
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Issue Dt:
|
07/08/2014
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Application #:
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13671940
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Filing Dt:
|
11/08/2012
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Publication #:
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Pub Dt:
|
05/08/2014
| | | | |
Title:
|
METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICE
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|
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Patent #:
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|
Issue Dt:
|
08/20/2013
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Application #:
|
13672040
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Filing Dt:
|
11/08/2012
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Publication #:
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Pub Dt:
|
03/14/2013
| | | | |
Title:
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HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE RESISTANCE
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|
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Patent #:
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Issue Dt:
|
11/15/2016
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Application #:
|
13672751
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Filing Dt:
|
11/09/2012
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Publication #:
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Pub Dt:
|
05/16/2013
| | | | |
Title:
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MEMORY MODULE AND MEMORY CONTROLLER FOR CONTROLLING A MEMORY MODULE
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Patent #:
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Issue Dt:
|
09/01/2015
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Application #:
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13673549
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Filing Dt:
|
11/09/2012
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Publication #:
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Pub Dt:
|
05/15/2014
| | | | |
Title:
|
INTEGRATED CIRCUITS AND METHODS OF FORMING INTEGRATED CIRCUITS WITH INTERLAYER DIELECTRIC PROTECTION
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Patent #:
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Issue Dt:
|
02/03/2015
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Application #:
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13674142
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Filing Dt:
|
11/12/2012
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Publication #:
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Pub Dt:
|
05/15/2014
| | | | |
Title:
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METHODS OF MANUFACTURING INTEGRATED CIRCUITS HAVING FINFET STRUCTURES WITH EPITAXIALLY FORMED SOURCE/DRAIN REGIONS
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Patent #:
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Issue Dt:
|
05/26/2015
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Application #:
|
13676483
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Filing Dt:
|
11/14/2012
|
Publication #:
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Pub Dt:
|
05/15/2014
| | | | |
Title:
|
REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE
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Patent #:
|
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Issue Dt:
|
09/09/2014
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Application #:
|
13676817
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Filing Dt:
|
11/14/2012
|
Publication #:
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Pub Dt:
|
05/15/2014
| | | | |
Title:
|
COMPENSATION FOR A CHARGE IN A SILICON SUBSTRATE
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Patent #:
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Issue Dt:
|
02/11/2014
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Application #:
|
13677373
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Filing Dt:
|
11/15/2012
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Title:
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ELASTIC MODULUS MAPPING OF AN INTEGRATED CIRCUIT CHIP IN A CHIP/DEVICE PACKAGE
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Patent #:
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Issue Dt:
|
09/23/2014
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Application #:
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13677647
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Filing Dt:
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11/15/2012
|
Publication #:
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Pub Dt:
|
05/15/2014
| | | | |
Title:
|
CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
01/07/2014
|
Application #:
|
13677863
|
Filing Dt:
|
11/15/2012
|
Title:
|
SELF-FORMATION OF HIGH-DENSITY DEFECT-FREE AND ALIGNED NANOSTRUCTURES
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Patent #:
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Issue Dt:
|
02/24/2015
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Application #:
|
13678054
|
Filing Dt:
|
11/15/2012
|
Publication #:
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Pub Dt:
|
05/15/2014
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE INCLUDING A SEMICONDUCTOR-ON-INSULATOR REGION AND A BULK REGION, AND METHOD FOR THE FORMATION THEREOF
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Patent #:
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Issue Dt:
|
12/02/2014
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Application #:
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13678111
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Filing Dt:
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11/15/2012
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Publication #:
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Pub Dt:
|
04/17/2014
| | | | |
Title:
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EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT
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|
Patent #:
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Issue Dt:
|
09/16/2014
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Application #:
|
13678124
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Filing Dt:
|
11/15/2012
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Publication #:
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Pub Dt:
|
05/15/2014
| | | | |
Title:
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SOURCE AND DRAIN DOPING USING DOPED RAISED SOURCE AND DRAIN REGIONS
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Patent #:
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Issue Dt:
|
02/18/2014
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Application #:
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13679222
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Filing Dt:
|
11/16/2012
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Title:
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STRAINED SIGE NANOWIRE HAVING (111)-ORIENTED SIDEWALLS
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|
Patent #:
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Issue Dt:
|
02/04/2014
|
Application #:
|
13679357
|
Filing Dt:
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11/16/2012
|
Publication #:
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Pub Dt:
|
03/21/2013
| | | | |
Title:
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SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE
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Patent #:
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Issue Dt:
|
09/02/2014
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Application #:
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13681761
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Filing Dt:
|
11/20/2012
|
Publication #:
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Pub Dt:
|
05/22/2014
| | | | |
Title:
|
DENSE FINFET SRAM
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|
|
Patent #:
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Issue Dt:
|
08/26/2014
|
Application #:
|
13682056
|
Filing Dt:
|
11/20/2012
|
Publication #:
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Pub Dt:
|
05/22/2014
| | | | |
Title:
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POLYGON RECOVERY FOR VLSI MASK CORRECTION
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|
Patent #:
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Issue Dt:
|
05/06/2014
|
Application #:
|
13682769
|
Filing Dt:
|
11/21/2012
|
Publication #:
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Pub Dt:
|
05/22/2014
| | | | |
Title:
|
FINFET FORMATION USING DOUBLE PATTERNING MEMORIZATION
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|
|
Patent #:
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|
Issue Dt:
|
04/26/2016
|
Application #:
|
13683508
|
Filing Dt:
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11/21/2012
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Publication #:
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Pub Dt:
|
05/22/2014
| | | | |
Title:
|
POWER-SCALABLE SKEW COMPENSATION IN SOURCE-SYNCHRONOUS PARALLEL INTERFACES
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|
Patent #:
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Issue Dt:
|
02/03/2015
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Application #:
|
13684842
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Filing Dt:
|
11/26/2012
|
Publication #:
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Pub Dt:
|
05/29/2014
| | | | |
Title:
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DUMMY FIN FORMATION BY GAS CLUSTER ION BEAM
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|
Patent #:
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|
Issue Dt:
|
06/10/2014
|
Application #:
|
13684869
|
Filing Dt:
|
11/26/2012
|
Publication #:
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Pub Dt:
|
05/29/2014
| | | | |
Title:
|
REPLACEMENT METAL GATE TRANSISTORS USING BI-LAYER HARDMASK
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|
|
Patent #:
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Issue Dt:
|
06/16/2015
|
Application #:
|
13685733
|
Filing Dt:
|
11/27/2012
|
Publication #:
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|
Pub Dt:
|
05/29/2014
| | | | |
Title:
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Finfet Semiconductor Device Having Increased Gate Height Control
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|