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Patent #:
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|
Issue Dt:
|
04/15/2014
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Application #:
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13685735
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Filing Dt:
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11/27/2012
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Title:
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LOCALLY ISOLATED PROTECTED BULK FINFET SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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07/08/2014
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Application #:
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13686203
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Filing Dt:
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11/27/2012
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Publication #:
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Pub Dt:
|
05/29/2014
| | | | |
Title:
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TRENCH SILICIDE MASK GENERATION USING DESIGNATED TRENCH TRANSFER AND TRENCH BLOCK REGIONS
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Patent #:
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Issue Dt:
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10/14/2014
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Application #:
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13686263
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Filing Dt:
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11/27/2012
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Publication #:
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Pub Dt:
|
04/04/2013
| | | | |
Title:
|
METHOD OF MANUFACTURING COMPLIMENTARY METAL-INSULATOR-METAL (MIM) CAPACITORS
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Patent #:
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Issue Dt:
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12/23/2014
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Application #:
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13686377
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Filing Dt:
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11/27/2012
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Publication #:
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Pub Dt:
|
05/29/2014
| | | | |
Title:
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PACKAGE STRUCTURES TO IMPROVE ON-CHIP ANTENNA PERFORMANCE
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Patent #:
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Issue Dt:
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01/07/2014
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Application #:
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13687240
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
|
05/16/2013
| | | | |
Title:
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METHOD FOR FORMING AND STRUCTURE OF A RECESSED SOURCE/DRAIN STRAP FOR A MUGFET
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Patent #:
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Issue Dt:
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03/10/2015
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Application #:
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13687314
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
|
05/15/2014
| | | | |
Title:
|
CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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08/12/2014
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Application #:
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13687355
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
|
05/29/2014
| | | | |
Title:
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METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR NFET SEMICONDUCTOR DEVICES AND DEVICES HAVING SUCH GATE STRUCTURES
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Patent #:
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Issue Dt:
|
09/09/2014
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Application #:
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13687877
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
|
04/04/2013
| | | | |
Title:
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RESTRICTED STRESS REGIONS FORMED IN THE CONTACT LEVEL OF A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
11/18/2014
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Application #:
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13688259
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Filing Dt:
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11/29/2012
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Publication #:
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Pub Dt:
|
05/29/2014
| | | | |
Title:
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SEMICONDUCTOR DEVICE HAVING A METAL GATE RECESS
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Patent #:
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Issue Dt:
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06/03/2014
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Application #:
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13689052
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Filing Dt:
|
11/29/2012
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Publication #:
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Pub Dt:
|
05/08/2014
| | | | |
Title:
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MAGNETORESISTIVE RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
|
08/26/2014
|
Application #:
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13689838
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Filing Dt:
|
11/30/2012
|
Publication #:
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Pub Dt:
|
06/05/2014
| | | | |
Title:
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HETEROJUNCTION BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
|
04/08/2014
|
Application #:
|
13689839
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Filing Dt:
|
11/30/2012
|
Title:
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METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING LOW RESISTANCE DEVICE CONTACTS
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|
Patent #:
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Issue Dt:
|
07/15/2014
|
Application #:
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13689844
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Filing Dt:
|
11/30/2012
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Publication #:
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|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING LOW RESISTANCE METAL GATE STRUCTURES
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Patent #:
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Issue Dt:
|
01/06/2015
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Application #:
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13689924
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Filing Dt:
|
11/30/2012
|
Publication #:
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|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
UNIFORM FINFET GATE HEIGHT
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|
|
Patent #:
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|
Issue Dt:
|
09/09/2014
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Application #:
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13689948
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Filing Dt:
|
11/30/2012
|
Publication #:
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|
Pub Dt:
|
06/05/2014
| | | | |
Title:
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UNIFORM FINFET GATE HEIGHT
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|
Patent #:
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|
Issue Dt:
|
02/17/2015
|
Application #:
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13689979
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Filing Dt:
|
11/30/2012
|
Publication #:
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|
Pub Dt:
|
06/05/2014
| | | | |
Title:
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NOVEL CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME
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Patent #:
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Issue Dt:
|
02/03/2015
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Application #:
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13690240
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Filing Dt:
|
11/30/2012
|
Publication #:
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|
Pub Dt:
|
06/05/2014
| | | | |
Title:
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Semiconductor Device Having SSOI Substrate with Relaxed Tensile Stress
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|
Patent #:
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|
Issue Dt:
|
08/18/2015
|
Application #:
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13691129
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Filing Dt:
|
11/30/2012
|
Publication #:
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|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
MULTI COMPONENT DIELECTRIC LAYER
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|
Patent #:
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|
Issue Dt:
|
07/08/2014
|
Application #:
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13692603
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Filing Dt:
|
12/03/2012
|
Publication #:
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|
Pub Dt:
|
05/22/2014
| | | | |
Title:
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DIELECTRIC EQUIVALENT THICKNESS AND CAPACITANCE SCALING FOR SEMICONDUCTOR DEVICES
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|
Patent #:
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|
Issue Dt:
|
04/15/2014
|
Application #:
|
13693094
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Filing Dt:
|
12/04/2012
|
Title:
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SEMICONDUCTOR DEVICE HAVING A GATE FORMED ON A UNIFORM SURFACE AND METHOD FOR FORMING THE SAME
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|
|
Patent #:
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|
Issue Dt:
|
05/27/2014
|
Application #:
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13693285
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Filing Dt:
|
12/04/2012
|
Publication #:
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|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH
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|
Patent #:
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|
Issue Dt:
|
02/17/2015
|
Application #:
|
13693627
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Filing Dt:
|
12/04/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
ASYMMETRIC TEMPLATES FOR FORMING NON-PERIODIC PATTERNS USING DIRECTES SELF-ASSEMBLY MATERIALS
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|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
13693749
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Filing Dt:
|
12/04/2012
|
Publication #:
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|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
FAR BACK END OF THE LINE STACK ENCAPSULATION
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|
|
Patent #:
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|
Issue Dt:
|
07/08/2014
|
Application #:
|
13705261
|
Filing Dt:
|
12/05/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
COMBINATION FINFET AND PLANAR FET SEMICONDUCTOR DEVICE AND METHODS OF MAKING SUCH A DEVICE
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|
Patent #:
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|
Issue Dt:
|
03/18/2014
|
Application #:
|
13705477
|
Filing Dt:
|
12/05/2012
|
Title:
|
Finfet eDram Strap Connection Structure
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|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
13705717
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Filing Dt:
|
12/05/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
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|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13705920
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Filing Dt:
|
12/05/2012
|
Title:
|
GATE-ALL-AROUND CARBON NANOTUBE TRANSISTOR WITH SELECTIVELY DOPED SPACERS
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|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13707058
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Filing Dt:
|
12/06/2012
|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
Title:
|
SILICIDE CONTACTS HAVING DIFFERENT SHAPES ON REGIONS OF A SEMICONDUCTOR DEVICE
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|
Patent #:
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|
Issue Dt:
|
08/26/2014
|
Application #:
|
13708126
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Filing Dt:
|
12/07/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
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Preventing FIN Erosion and Limiting Epi Overburden in FinFET Structures by Composite Hardmask
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|
Patent #:
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|
Issue Dt:
|
11/12/2013
|
Application #:
|
13708499
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Filing Dt:
|
12/07/2012
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
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SILICON BASED MICROCHANNEL COOLING AND ELECTRICAL PACKAGE
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|
Patent #:
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|
Issue Dt:
|
08/26/2014
|
Application #:
|
13708531
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Filing Dt:
|
12/07/2012
|
Publication #:
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|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
BULK FINFET WITH SUPER STEEP RETROGRADE WELL
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|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13709397
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Filing Dt:
|
12/10/2012
|
Publication #:
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|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
METHOD OF FORMING SELF-ASSEMBLED PATTERNS USING BLOCK COPOLYMERS, AND ARTICLES THEREOF
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Patent #:
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|
Issue Dt:
|
11/18/2014
|
Application #:
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13709541
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Filing Dt:
|
12/10/2012
|
Publication #:
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Pub Dt:
|
06/12/2014
| | | | |
Title:
|
DOUBLE SIDEWALL IMAGE TRANSFER PROCESS
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|
Patent #:
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|
Issue Dt:
|
05/20/2014
|
Application #:
|
13709662
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Filing Dt:
|
12/10/2012
|
Publication #:
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|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
BORDERLESS CONTACTS FOR SEMICONDUCTOR TRANSISTORS
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|
Patent #:
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|
Issue Dt:
|
05/27/2014
|
Application #:
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13709748
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Filing Dt:
|
12/10/2012
|
Publication #:
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|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
VECTORIZATION OF BIT-LEVEL NETLISTS
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|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13710498
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Filing Dt:
|
12/11/2012
|
Publication #:
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|
Pub Dt:
|
06/12/2014
| | | | |
Title:
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SEMICONDUCTOR DEVICE RESOLUTION ENHANCEMENT BY ETCHING MULTIPLE SIDES OF A MASK
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|
Patent #:
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|
Issue Dt:
|
11/11/2014
|
Application #:
|
13710551
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Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
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MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING
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|
Patent #:
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|
Issue Dt:
|
11/25/2014
|
Application #:
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13710561
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Filing Dt:
|
12/11/2012
|
Publication #:
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|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
DRAM ERROR DETECTION, EVALUATION, AND CORRECTION
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|
Patent #:
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|
Issue Dt:
|
09/02/2014
|
Application #:
|
13710575
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Filing Dt:
|
12/11/2012
|
Publication #:
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|
Pub Dt:
|
06/12/2014
| | | | |
Title:
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CONTACT LANDING PADS FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME
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|
Patent #:
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|
Issue Dt:
|
08/26/2014
|
Application #:
|
13711813
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Filing Dt:
|
12/12/2012
|
Publication #:
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|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
METHODS OF FORMING BULK FINFET SEMICONDUCTOR DEVICES BY PERFORMING A LINER RECESSING PROCESS TO DEFINE FIN HEIGHTS AND FINFET DEVICES WITH SUCH A RECESSED LINER
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|
Patent #:
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|
Issue Dt:
|
08/19/2014
|
Application #:
|
13712234
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Filing Dt:
|
12/12/2012
|
Publication #:
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|
Pub Dt:
|
06/12/2014
| | | | |
Title:
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HIGH DENSITY SERIAL CAPACITOR DEVICE AND METHODS OF MAKING SUCH A CAPACITOR DEVICE
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|
Patent #:
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|
Issue Dt:
|
03/17/2015
|
Application #:
|
13712567
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Filing Dt:
|
12/12/2012
|
Publication #:
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|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
EFFICIENT USE OF MIRRORED STORAGE CLOUDS
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|
Patent #:
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|
Issue Dt:
|
05/26/2015
|
Application #:
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13713759
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Filing Dt:
|
12/13/2012
|
Publication #:
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|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
QUANTUM CIRCUIT WITHIN WAVEGUIDE-BEYOND-CUTOFF
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13713842
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Filing Dt:
|
12/13/2012
|
Publication #:
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|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
FINFET WITH MERGE-FREE FINS
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|
|
Patent #:
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|
Issue Dt:
|
09/22/2015
|
Application #:
|
13714049
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Filing Dt:
|
12/13/2012
|
Publication #:
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|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SILICIDE CONTACTS ON NON-PLANAR STRUCTURES
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|
Patent #:
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|
Issue Dt:
|
08/26/2014
|
Application #:
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13716686
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Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE BY PERFORMING AN EPITAXIAL GROWTH PROCESS
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|
Patent #:
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|
Issue Dt:
|
04/21/2015
|
Application #:
|
13716731
|
Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
Title:
|
ALTERING CAPACITANCE OF MIM CAPACITOR HAVING REACTIVE LAYER THEREIN
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|
|
Patent #:
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|
Issue Dt:
|
03/29/2016
|
Application #:
|
13716758
|
Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
METHODS OF FORMING FINS FOR A FINFET DEVICE WHEREIN THE FINS HAVE A HIGH GERMANIUM CONTENT
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|
|
Patent #:
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|
Issue Dt:
|
02/03/2015
|
Application #:
|
13717079
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Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
THERMAL SPIN TORQURE TRANSFER MAGNETORESISTIVE RANDOM ACCESS MEMORY
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|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13717235
|
Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
DEVICE STRUCTURE WITH INCREASED CONTACT AREA AND REDUCED GATE CAPACITANCE
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|
|
Patent #:
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|
Issue Dt:
|
12/30/2014
|
Application #:
|
13717701
|
Filing Dt:
|
12/18/2012
|
Publication #:
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|
Pub Dt:
|
06/19/2014
| | | | |
Title:
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PHASE CHANGE MEMORY CELL WITH LARGE ELECTRODE CONTACT AREA
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|
|
Patent #:
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|
Issue Dt:
|
09/09/2014
|
Application #:
|
13718346
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Filing Dt:
|
12/18/2012
|
Publication #:
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|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE
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|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13718748
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Filing Dt:
|
12/18/2012
|
Title:
|
FIELD-EFFECT INTER-DIGITATED BACK CONTACT PHOTOVOLTAIC DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13718767
|
Filing Dt:
|
12/18/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
ACCURATE CONTROL OF DISTANCE BETWEEN SUSPENDED SEMICONDUCTOR NANOWIRES AND SUBSTRATE SURFACE
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|
|
Patent #:
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|
Issue Dt:
|
06/16/2015
|
Application #:
|
13719965
|
Filing Dt:
|
12/19/2012
|
Publication #:
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|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
PIEZOELECTRONIC MEMORY
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|
|
Patent #:
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|
Issue Dt:
|
12/23/2014
|
Application #:
|
13721991
|
Filing Dt:
|
12/20/2012
|
Publication #:
|
|
Pub Dt:
|
06/26/2014
| | | | |
Title:
|
PACKAGING STRUCTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13722130
|
Filing Dt:
|
12/20/2012
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
Title:
|
PORTABLE ELECTRONIC DEVICE CASE WITH ACTIVE THERMAL PROTECTION
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|
|
Patent #:
|
|
Issue Dt:
|
04/07/2015
|
Application #:
|
13725837
|
Filing Dt:
|
12/21/2012
|
Publication #:
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|
Pub Dt:
|
06/26/2014
| | | | |
Title:
|
PRECISION POLYSILICON RESISTORS
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|
|
Patent #:
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|
Issue Dt:
|
11/18/2014
|
Application #:
|
13726732
|
Filing Dt:
|
12/26/2012
|
Publication #:
|
|
Pub Dt:
|
06/26/2014
| | | | |
Title:
|
OPTIMIZING LITHOGRAPHIC PROCESSES USING LASER ANNEALING TECHNIQUES
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Patent #:
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Issue Dt:
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05/20/2014
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Application #:
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13728438
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Filing Dt:
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12/27/2012
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Title:
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METHODS OF FORMING A THREE-DIMENSIONAL SEMICONDUCTOR DEVICE WITH A NANOWIRE CHANNEL STRUCTURE
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Patent #:
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Issue Dt:
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11/24/2015
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Application #:
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13729843
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Filing Dt:
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12/28/2012
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Publication #:
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Pub Dt:
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07/03/2014
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Title:
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METHODS OF USING A TRENCH SALICIDE ROUTING LAYER
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13732474
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Filing Dt:
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01/02/2013
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Publication #:
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Pub Dt:
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07/03/2014
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Title:
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In-Line Transistor Bandwidth Measurement
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Patent #:
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Issue Dt:
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05/19/2015
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Application #:
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13732494
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Filing Dt:
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01/02/2013
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Publication #:
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Pub Dt:
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07/03/2014
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Title:
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INTERGRATING A SILICON PHOTONICS PHOTODETECTOR WITH CMOS DEVICES
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Patent #:
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Issue Dt:
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04/07/2015
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Application #:
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13732954
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Filing Dt:
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01/02/2013
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Publication #:
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Pub Dt:
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07/03/2014
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Title:
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HYBRID LATCH AND FUSE SCHEME FOR MEMORY REPAIR
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Patent #:
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Issue Dt:
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02/25/2014
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Application #:
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13732989
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Filing Dt:
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01/02/2013
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Title:
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SPARE CELL INSERTION BASED ON REACHABLE STATE ANALYSIS
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Patent #:
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Issue Dt:
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07/15/2014
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Application #:
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13733016
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Filing Dt:
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01/02/2013
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Publication #:
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Pub Dt:
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07/03/2014
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Title:
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SOFT PIN INSERTION DURING PHYSICAL DESIGN
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Patent #:
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Issue Dt:
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05/24/2016
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Application #:
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13733182
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Filing Dt:
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01/03/2013
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Publication #:
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Pub Dt:
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07/03/2014
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Title:
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ACID-STRIPPABLE SILICON-CONTAINING ANTIREFLECTIVE COATING
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Patent #:
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Issue Dt:
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02/10/2015
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Application #:
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13733243
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Filing Dt:
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01/03/2013
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Publication #:
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Pub Dt:
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07/03/2014
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Title:
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FABRICATING POLYSILICON MOS DEVICES AND PASSIVE ESD DEVICES
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Patent #:
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Issue Dt:
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10/07/2014
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Application #:
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13733248
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Filing Dt:
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01/03/2013
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Publication #:
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Pub Dt:
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07/03/2014
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Title:
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TEST COVERAGE OF INTEGRATED CIRCUITS WITH MASKING PATTERN SELECTION
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Patent #:
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Issue Dt:
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10/14/2014
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Application #:
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13733282
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Filing Dt:
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01/03/2013
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Publication #:
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Pub Dt:
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07/03/2014
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Title:
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GATE ELECTRODE(S) AND CONTACT STRUCTURE(S), AND METHODS OF FABRICATION THEREOF
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13733540
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Filing Dt:
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01/03/2013
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Publication #:
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Pub Dt:
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07/03/2014
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Title:
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REMOVAL OF MASKING MATERIAL
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Patent #:
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Issue Dt:
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06/24/2014
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Application #:
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13734499
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Filing Dt:
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01/04/2013
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Publication #:
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Pub Dt:
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05/16/2013
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Title:
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SEMICONDUCTOR STRUCTURE AND CIRCUIT INCLUDING ORDERED ARRANGEMENT OF GRAPHENE NANORIBBONS, AND METHODS OF FORMING SAME
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13734501
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Filing Dt:
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01/04/2013
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Publication #:
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Pub Dt:
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07/10/2014
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Title:
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THERMAL DISSIPATIVE RETRACTABLE FLEX ASSEMBLY
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Patent #:
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Issue Dt:
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01/27/2015
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Application #:
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13735315
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Filing Dt:
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01/07/2013
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Publication #:
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Pub Dt:
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07/10/2014
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Title:
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SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES
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Patent #:
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Issue Dt:
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11/25/2014
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Application #:
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13736111
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Filing Dt:
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01/08/2013
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Publication #:
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Pub Dt:
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07/10/2014
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Title:
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METHOD OF FORMING FINFET OF VARIABLE CHANNEL WIDTH
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Patent #:
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Issue Dt:
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04/14/2015
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Application #:
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13736183
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Filing Dt:
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01/08/2013
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Publication #:
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Pub Dt:
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07/10/2014
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Title:
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COMPRESSIVE STRAINED III-V COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE
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Patent #:
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Issue Dt:
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03/25/2014
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Application #:
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13736189
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Filing Dt:
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01/08/2013
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Publication #:
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Pub Dt:
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05/16/2013
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Title:
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MEMORY CELL WITH POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL
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Patent #:
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Issue Dt:
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08/05/2014
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Application #:
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13736672
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Filing Dt:
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01/08/2013
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Publication #:
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Pub Dt:
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07/10/2014
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Title:
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PHOTONICS DEVICE AND CMOS DEVICE HAVING A COMMON GATE
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Patent #:
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Issue Dt:
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04/07/2015
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Application #:
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13737002
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Filing Dt:
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01/09/2013
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Publication #:
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Pub Dt:
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07/10/2014
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Title:
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FINFET WITH DIELECTRIC ISOLATION BY SILICON-ON-NOTHING AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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01/06/2015
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Application #:
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13737089
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Filing Dt:
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01/09/2013
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Publication #:
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Pub Dt:
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07/10/2014
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Title:
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STRAINED FINFET WITH AN ELECTRICALLY ISOLATED CHANNEL
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Patent #:
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Issue Dt:
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09/09/2014
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Application #:
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13737099
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Filing Dt:
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01/09/2013
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Publication #:
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Pub Dt:
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07/10/2014
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Title:
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DUAL MANDREL SIDEWALL IMAGE TRANSFER PROCESSES
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Patent #:
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Issue Dt:
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07/01/2014
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Application #:
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13737231
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Filing Dt:
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01/09/2013
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Publication #:
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Pub Dt:
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07/10/2014
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Title:
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Automatic Generation of Wire Tag Lists for a Metal Stack
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Patent #:
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Issue Dt:
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09/30/2014
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Application #:
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13738139
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Filing Dt:
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01/10/2013
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Publication #:
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Pub Dt:
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07/10/2014
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Title:
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ELECTROLESS PLATING OF COBALT ALLOYS FOR ON CHIP INDUCTORS
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Patent #:
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Issue Dt:
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12/02/2014
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Application #:
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13738270
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Filing Dt:
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01/10/2013
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Publication #:
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Pub Dt:
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07/10/2014
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Title:
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REDUCING GATE HEIGHT VARIANCE DURING SEMICONDUCTOR DEVICE FORMATION
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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13738298
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Filing Dt:
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01/10/2013
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Publication #:
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Pub Dt:
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07/10/2014
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Title:
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SELF-FORMED NANOMETER CHANNEL AT WAFER SCALE
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Patent #:
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Issue Dt:
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10/14/2014
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Application #:
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13738367
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Filing Dt:
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01/10/2013
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Publication #:
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Pub Dt:
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05/16/2013
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Title:
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ON CHIP INDUCTOR WITH FREQUENCY DEPENDENT INDUCTANCE
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Patent #:
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Issue Dt:
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12/31/2013
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Application #:
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13738435
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Filing Dt:
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01/10/2013
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Title:
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FIN REMOVAL METHOD
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13738532
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Filing Dt:
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01/10/2013
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Publication #:
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Pub Dt:
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07/10/2014
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Title:
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SILICON-ON-INSULATOR HEAT SINK
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Patent #:
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Issue Dt:
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06/10/2014
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Application #:
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13739123
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Filing Dt:
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01/11/2013
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Publication #:
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Pub Dt:
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05/23/2013
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Title:
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REDUCTION OF ALERTS IN INFORMATION TECHNOLOGY SYSTEMS
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Patent #:
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Issue Dt:
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02/18/2014
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Application #:
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13739222
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Filing Dt:
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01/11/2013
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Publication #:
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Pub Dt:
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05/16/2013
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Title:
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SOLUTIONS FOR CONTROLLING BULK BIAS VOLTAGE IN AN EXTREMELY THIN SILICON-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT CHIP
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Patent #:
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Issue Dt:
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08/25/2015
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Application #:
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13741416
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Filing Dt:
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01/15/2013
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Publication #:
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Pub Dt:
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07/17/2014
| | | | |
Title:
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BURIED WAVEGUIDE PHOTODETECTOR
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Patent #:
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Issue Dt:
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03/24/2015
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Application #:
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13741611
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Filing Dt:
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01/15/2013
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Publication #:
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Pub Dt:
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07/17/2014
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Title:
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LITHOGRAPHIC MATERIAL STACK INCLUDING A METAL-COMPOUND HARD MASK
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Patent #:
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Issue Dt:
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03/24/2015
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Application #:
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13741638
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Filing Dt:
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01/15/2013
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Publication #:
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Pub Dt:
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07/17/2014
| | | | |
Title:
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TITANIUM OXYNITRIDE HARD MASK FOR LITHOGRAPHIC PATTERNING
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Patent #:
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Issue Dt:
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10/21/2014
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Application #:
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13741645
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Filing Dt:
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01/15/2013
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Publication #:
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Pub Dt:
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07/17/2014
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Title:
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AUTOMATING INTEGRATED CIRCUIT DEVICE LIBRARY GENERATION IN MODEL BASED METROLOGY
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Patent #:
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Issue Dt:
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07/29/2014
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Application #:
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13741947
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Filing Dt:
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01/15/2013
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Publication #:
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Pub Dt:
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07/17/2014
| | | | |
Title:
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HYBRID CONDUCTOR THROUGH-SILICON-VIA FOR POWER DISTRIBUTION AND SIGNAL TRANSMISSION
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Patent #:
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Issue Dt:
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01/28/2014
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Application #:
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13742508
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Filing Dt:
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01/16/2013
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Publication #:
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Pub Dt:
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05/23/2013
| | | | |
Title:
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SEMICONDUCTOR DEVICE HEAT DISSIPATION STRUCTURE
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Patent #:
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Issue Dt:
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10/28/2014
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Application #:
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13742916
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Filing Dt:
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01/16/2013
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Publication #:
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Pub Dt:
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05/23/2013
| | | | |
Title:
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SEALED AIR GAP FOR SEMICONDUCTOR CHIP
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Patent #:
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Issue Dt:
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01/06/2015
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Application #:
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13743454
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Filing Dt:
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01/17/2013
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Publication #:
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Pub Dt:
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07/17/2014
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Title:
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METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICE
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Patent #:
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Issue Dt:
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12/23/2014
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Application #:
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13743886
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Filing Dt:
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01/17/2013
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Publication #:
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Pub Dt:
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07/17/2014
| | | | |
Title:
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METHOD OF FORMING STEP DOPING CHANNEL PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR AND RESULTING DEVICE
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Patent #:
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Issue Dt:
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09/27/2016
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Application #:
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13743935
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Filing Dt:
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01/17/2013
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Publication #:
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Pub Dt:
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06/06/2013
| | | | |
Title:
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METHOD AND APPARATUS FOR OPTICAL MODULATION
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