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Reel/Frame:	036550/0001			Pages:	983
		Recorded:	09/03/2015
Attorney Dkt #:	3718.266
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14793
Page 49 of 148
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Patent #:	7893493	Issue Dt:	02/22/2011	Application #:	11456326	Filing Dt:	07/10/2006
Publication #:	US20080006876	Pub Dt:	01/10/2008
Title:	STACKING FAULT REDUCTION IN EPITAXIALLY GROWN SILICON

Patent #:	7456702	Issue Dt:	11/25/2008	Application #:	11456351	Filing Dt:	07/10/2006
Publication #:	US20080258849	Pub Dt:	10/23/2008
Title:	LOW PASS METAL POWDER FILTER

Patent #:	7396757	Issue Dt:	07/08/2008	Application #:	11456721	Filing Dt:	07/11/2006
Publication #:	US20080014731	Pub Dt:	01/17/2008
Title:	INTERCONNECT STRUCTURE WITH DIELECTRIC AIR GAPS

Patent #:	7627840	Issue Dt:	12/01/2009	Application #:	11457174	Filing Dt:	07/13/2006
Publication #:	US20080016477	Pub Dt:	01/17/2008
Title:	METHOD FOR SOFT ERROR MODELING WITH DOUBLE CURRENT PULSE

Patent #:	NONE	Issue Dt:		Application #:	11457332	Filing Dt:	07/13/2006
Publication #:	US20080016475	Pub Dt:	01/17/2008
Title:	Method, System and Program Product for Automated Transistor Tuning in an Integrated Circuit Design

Patent #:	7724559	Issue Dt:	05/25/2010	Application #:	11457477	Filing Dt:	07/14/2006
Publication #:	US20080025073	Pub Dt:	01/31/2008
Title:	SELF-REFERENCED MATCH-LINE SENSE AMPLIFIER FOR CONTENT ADDRESSABLE MEMORIES

Patent #:	7448007	Issue Dt:	11/04/2008	Application #:	11457495	Filing Dt:	07/14/2006
Publication #:	US20080016479	Pub Dt:	01/17/2008
Title:	SLEW CONSTRAINED MINIMUM COST BUFFERING

Patent #:	NONE	Issue Dt:		Application #:	11457573	Filing Dt:	07/14/2006
Publication #:	US20060242825	Pub Dt:	11/02/2006
Title:	Method of making a circuitized substrate

Patent #:	7417480	Issue Dt:	08/26/2008	Application #:	11457637	Filing Dt:	07/14/2006
Publication #:	US20080012617	Pub Dt:	01/17/2008
Title:	DUTY CYCLE CORRECTION CIRCUIT WHOSE OPERATION IS LARGELY INDEPENDENT OF OPERATING VOLTAGE AND PROCESS

Patent #:	7490305	Issue Dt:	02/10/2009	Application #:	11457865	Filing Dt:	07/17/2006
Publication #:	US20080016480	Pub Dt:	01/17/2008
Title:	METHOD FOR DRIVING VALUES TO DC ADJUSTED/UNTIMED NETS TO IDENTIFY TIMING PROBLEMS

Patent #:	NONE	Issue Dt:		Application #:	11457916	Filing Dt:	07/17/2006
Publication #:	US20080046772	Pub Dt:	02/21/2008
Title:	SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION

Patent #:	7387930	Issue Dt:	06/17/2008	Application #:	11458120	Filing Dt:	07/18/2006
Publication #:	US20060275974	Pub Dt:	12/07/2006
Title:	METHOD OF FABRICATING A BOTTLE TRENCH AND A BOTTLE TRENCH CAPACITOR

Patent #:	7759606	Issue Dt:	07/20/2010	Application #:	11458161	Filing Dt:	07/18/2006
Publication #:	US20060243712	Pub Dt:	11/02/2006
Title:	METHOD AND APPARATUS FOR REPAIR OF REFLECTIVE PHOTOMASKS

Patent #:	7368355	Issue Dt:	05/06/2008	Application #:	11458250	Filing Dt:	07/18/2006
Publication #:	US20060255410	Pub Dt:	11/16/2006
Title:	FINFET TRANSISTOR AND CIRCUIT

Patent #:	7691717	Issue Dt:	04/06/2010	Application #:	11458494	Filing Dt:	07/19/2006
Publication #:	US20080122574	Pub Dt:	05/29/2008
Title:	POLYSILICON CONTAINING RESISTOR WITH ENHANCED SHEET RESISTANCE PRECISION AND METHOD FOR FABRICATION THEREOF

Patent #:	7405620	Issue Dt:	07/29/2008	Application #:	11458712	Filing Dt:	07/20/2006
Publication #:	US20080018400	Pub Dt:	01/24/2008
Title:	DIFFERENTIAL AMPLIFIER AND METHOD

Patent #:	7473633	Issue Dt:	01/06/2009	Application #:	11458726	Filing Dt:	07/20/2006
Publication #:	US20060292861	Pub Dt:	12/28/2006
Title:	METHOD FOR MAKING INTEGRATED CIRCUIT CHIP HAVING CARBON NANOTUBE COMPOSITE INTERCONNECTION VIAS

Patent #:	7573085	Issue Dt:	08/11/2009	Application #:	11458828	Filing Dt:	07/20/2006
Publication #:	US20060275978	Pub Dt:	12/07/2006
Title:	DEEP TRENCH FORMATION IN SEMICONDUCTOR DEVICE FABRICATION

Patent #:	7382149	Issue Dt:	06/03/2008	Application #:	11459367	Filing Dt:	07/24/2006
Publication #:	US20080018356	Pub Dt:	01/24/2008
Title:	A SYSTEM FOR ACQUIRING DEVICE PARAMETERS

Patent #:	7473594	Issue Dt:	01/06/2009	Application #:	11459730	Filing Dt:	07/25/2006
Publication #:	US20080026516	Pub Dt:	01/31/2008
Title:	RAISED STI STRUCTURE AND SUPERDAMASCENE TECHNIQUE FOR NMOSFET PERFORMANCE ENHANCEMENT WITH EMBEDDED SILICON CARBON

Patent #:	7545664	Issue Dt:	06/09/2009	Application #:	11459957	Filing Dt:	07/26/2006
Publication #:	US20080028176	Pub Dt:	01/31/2008
Title:	MEMORY SYSTEM HAVING SELF TIMED DAISY CHAINED MEMORY CHIPS

Patent #:	7345901	Issue Dt:	03/18/2008	Application #:	11459968	Filing Dt:	07/26/2006
Publication #:	US20080025130	Pub Dt:	01/31/2008
Title:	COMPUTER SYSTEM HAVING DAISY CHAINED SELF TIMED MEMORY CHIPS

Patent #:	7342816	Issue Dt:	03/11/2008	Application #:	11459994	Filing Dt:	07/26/2006
Publication #:	US20080031077	Pub Dt:	02/07/2008
Title:	DAISY CHAINABLE MEMORY CHIP

Patent #:	7660942	Issue Dt:	02/09/2010	Application #:	11459997	Filing Dt:	07/26/2006
Publication #:	US20080028161	Pub Dt:	01/31/2008
Title:	DAISY CHAINABLE SELF TIMED MEMORY CHIP

Patent #:	7470615	Issue Dt:	12/30/2008	Application #:	11460010	Filing Dt:	07/26/2006
Publication #:	US20080026513	Pub Dt:	01/31/2008
Title:	SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED DEVICE CONTACTS

Patent #:	7482261	Issue Dt:	01/27/2009	Application #:	11460011	Filing Dt:	07/26/2006
Publication #:	US20080026554	Pub Dt:	01/31/2008
Title:	INTERCONNECT STRUCTURE FOR BEOL APPLICATIONS

Patent #:	7394113	Issue Dt:	07/01/2008	Application #:	11460013	Filing Dt:	07/26/2006
Publication #:	US20080121936	Pub Dt:	05/29/2008
Title:	SELF-ALIGNMENT SCHEME FOR A HETEROJUNCTION BIPOLAR TRANSISTOR

Patent #:	7584369	Issue Dt:	09/01/2009	Application #:	11460014	Filing Dt:	07/26/2006
Publication #:	US20080028244	Pub Dt:	01/31/2008
Title:	METHOD AND APPARATUS FOR MONITORING AND CONTROLLING HEAT GENERATION IN A MULTI-CORE PROCESSOR

Patent #:	NONE	Issue Dt:		Application #:	11460019	Filing Dt:	07/26/2006
Publication #:	US20080026541	Pub Dt:	01/31/2008
Title:	AIR-GAP INTERCONNECT STRUCTURES WITH SELECTIVE CAP

Patent #:	7643591	Issue Dt:	01/05/2010	Application #:	11460065	Filing Dt:	07/26/2006
Publication #:	US20080043890	Pub Dt:	02/21/2008
Title:	TRANSITION BALANCING FOR NOISE REDUCTION /DI/DT REDUCTION DURING DESIGN, SYNTHESIS, AND PHYSICAL DESIGN

Patent #:	7453151	Issue Dt:	11/18/2008	Application #:	11460314	Filing Dt:	07/27/2006
Publication #:	US20080122096	Pub Dt:	05/29/2008
Title:	METHODS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES

Patent #:	7307911	Issue Dt:	12/11/2007	Application #:	11460464	Filing Dt:	07/27/2006
Title:	APPARATUS AND METHOD FOR IMPROVING SENSING MARGIN OF ELECTRICALLY PROGRAMMABLE FUSES

Patent #:	7693678	Issue Dt:	04/06/2010	Application #:	11460504	Filing Dt:	07/27/2006
Publication #:	US20080027670	Pub Dt:	01/31/2008
Title:	INTEGRATED CIRCUIT TEMPERATURE MEASUREMENT METHODS AND APPARATUSES

Patent #:	7480883	Issue Dt:	01/20/2009	Application #:	11460537	Filing Dt:	07/27/2006
Publication #:	US20070028193	Pub Dt:	02/01/2007
Title:	MULTIPLE VOLTAGE INTEGRATED CIRCUIT AND DESIGN METHOD THEREFOR

Patent #:	8030649	Issue Dt:	10/04/2011	Application #:	11460751	Filing Dt:	07/28/2006
Publication #:	US20080023700	Pub Dt:	01/31/2008
Title:	SCAN TESTING IN SINGLE-CHIP MULTICORE SYSTEMS

Patent #:	7297618	Issue Dt:	11/20/2007	Application #:	11460762	Filing Dt:	07/28/2006
Title:	FULLY SILICIDED GATE ELECTRODES AND METHOD OF MAKING THE SAME

Patent #:	7488679	Issue Dt:	02/10/2009	Application #:	11461137	Filing Dt:	07/31/2006
Publication #:	US20080026568	Pub Dt:	01/31/2008
Title:	INTERCONNECT STRUCTURE AND PROCESS OF MAKING THE SAME

Patent #:	7470985	Issue Dt:	12/30/2008	Application #:	11461208	Filing Dt:	07/31/2006
Publication #:	US20080023827	Pub Dt:	01/31/2008
Title:	SOLDER CONNECTOR STRUCTURE AND METHOD

Patent #:	7455939	Issue Dt:	11/25/2008	Application #:	11461217	Filing Dt:	07/31/2006
Publication #:	US20080026298	Pub Dt:	01/31/2008
Title:	METHOD OF IMPROVING GRATING TEST PATTERN FOR LITHOGRAPHY MONITORING AND CONTROLING

Patent #:	7378338	Issue Dt:	05/27/2008	Application #:	11461220	Filing Dt:	07/31/2006
Publication #:	US20060264048	Pub Dt:	11/23/2006
Title:	A METHOD OF FORMING AN INTERCONNECT STRUCTURE DIFFUSION BARRIER WITH HIGH NITROGEN CONTENT

Patent #:	7398494	Issue Dt:	07/08/2008	Application #:	11461469	Filing Dt:	08/01/2006
Publication #:	US20070050739	Pub Dt:	03/01/2007
Title:	METHOD FOR PERFORMING VERIFICATION OF LOGIC CIRCUITS

Patent #:	7473643	Issue Dt:	01/06/2009	Application #:	11461623	Filing Dt:	08/01/2006
Publication #:	US20060264026	Pub Dt:	11/23/2006
Title:	DENDRITE GROWTH CONTROL CIRCUIT

Patent #:	7617422	Issue Dt:	11/10/2009	Application #:	11461657	Filing Dt:	08/01/2006
Publication #:	US20080126330	Pub Dt:	05/29/2008
Title:	METHOD, SYSTEM, AND PROGRAM PRODUCT FOR MANAGING DATA DECAY

Patent #:	7511528	Issue Dt:	03/31/2009	Application #:	11461788	Filing Dt:	08/02/2006
Publication #:	US20080030223	Pub Dt:	02/07/2008
Title:	DEVICE AND METHOD TO ELIMINATE STEP RESPONSE POWER SUPPLY PERTURBATION

Patent #:	7472364	Issue Dt:	12/30/2008	Application #:	11461857	Filing Dt:	08/02/2006
Publication #:	US20080034339	Pub Dt:	02/07/2008
Title:	METHOD OF MATCHING LAYOUT SHAPES PATTERNS IN AN INTEGRATED CIRCUIT USING WALSH PATTERNS.

Patent #:	7405139	Issue Dt:	07/29/2008	Application #:	11462124	Filing Dt:	08/03/2006
Publication #:	US20080122037	Pub Dt:	05/29/2008
Title:	PREVENTION OF BACKSIDE CRACKS IN SEMICONDUCTOR CHIPS OR WAFERS USING BACKSIDE FILM OR BACKSIDE WET ETCH

Patent #:	7475366	Issue Dt:	01/06/2009	Application #:	11462508	Filing Dt:	08/04/2006
Publication #:	US20080034337	Pub Dt:	02/07/2008
Title:	INTEGRATED CIRCUIT DESIGN CLOSURE FOR SELECTIVE VOLTAGE BINNING

Patent #:	7847358	Issue Dt:	12/07/2010	Application #:	11462648	Filing Dt:	08/04/2006
Publication #:	US20060270136	Pub Dt:	11/30/2006
Title:	HIGH PERFORMANCE STRAINED CMOS DEVICES

Patent #:	7378712	Issue Dt:	05/27/2008	Application #:	11463039	Filing Dt:	08/08/2006
Publication #:	US20070194385	Pub Dt:	08/23/2007
Title:	GATE STACKS

Patent #:	7405677	Issue Dt:	07/29/2008	Application #:	11463269	Filing Dt:	08/08/2006
Publication #:	US20080036629	Pub Dt:	02/14/2008
Title:	APPARATUS, SYSTEM, AND METHOD FOR INCREMENTAL ENCODING CONVERSION OF XML DATA USING JAVA

Patent #:	7316940	Issue Dt:	01/08/2008	Application #:	11463348	Filing Dt:	08/09/2006
Publication #:	US20060292830	Pub Dt:	12/28/2006
Title:	CHIP DICING

Patent #:	7494915	Issue Dt:	02/24/2009	Application #:	11463447	Filing Dt:	08/09/2006
Publication #:	US20060292852	Pub Dt:	12/28/2006
Title:	BACK END INTERCONNECT WITH A SHAPED INTERFACE

Patent #:	7436030	Issue Dt:	10/14/2008	Application #:	11463640	Filing Dt:	08/10/2006
Publication #:	US20080036012	Pub Dt:	02/14/2008
Title:	STRAINED MOSFETS ON SEPARATED SILICON LAYERS

Patent #:	NONE	Issue Dt:		Application #:	11463642	Filing Dt:	08/10/2006
Publication #:	US20080038913	Pub Dt:	02/14/2008
Title:	AN ALUMINUM-FREE WIRE BOND PAD

Patent #:	NONE	Issue Dt:		Application #:	11463911	Filing Dt:	08/11/2006
Publication #:	US20080035921	Pub Dt:	02/14/2008
Title:	METHOD AND CIRCUIT FOR DETECTING AND COMPENSATING FOR A DEGRADATION OF A SEMICONDUCTOR DEVICE

Patent #:	7450413	Issue Dt:	11/11/2008	Application #:	11463917	Filing Dt:	08/11/2006
Publication #:	US20080037313	Pub Dt:	02/14/2008
Title:	CONFIGURABLE SRAM SYSTEM AND METHOD

Patent #:	7480877	Issue Dt:	01/20/2009	Application #:	11463958	Filing Dt:	08/11/2006
Publication #:	US20080040694	Pub Dt:	02/14/2008
Title:	METHODS AND APPARATUS FOR BOOLEAN EQUIVALENCY CHECKING IN THE PRESENCE OF VOTING LOGIC

Patent #:	7444277	Issue Dt:	10/28/2008	Application #:	11464009	Filing Dt:	08/11/2006
Publication #:	US20070078639	Pub Dt:	04/05/2007
Title:	FACILITATING SIMULATION OF A MODEL WITHIN A DISTRIBUTED ENVIRONMENT

Patent #:	8105955	Issue Dt:	01/31/2012	Application #:	11464664	Filing Dt:	08/15/2006
Publication #:	US20080121926	Pub Dt:	05/29/2008
Title:	INTEGRATED CIRCUIT SYSTEM WITH CARBON AND NON-CARBON SILICON

Patent #:	7273770	Issue Dt:	09/25/2007	Application #:	11464959	Filing Dt:	08/16/2006
Publication #:	US20060281224	Pub Dt:	12/14/2006
Title:	COMPLIANT PASSIVATED EDGE SEAL FOR LOW-K INTERCONNECT STRUCTURES

Patent #:	7759260	Issue Dt:	07/20/2010	Application #:	11465030	Filing Dt:	08/16/2006
Publication #:	US20060281265	Pub Dt:	12/14/2006
Title:	SELECTIVE NITRIDATION OF GATE OXIDES

Patent #:	7824568	Issue Dt:	11/02/2010	Application #:	11465176	Filing Dt:	08/17/2006
Publication #:	US20080042099	Pub Dt:	02/21/2008
Title:	SOLUTION FOR FORMING POLISHING SLURRY, POLISHING SLURRY AND RELATED METHODS

Patent #:	7642020	Issue Dt:	01/05/2010	Application #:	11465227	Filing Dt:	08/17/2006
Publication #:	US20080044748	Pub Dt:	02/21/2008
Title:	METHOD FOR SEPARATING OPTICAL AND RESIST EFFECTS IN PROCESS MODELS

Patent #:	7930667	Issue Dt:	04/19/2011	Application #:	11465473	Filing Dt:	08/18/2006
Publication #:	US20080046852	Pub Dt:	02/21/2008
Title:	SYSTEM AND METHOD OF AUTOMATED WIRE AND VIA LAYOUT OPTIMIZATION DESCRIPTION

Patent #:	7752480	Issue Dt:	07/06/2010	Application #:	11465639	Filing Dt:	08/18/2006
Publication #:	US20080046776	Pub Dt:	02/21/2008
Title:	SYSTEM AND METHOD FOR SWITCHING DIGITAL CIRCUIT CLOCK NET DRIVER WITHOUT LOSING CLOCK PULSES

Patent #:	7790558	Issue Dt:	09/07/2010	Application #:	11465663	Filing Dt:	08/18/2006
Publication #:	US20060281272	Pub Dt:	12/14/2006
Title:	METHOD AND APPARATUS FOR INCREASE STRAIN EFFECT IN A TRANSISTOR CHANNEL

Patent #:	NONE	Issue Dt:		Application #:	11465799	Filing Dt:	08/19/2006
Publication #:	US20080044967	Pub Dt:	02/21/2008
Title:	INTEGRATED CIRCUIT SYSTEM HAVING STRAINED TRANSISTOR

Patent #:	7498256	Issue Dt:	03/03/2009	Application #:	11465865	Filing Dt:	08/21/2006
Publication #:	US20080042291	Pub Dt:	02/21/2008
Title:	COPPER CONTACT VIA STRUCTURE USING HYBRID BARRIER LAYER

Patent #:	7487484	Issue Dt:	02/03/2009	Application #:	11466120	Filing Dt:	08/22/2006
Publication #:	US20060277515	Pub Dt:	12/07/2006
Title:	METHOD, SYSTEM AND STORAGE MEDIUM FOR DETERMINING CIRCUIT PLACEMENT

Patent #:	7336100	Issue Dt:	02/26/2008	Application #:	11466754	Filing Dt:	08/23/2006
Publication #:	US20060279334	Pub Dt:	12/14/2006
Title:	SINGLE SUPPLY LEVEL CONVERTER

Patent #:	7790540	Issue Dt:	09/07/2010	Application #:	11467186	Filing Dt:	08/25/2006
Publication #:	US20080048271	Pub Dt:	02/28/2008
Title:	STRUCTURE AND METHOD TO USE LOW K STRESS LINER TO REDUCE PARASITIC CAPACITANCE

Patent #:	7394089	Issue Dt:	07/01/2008	Application #:	11467294	Filing Dt:	08/25/2006
Publication #:	US20080048169	Pub Dt:	02/28/2008
Title:	HEAT-SHIELDED LOW POWER PCM-BASED REPROGRAMMABLE EFUSE DEVICE

Patent #:	7462915	Issue Dt:	12/09/2008	Application #:	11467446	Filing Dt:	08/25/2006
Publication #:	US20060286786	Pub Dt:	12/21/2006
Title:	METHOD AND APPARATUS FOR INCREASE STRAIN EFFECT IN A TRANSISTOR CHANNEL

Patent #:	8171438	Issue Dt:	05/01/2012	Application #:	11467493	Filing Dt:	08/25/2006
Publication #:	US20080127106	Pub Dt:	05/29/2008
Title:	VERIFICATION OF A PROGRAM PARTITIONED ACCORDING TO THE CONTROL FLOW INFORMATION OF THE PROGRAM

Patent #:	7372158	Issue Dt:	05/13/2008	Application #:	11467593	Filing Dt:	08/28/2006
Publication #:	US20070004206	Pub Dt:	01/04/2007
Title:	IMPROVED HDP-BASED ILD CAPPING LAYER

Patent #:	7560382	Issue Dt:	07/14/2009	Application #:	11467712	Filing Dt:	08/28/2006
Publication #:	US20080048297	Pub Dt:	02/28/2008
Title:	EMBEDDED INTERCONNECTS, AND METHODS FOR FORMING SAME

Patent #:	NONE	Issue Dt:		Application #:	11467721	Filing Dt:	08/28/2006
Publication #:	US20080050863	Pub Dt:	02/28/2008
Title:	SEMICONDUCTOR STRUCTURE INCLUDING MULTIPLE STRESSED LAYERS

Patent #:	7927664	Issue Dt:	04/19/2011	Application #:	11467862	Filing Dt:	08/28/2006
Publication #:	US20080050530	Pub Dt:	02/28/2008
Title:	METHOD OF STEP-AND-FLASH IMPRINT LITHOGRAPHY

Patent #:	7413967	Issue Dt:	08/19/2008	Application #:	11468030	Filing Dt:	08/29/2006
Publication #:	US20060289959	Pub Dt:	12/28/2006
Title:	YIELD IMPROVEMENT IN SILICON-GERMANIUM EPITAXIAL GROWTH

Patent #:	7816231	Issue Dt:	10/19/2010	Application #:	11468068	Filing Dt:	08/29/2006
Publication #:	US20080054313	Pub Dt:	03/06/2008
Title:	DEVICE STRUCTURES INCLUDING BACKSIDE CONTACTS, AND METHODS FOR FORMING SAME

Patent #:	7448008	Issue Dt:	11/04/2008	Application #:	11468078	Filing Dt:	08/29/2006
Publication #:	US20080059925	Pub Dt:	03/06/2008
Title:	METHOD, SYSTEM, AND PROGRAM PRODUCT FOR AUTOMATED VERIFICATION OF GATING LOGIC USING FORMAL VERIFICATION

Patent #:	7908906	Issue Dt:	03/22/2011	Application #:	11468089	Filing Dt:	08/29/2006
Publication #:	US20080057569	Pub Dt:	03/06/2008
Title:	FLUIDIC TEST APPARATUS AND METHOD

Patent #:	7510960	Issue Dt:	03/31/2009	Application #:	11468102	Filing Dt:	08/29/2006
Publication #:	US20080054392	Pub Dt:	03/06/2008
Title:	BRIDGE FOR SEMICONDUCTOR INTERNAL NODE

Patent #:	7462522	Issue Dt:	12/09/2008	Application #:	11468402	Filing Dt:	08/30/2006
Publication #:	US20080057653	Pub Dt:	03/06/2008
Title:	METHOD AND STRUCTURE FOR IMPROVING DEVICE PERFORMANCE VARIATION IN DUAL STRESS LINER TECHNOLOGY

Patent #:	8754446	Issue Dt:	06/17/2014	Application #:	11468403	Filing Dt:	08/30/2006
Publication #:	US20080121931	Pub Dt:	05/29/2008
Title:	SEMICONDUCTOR STRUCTURE HAVING UNDERCUT-GATE-OXIDE GATE STACK ENCLOSED BY PROTECTIVE BARRIER MATERIAL

Patent #:	7393739	Issue Dt:	07/01/2008	Application #:	11468512	Filing Dt:	08/30/2006
Publication #:	US20080054306	Pub Dt:	03/06/2008
Title:	DEMULTIPLEXERS USING TRANSISTORS FOR ACCESSING MEMORY CELL ARRAYS

Patent #:	NONE	Issue Dt:		Application #:	11468543	Filing Dt:	08/30/2006
Publication #:	US20060292789	Pub Dt:	12/28/2006
Title:	STRUCTURE AND METHOD FOR COLLAR SELF-ALIGNED TO BURIED PLATE

Patent #:	7408373	Issue Dt:	08/05/2008	Application #:	11468938	Filing Dt:	08/31/2006
Publication #:	US20070013386	Pub Dt:	01/18/2007
Title:	DEVICE FOR PROBE CARD POWER BUS VOLTAGE DROP REDUCTION

Patent #:	7675118	Issue Dt:	03/09/2010	Application #:	11468958	Filing Dt:	08/31/2006
Publication #:	US20080054357	Pub Dt:	03/06/2008
Title:	SEMICONDUCTOR STRUCTURE WITH ENHANCED PERFORMANCE USING A SIMPLIFIED DUAL STRESS LINER CONFIGURATION

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Patent #:	7403073	Issue Dt:	07/22/2008	Application #:	11469423	Filing Dt:	08/31/2006
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Title:	TUNABLE SEMICONDUCTOR DIODES

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100

Patent #:	NONE	Issue Dt:		Application #:	11472726	Filing Dt:	06/22/2006
Publication #:	US20070296064	Pub Dt:	12/27/2007
Title:	Electronic structures utilizing etch resistant boron and phosphorus materials and methods to form same

Assignor

INTERNATIONAL BUSINESS MACHINES CORPORATION

Exec Dt:

06/29/2015

Assignee

GLOBALFOUNDRIES U.S. 2 LLC

2070 ROUTE 52

HOPEWELL JUNCTION, NEW YORK 12533

Correspondence name and address
	HESLIN ROTHENBERG FARLEY & MESITI P.C.
	5 COLUMBIA CIRCLE
	ALBANY, NY 12203

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