|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
09869091
|
Filing Dt:
|
10/23/2001
|
Title:
|
METHOD OF TRANSMITTING INFORMATION THROUGH DATA SWITCHING APPARATUS AND APPARATUS THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09870088
|
Filing Dt:
|
05/30/2001
|
Title:
|
TECHNIQUE FOR LOCALLY REDUCING EFFECTS ON AN ANALOG SIGNAL DUE TO CHANGES ON A REFERENCE BUS IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09870850
|
Filing Dt:
|
05/30/2001
|
Publication #:
|
|
Pub Dt:
|
10/11/2001
| | | | |
Title:
|
SEMICONDUCTOR PROCESSING METHODS, SEMICONDUCTOR CIRCUITRY, AND GATE STACKS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09870982
|
Filing Dt:
|
05/30/2001
|
Title:
|
METHOD FOR GENERATING MEMORY ADDRESSES FOR ACCESSING MEMORY-CELL ARRAYS IN MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2002
|
Application #:
|
09871062
|
Filing Dt:
|
05/31/2001
|
Publication #:
|
|
Pub Dt:
|
09/20/2001
| | | | |
Title:
|
INTEGRATED CIRCUIT INDUCTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2003
|
Application #:
|
09871234
|
Filing Dt:
|
05/30/2001
|
Publication #:
|
|
Pub Dt:
|
02/07/2002
| | | | |
Title:
|
CIRCUITAL STRUCTURE FOR READING DATA IN A NON-VOLATILE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2003
|
Application #:
|
09871235
|
Filing Dt:
|
05/30/2001
|
Publication #:
|
|
Pub Dt:
|
02/07/2002
| | | | |
Title:
|
CIRCUITAL STRUCTURE FOR PROGRAMMING DATA IN A NON-VOLATILE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2003
|
Application #:
|
09871454
|
Filing Dt:
|
05/31/2001
|
Publication #:
|
|
Pub Dt:
|
09/27/2001
| | | | |
Title:
|
INTEGRATED CIRCUIT INDUCTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2002
|
Application #:
|
09871684
|
Filing Dt:
|
06/04/2001
|
Publication #:
|
|
Pub Dt:
|
10/11/2001
| | | | |
Title:
|
METHOD FOR REPAIRING MOSI ATTENUATED PHASE SHIFT MASKS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09872221
|
Filing Dt:
|
05/31/2001
|
Publication #:
|
|
Pub Dt:
|
10/04/2001
| | | | |
Title:
|
APPARATUS AND METHODS OF PACKAGING AND TESTING DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2002
|
Application #:
|
09872804
|
Filing Dt:
|
06/01/2001
|
Publication #:
|
|
Pub Dt:
|
11/29/2001
| | | | |
Title:
|
VOLTAGE INDEPENDENT FUSE CIRCUIT AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09873463
|
Filing Dt:
|
06/04/2001
|
Publication #:
|
|
Pub Dt:
|
10/04/2001
| | | | |
Title:
|
MULTIPLEXED DATA TRANSFER ARRANGEMENT INCLUDING A MULTI-PHASE SIGNAL GENERATOR FOR LATENCY CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
09873701
|
Filing Dt:
|
06/04/2001
|
Publication #:
|
|
Pub Dt:
|
11/29/2001
| | | | |
Title:
|
METHOD AND STRUCTURE FOR TEXTURED SURFACES IN FLOATING GATE TUNNELING OXIDE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09873823
|
Filing Dt:
|
06/04/2001
|
Publication #:
|
|
Pub Dt:
|
10/11/2001
| | | | |
Title:
|
DEVICE AND METHOD FOR SUPPLYING CURRENT TO A SEMICONDUCTOR MEMORY TO SUPPORT A BOOSTED VOLTAGE WITHIN THE MEMORY DURING TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2003
|
Application #:
|
09874011
|
Filing Dt:
|
06/06/2001
|
Publication #:
|
|
Pub Dt:
|
12/12/2002
| | | | |
Title:
|
THERMALLY ENHANCED HIGH DENSITY SEMICONDUCTOR PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
09874044
|
Filing Dt:
|
06/06/2001
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
Title:
|
METHOD AND CIRCUIT FOR NORMALIZATION OF FLOATING POINT SIGNIFICANTS IN A SIMD ARRAY MPP
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
09874307
|
Filing Dt:
|
06/06/2001
|
Publication #:
|
|
Pub Dt:
|
12/19/2002
| | | | |
Title:
|
METHOD AND CIRCUIT FOR ALIGNMENT OF FLOATING POINT SIGNIFICANTS IN A SIMD ARRAY MPP
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2005
|
Application #:
|
09874500
|
Filing Dt:
|
06/05/2001
|
Publication #:
|
|
Pub Dt:
|
01/31/2002
| | | | |
Title:
|
SWITCHING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
09874666
|
Filing Dt:
|
06/05/2001
|
Publication #:
|
|
Pub Dt:
|
02/14/2002
| | | | |
Title:
|
CONTROLLED COLLAPSE CHIP CONNECTION (C4) INTEGRATED CIRCUIT PACKAGE WHICH HAS TWO DISSIMILAR UNDERFILL MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2003
|
Application #:
|
09874671
|
Filing Dt:
|
06/05/2001
|
Publication #:
|
|
Pub Dt:
|
10/17/2002
| | | | |
Title:
|
APPARATUS FOR PACKAGE REDUCTION IN STACKED CHIP AND BOARD ASSEMBLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09875181
|
Filing Dt:
|
06/07/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
Column redundancy for prefetch
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2006
|
Application #:
|
09875375
|
Filing Dt:
|
06/05/2001
|
Publication #:
|
|
Pub Dt:
|
12/05/2002
| | | | |
Title:
|
MULTI-MODAL MOTION ESTIMATION FOR VIDEO SEQUENCES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
09875421
|
Filing Dt:
|
06/05/2001
|
Publication #:
|
|
Pub Dt:
|
12/05/2002
| | | | |
Title:
|
SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS AND LOCAL INTERCONNECTS AND METHODS FOR MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2004
|
Application #:
|
09876095
|
Filing Dt:
|
06/08/2001
|
Publication #:
|
|
Pub Dt:
|
12/12/2002
| | | | |
Title:
|
SENSE AMPLIFIER AND ARCHITECTURE FOR OPEN DIGIT ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09876674
|
Filing Dt:
|
06/07/2001
|
Publication #:
|
|
Pub Dt:
|
11/22/2001
| | | | |
Title:
|
FLASH MEMORY CELL FOR HIGH EFFICIENCY PROGRAMMING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
09876848
|
Filing Dt:
|
06/05/2001
|
Publication #:
|
|
Pub Dt:
|
10/03/2002
| | | | |
Title:
|
ROW DRIVER CIRCUIT FOR A SENSOR INCLUDING A SHARED ROW-RESET BUS AND A CHARGE PUMP BOOSTING CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2003
|
Application #:
|
09877280
|
Filing Dt:
|
06/08/2001
|
Publication #:
|
|
Pub Dt:
|
10/04/2001
| | | | |
Title:
|
PROCESS FOR FORMING LOW RESISTANCE METAL SILICIDE LOCAL INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2003
|
Application #:
|
09877897
|
Filing Dt:
|
06/08/2001
|
Publication #:
|
|
Pub Dt:
|
10/04/2001
| | | | |
Title:
|
METHOD AND APPARATUS FOR TESTING THE TIMING OF INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2003
|
Application #:
|
09878062
|
Filing Dt:
|
06/07/2001
|
Publication #:
|
|
Pub Dt:
|
12/12/2002
| | | | |
Title:
|
METHOD AND APPARATUS FOR UTILIZING STATIC QUEUES IN PROCESSOR STAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
09878302
|
Filing Dt:
|
06/11/2001
|
Publication #:
|
|
Pub Dt:
|
12/12/2002
| | | | |
Title:
|
ALTERNATIVE METHOD USED TO PACKAGE MULTIMEDIA CARD BY TRANSFER MOLDING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09878432
|
Filing Dt:
|
06/12/2001
|
Title:
|
CLOCKED PASS TRANSISTOR AND COMPLEMENTARY PASS TRANSISTOR LOGIC CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09878576
|
Filing Dt:
|
06/11/2001
|
Publication #:
|
|
Pub Dt:
|
10/04/2001
| | | | |
Title:
|
DEVICE AND METHOD FOR LIMITING THE EXTENT TO WHICH CIRCUITS IN INTEGRATED CIRCUIT DICE ELECTRICALLY LOAD BOND PADS AND OTHER CIRCUIT NODES IN THE DICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
09878616
|
Filing Dt:
|
06/12/2001
|
Publication #:
|
|
Pub Dt:
|
10/11/2001
| | | | |
Title:
|
APPARATUS FOR EXTENDING THE AVAILABLE NUMBER OF CONFIGURATION REGISTERS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
09879231
|
Filing Dt:
|
06/11/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
CAPACITOR CONSTRUCTIONS HAVING A CONDUCTIVE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2002
|
Application #:
|
09879244
|
Filing Dt:
|
06/11/2001
|
Publication #:
|
|
Pub Dt:
|
10/25/2001
| | | | |
Title:
|
SEMICONDUCTOR WIREBOND MACHINE LEADFRAME THERMAL MAP SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2002
|
Application #:
|
09879453
|
Filing Dt:
|
06/12/2001
|
Publication #:
|
|
Pub Dt:
|
11/15/2001
| | | | |
Title:
|
Memory using insulator traps
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2004
|
Application #:
|
09879602
|
Filing Dt:
|
06/12/2001
|
Publication #:
|
|
Pub Dt:
|
10/18/2001
| | | | |
Title:
|
METHOD FOR READING A VERTICAL GAIN CELL AND ARRAY FOR A DYNAMIC RANDOM ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
09879741
|
Filing Dt:
|
06/11/2001
|
Publication #:
|
|
Pub Dt:
|
10/04/2001
| | | | |
Title:
|
SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY AND SEMICONDUCTOR PROCESSING METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2003
|
Application #:
|
09879742
|
Filing Dt:
|
06/11/2001
|
Publication #:
|
|
Pub Dt:
|
11/01/2001
| | | | |
Title:
|
METHODS FOR FORMING WORDLINES, TRANSISTOR GATES, AND CONDUCTIVE INTERCONNECTS, AND WORDLINE, TRANSISTOR GATE, AND CONDUCTIVE INTERCONNECT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2003
|
Application #:
|
09880617
|
Filing Dt:
|
06/13/2001
|
Title:
|
INPUT BUFFER WITH AUTOMATIC SWITCHING POINT ADJUSTMENT CIRCUITRY, AND SYNCHRONOUS DRAM DEVICE INCLUDING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
09881299
|
Filing Dt:
|
06/13/2001
|
Publication #:
|
|
Pub Dt:
|
10/18/2001
| | | | |
Title:
|
CONDUCTIVE CONNECTION FORMING METHODS, OXIDATION REDUCING METHODS, AND INTEGRATED CIRCUITS FORMED THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09881308
|
Filing Dt:
|
06/13/2001
|
Title:
|
SEMICONDUCTOR STRUCTURES, METHODS OF IMPLANTING DOPANTS INTO SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING CMOS CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
09881407
|
Filing Dt:
|
06/13/2001
|
Publication #:
|
|
Pub Dt:
|
12/19/2002
| | | | |
Title:
|
METHODS OF FORMING TRANSISTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
09881408
|
Filing Dt:
|
06/13/2001
|
Publication #:
|
|
Pub Dt:
|
12/19/2002
| | | | |
Title:
|
DIELECTRIC LAYER FORMING METHOD AND DEVICES FORMED THEREWITH
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
09881472
|
Filing Dt:
|
06/14/2001
|
Publication #:
|
|
Pub Dt:
|
12/19/2002
| | | | |
Title:
|
SEMICONDUCTOR MEMORY WITH WORDLINE TIMING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
09881792
|
Filing Dt:
|
06/15/2001
|
Publication #:
|
|
Pub Dt:
|
10/18/2001
| | | | |
Title:
|
HIGH DENSITY FLIP CHIP MEMORY ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2003
|
Application #:
|
09882469
|
Filing Dt:
|
06/14/2001
|
Title:
|
SEMICONDUCTOR DIE WITH INTEGRAL DECOUPLING CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09882535
|
Filing Dt:
|
06/14/2001
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
Title:
|
BIASING CIRCUIT FOR MULTI-LEVEL MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2002
|
Application #:
|
09882920
|
Filing Dt:
|
06/15/2001
|
Publication #:
|
|
Pub Dt:
|
12/20/2001
| | | | |
Title:
|
DYNAMIC FLASH MEMORY CELLS WITH ULTRA THIN TUNNEL OXIDES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2002
|
Application #:
|
09883609
|
Filing Dt:
|
06/18/2001
|
Publication #:
|
|
Pub Dt:
|
10/25/2001
| | | | |
Title:
|
BALL ARRAY LAYOUT IN CHIP ASSEMBLY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
09883795
|
Filing Dt:
|
06/18/2001
|
Publication #:
|
|
Pub Dt:
|
10/25/2001
| | | | |
Title:
|
METHOD OF FORMING A DEVICE WITH A GALLIUM NITRIDE OR GALLIUM ALUMINUM NITRIDE GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09884081
|
Filing Dt:
|
06/20/2001
|
Title:
|
DIFFERENTIAL INPUT BUFFER BIAS PULSER CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
09884174
|
Filing Dt:
|
06/19/2001
|
Publication #:
|
|
Pub Dt:
|
12/19/2002
| | | | |
Title:
|
APPARATUS AND METHOD FOR CLOCK DOMAIN CROSSING WITH INTEGRATED DECODE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09884234
|
Filing Dt:
|
06/19/2001
|
Publication #:
|
|
Pub Dt:
|
11/15/2001
| | | | |
Title:
|
APPARATUS AND METHOD FOR PROGRAMMING VOLTAGE PROTECTION IN A NON-VOLATILE MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2004
|
Application #:
|
09884290
|
Filing Dt:
|
06/18/2001
|
Publication #:
|
|
Pub Dt:
|
10/25/2001
| | | | |
Title:
|
METHODS OF PATTERNING RADIATION, METHODS OF FORMING RADIATION-PATTERNING TOOLS, AND RADIATION-PATTERNING TOOLS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
09884293
|
Filing Dt:
|
06/18/2001
|
Publication #:
|
|
Pub Dt:
|
10/18/2001
| | | | |
Title:
|
METHODS OF FORMING INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2003
|
Application #:
|
09884630
|
Filing Dt:
|
06/18/2001
|
Publication #:
|
|
Pub Dt:
|
10/11/2001
| | | | |
Title:
|
METHOD FOR REDUCING CAPACITIVE COUPLING BETWEEN CONDUCTIVE LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09884785
|
Filing Dt:
|
06/19/2001
|
Publication #:
|
|
Pub Dt:
|
11/22/2001
| | | | |
Title:
|
APPARATUS AND METHOD FOR PROGRAMMING VOLTAGE PROTECTION IN A NON-VOLATILE MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2002
|
Application #:
|
09884793
|
Filing Dt:
|
06/19/2001
|
Publication #:
|
|
Pub Dt:
|
11/29/2001
| | | | |
Title:
|
APPARATUS AND METHOD FOR PROGRAMMING VOLTAGE PROTECTION IN A NON-VOLATILE MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
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06/24/2003
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Application #:
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09884950
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Filing Dt:
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06/19/2001
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Publication #:
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Pub Dt:
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11/01/2001
| | | | |
Title:
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SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY MEMORY DEVICES, METHODS OF FORMING CAPACITOR CONTAINERS, METHODS OF MAKING ELECTRICAL CONNECTION TO CIRCUIT NODES AND RELATED INTEGRATED CIRCUITRY
|
|
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Patent #:
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|
Issue Dt:
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04/12/2005
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Application #:
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09885393
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Filing Dt:
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06/19/2001
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Publication #:
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Pub Dt:
|
10/25/2001
| | | | |
Title:
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SEMICONDUCTOR PROCESSING METHODS
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Patent #:
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Issue Dt:
|
04/01/2003
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Application #:
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09885615
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Filing Dt:
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06/20/2001
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Publication #:
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Pub Dt:
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12/26/2002
| | | | |
Title:
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METHOD AND APPARATUS FOR CONDUCTING HEAT IN A FLIP-CHIP ASSEMBLY
|
|
|
Patent #:
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|
Issue Dt:
|
10/07/2003
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Application #:
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09885624
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Filing Dt:
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06/20/2001
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Publication #:
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Pub Dt:
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02/07/2002
| | | | |
Title:
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INSULATED ELECTRODE STRUCTURES FOR A DISPLAY DEVICE
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|
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Patent #:
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Issue Dt:
|
09/24/2002
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Application #:
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09886332
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Filing Dt:
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06/21/2001
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Publication #:
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Pub Dt:
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11/22/2001
| | | | |
Title:
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DIRECT WRITING OF LOW CARBON CONDUCTIVE MATERIAL
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|
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Patent #:
|
|
Issue Dt:
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04/09/2002
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Application #:
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09886543
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Filing Dt:
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06/21/2001
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Publication #:
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Pub Dt:
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02/28/2002
| | | | |
Title:
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Methods for alternate bitline stress testing
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|
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Patent #:
|
|
Issue Dt:
|
08/27/2002
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Application #:
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09886762
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Filing Dt:
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06/21/2001
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Publication #:
|
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Pub Dt:
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10/25/2001
| | | | |
Title:
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DEVICE AND METHOD FOR REPAIRING A MEMORY ARRAY BY STORING EACH BIT IN MULTIPLE MEMORY CELLS IN THE ARRAY
|
|
|
Patent #:
|
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Issue Dt:
|
02/25/2003
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Application #:
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09886782
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Filing Dt:
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06/21/2001
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Publication #:
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Pub Dt:
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11/08/2001
| | | | |
Title:
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USE OF RESIDUAL ORGANIC COMPOUNDS TO FACILITATE GATE BREAK ON A CARRIER SUBSTRATE FOR A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2003
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Application #:
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09887085
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Filing Dt:
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06/21/2001
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Publication #:
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Pub Dt:
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11/01/2001
| | | | |
Title:
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CONDUCTIVE LINES, COAXIAL LINES, INTEGRATED CIRCUITRY, AND METHODS OF FORMING CONDUCTIVE LINES, COAXIAL LINES, AND INTEGRATED CIRCUITRY
|
|
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Patent #:
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|
Issue Dt:
|
09/24/2002
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Application #:
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09887214
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Filing Dt:
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06/22/2001
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Publication #:
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Pub Dt:
|
11/01/2001
| | | | |
Title:
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METHOD OF FORMING A MASK
|
|
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Patent #:
|
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Issue Dt:
|
11/05/2002
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Application #:
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09887603
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Filing Dt:
|
06/22/2001
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Publication #:
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Pub Dt:
|
11/01/2001
| | | | |
Title:
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MASK FOR PRODUCING RECTANGULAR OPENINGS IN A SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2003
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Application #:
|
09888050
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Filing Dt:
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06/22/2001
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Publication #:
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Pub Dt:
|
01/31/2002
| | | | |
Title:
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METHOD FOR POST CHEMICAL-MECHANICAL PLANARIZATION CLEANING OF SEMICONDUCTOR WAFERS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
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Application #:
|
09888084
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Filing Dt:
|
06/21/2001
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Publication #:
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Pub Dt:
|
02/28/2002
| | | | |
Title:
|
METHODS AND APPARATUS FOR ELECTRICAL, MECHANICAL AND/OR CHEMICAL REMOVAL OF CONDUCTIVE MATERIAL FROM A MICROELECTRONIC SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2003
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Application #:
|
09888252
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Filing Dt:
|
06/22/2001
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Publication #:
|
|
Pub Dt:
|
01/02/2003
| | | | |
Title:
|
CHARGING A CAPACITANCE OF A MEMORY CELL AND CHARGER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
09888674
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Filing Dt:
|
06/25/2001
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Publication #:
|
|
Pub Dt:
|
01/02/2003
| | | | |
Title:
|
METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING AN OPENING IN A SOLDER MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2002
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Application #:
|
09888725
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Filing Dt:
|
06/25/2001
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Publication #:
|
|
Pub Dt:
|
01/03/2002
| | | | |
Title:
|
METHOD TO FIND A VALUE WITHIN A RANGE USING WEIGHTED SUBRANGES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2003
|
Application #:
|
09888845
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Filing Dt:
|
06/25/2001
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Publication #:
|
|
Pub Dt:
|
11/22/2001
| | | | |
Title:
|
REMOVAL OF COPPER OXIDES FROM INTEGRATED INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2003
|
Application #:
|
09888885
|
Filing Dt:
|
06/25/2001
|
Publication #:
|
|
Pub Dt:
|
11/08/2001
| | | | |
Title:
|
INTERDIGITATED LEADS-OVER-CHIP LEAD FRAME, AND DEVICE, FOR SUPPORTING AN INTEGRATED CIRCUIT DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09891438
|
Filing Dt:
|
06/25/2001
|
Publication #:
|
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Pub Dt:
|
11/01/2001
| | | | |
Title:
|
PROCESS FOR THE MANUFACTURE OF INTEGRATED DEVICES WITH GATE OXIDE PROTECTION FROM MANUFACTURING PROCESS DAMAGE, AND PROTECTION STRUCTURE THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2008
|
Application #:
|
09891523
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Filing Dt:
|
06/27/2001
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Publication #:
|
|
Pub Dt:
|
12/12/2002
| | | | |
Title:
|
PARALLEL CACHELETS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09891567
|
Filing Dt:
|
06/25/2001
|
Publication #:
|
|
Pub Dt:
|
11/01/2001
| | | | |
Title:
|
MEMORY DEVICE BALANCED SWITCHING CIRCUIT AND METHOD OF CONTROLLING AN ARRAY OF TRANSFER GATES FOR FAST SWITCHING TIMES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
09891570
|
Filing Dt:
|
06/25/2001
|
Publication #:
|
|
Pub Dt:
|
11/22/2001
| | | | |
Title:
|
SEMICONDUCTOR PROCESSING METHODS OF FORMING AND UTILIZING ANTIREFLECTIVE MATERIAL LAYERS, AND METHODS OF FORMING TRANSISTOR GATE STACKS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2003
|
Application #:
|
09891575
|
Filing Dt:
|
06/25/2001
|
Publication #:
|
|
Pub Dt:
|
11/01/2001
| | | | |
Title:
|
SEMICONDUCTOR PROCESSING METHODS AND INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
|
Application #:
|
09891623
|
Filing Dt:
|
06/25/2001
|
Publication #:
|
|
Pub Dt:
|
06/13/2002
| | | | |
Title:
|
RISER CARD ASSEMBLY AND METHOD FOR ITS INSTALLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2002
|
Application #:
|
09892099
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Filing Dt:
|
06/26/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
CLOCK GENERATION CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2002
|
Application #:
|
09892156
|
Filing Dt:
|
06/26/2001
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Title:
|
METHOD AND PROCESS OF CONTACT TO A HEAT SOFTENED SOLDER BALL ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2003
|
Application #:
|
09892921
|
Filing Dt:
|
06/26/2001
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
Title:
|
PACKAGING AND ASSEMBLY METHOD FOR OPTICAL COUPLING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2002
|
Application #:
|
09892956
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Filing Dt:
|
06/27/2001
|
Publication #:
|
|
Pub Dt:
|
05/09/2002
| | | | |
Title:
|
STACKED LOCAL INTERCONNECT STRUCTURE AND METHOD OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
09893616
|
Filing Dt:
|
06/29/2001
|
Publication #:
|
|
Pub Dt:
|
06/27/2002
| | | | |
Title:
|
Data transmission circuit for memory subsystem, has switching circuit that selectively connects or disconnects two data bus segments to respectively enable data transmission or I/O circuit connection
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
09893779
|
Filing Dt:
|
06/27/2001
|
Publication #:
|
|
Pub Dt:
|
01/02/2003
| | | | |
Title:
|
ON-DIE CACHE MEMORY WITH REPEATERS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2008
|
Application #:
|
09893868
|
Filing Dt:
|
06/29/2001
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
Title:
|
CASCADED DOMINO FOUR-TO-TWO REDUCER CIRCUIT AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2003
|
Application #:
|
09894070
|
Filing Dt:
|
06/28/2001
|
Publication #:
|
|
Pub Dt:
|
11/29/2001
| | | | |
Title:
|
BARRIER IN GATE STACK FOR IMPROVED GATE DIELECTRIC INTEGRITY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
09894136
|
Filing Dt:
|
06/29/2001
|
Publication #:
|
|
Pub Dt:
|
01/02/2003
| | | | |
Title:
|
SYSTEM FOR SHARING CHANNELS BY INTERLEAVING FLITS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
09894194
|
Filing Dt:
|
06/27/2001
|
Publication #:
|
|
Pub Dt:
|
11/08/2001
| | | | |
Title:
|
METHODS OF PHOTO-PROCESSING PHOTORESIST
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2005
|
Application #:
|
09894460
|
Filing Dt:
|
06/28/2001
|
Publication #:
|
|
Pub Dt:
|
01/02/2003
| | | | |
Title:
|
ETCHING OF HIGH ASPECT RATIO STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2003
|
Application #:
|
09894513
|
Filing Dt:
|
06/27/2001
|
Publication #:
|
|
Pub Dt:
|
01/02/2003
| | | | |
Title:
|
CACHE ARCHITECTURE FOR PIPELINED OPERATION WITH ON-DIE PROCESSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
09894638
|
Filing Dt:
|
06/27/2001
|
Publication #:
|
|
Pub Dt:
|
01/02/2003
| | | | |
Title:
|
CACHE ARCHITECTURE WITH REDUNDANT SUB ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2003
|
Application #:
|
09894755
|
Filing Dt:
|
06/28/2001
|
Publication #:
|
|
Pub Dt:
|
01/02/2003
| | | | |
Title:
|
SUCCESSIVE TEMPLATE GENERATION USING MINIMAL RANDOM ACCESS MEMORY BANDWIDTH
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09894935
|
Filing Dt:
|
06/28/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
METHOD AND STENCIL FOR EXTRUDING MATERIAL ON A SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2004
|
Application #:
|
09895662
|
Filing Dt:
|
06/29/2001
|
Publication #:
|
|
Pub Dt:
|
03/14/2002
| | | | |
Title:
|
METHOD OF PRESSURE CURING FOR REDUCING VOIDS IN A DIE ATTACH BONDLINE AND APPLICATIONS THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
09895738
|
Filing Dt:
|
06/29/2001
|
Publication #:
|
|
Pub Dt:
|
01/02/2003
| | | | |
Title:
|
METHOD AND APPARATUS TO IMPROVE THE PROTECTION OF INFORMATION PRESENTED BY A COMPUTER
|
|