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Reel/Frame:038376/0001   Pages: 271
Recorded: 04/07/2016
Attorney Dkt #:F162302
Conveyance: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL
Total properties: 1469
Page 5 of 15
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1
Patent #:
Issue Dt:
05/23/2006
Application #:
11119675
Filing Dt:
05/02/2005
Publication #:
Pub Dt:
09/01/2005
Title:
HIGH PRECISION DIGITAL-TO-ANALOG CONVERTER WITH OPTIMIZED POWER CONSUMPTION
2
Patent #:
Issue Dt:
03/25/2008
Application #:
11120937
Filing Dt:
05/03/2005
Publication #:
Pub Dt:
09/08/2005
Title:
METHOD OF MAKING NONVOLATILE TRANSISTOR PAIRS WITH SHARED CONTROL GATE
3
Patent #:
Issue Dt:
12/22/2009
Application #:
11121875
Filing Dt:
05/04/2005
Publication #:
Pub Dt:
11/09/2006
Title:
LPC CONFIGURATION SHARING METHOD
4
Patent #:
Issue Dt:
08/26/2008
Application #:
11121990
Filing Dt:
05/05/2005
Publication #:
Pub Dt:
11/10/2005
Title:
METHOD FOR FORMING A PHOTONIC BAND-GAP STRUCTURE AND A DEVICE FABRICATED IN ACCORDANCE WITH SUCH A METHOD
5
Patent #:
Issue Dt:
10/23/2007
Application #:
11122009
Filing Dt:
05/05/2005
Publication #:
Pub Dt:
11/10/2005
Title:
METHOD FOR CONSTRUCTING PASSIVE DEVICES ON A SUBSTRATE AND A DEVICE FABRICATED IN ACCORDANCE WITH SUCH A METHOD
6
Patent #:
Issue Dt:
12/11/2007
Application #:
11122010
Filing Dt:
05/05/2005
Publication #:
Pub Dt:
11/10/2005
Title:
METHOD FOR PRODUCING A COPLANAR WAVEGUIDE SYSTEM ON A SUBSTRATE, AND A COMPONENT FOR THE TRANSMISSION OF ELECTROMAGNETIC WAVES FABRICATED IN ACCORDANCE WITH SUCH A METHOD
7
Patent #:
Issue Dt:
04/27/2010
Application #:
11122038
Filing Dt:
05/05/2005
Publication #:
Pub Dt:
11/10/2005
Title:
METHOD FOR PRODUCING A CONDUCTOR PATH ON A SUBSTRATE, AND A COMPONENT HAVING A CONDUCTOR PATH FABRICATED IN ACCORDANCE WITH SUCH A METHOD
8
Patent #:
Issue Dt:
05/30/2006
Application #:
11122057
Filing Dt:
05/05/2005
Publication #:
Pub Dt:
11/10/2005
Title:
METHOD FOR PRODUCING A SPIRAL INDUCTANCE ON A SUBSTRATE, AND A DEVICE FABRICATED ACCORDING TO SUCH A METHOD
9
Patent #:
NONE
Issue Dt:
Application #:
11123305
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
11/09/2006
Title:
Transient pulse, substrate-triggered biCMOS rail clamp for ESD abatement
10
Patent #:
Issue Dt:
09/30/2008
Application #:
11123544
Filing Dt:
05/05/2005
Publication #:
Pub Dt:
04/20/2006
Title:
METHOD AND SYSTEM FOR PROVIDING SENSING CIRCUITRY IN A MULTI-BANK MEMORY DEVICE
11
Patent #:
Issue Dt:
02/26/2008
Application #:
11123673
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
11/09/2006
Title:
ULTRASCALABLE VERTICAL MOS TRANSISTOR WITH PLANAR CONTACTS
12
Patent #:
Issue Dt:
07/22/2008
Application #:
11123682
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
04/20/2006
Title:
METHOD AND SYSTEM FOR MANAGING ADDRESS BITS DURING BUFFERED PROGRAM OPERATIONS IN A MEMORY DEVICE
13
Patent #:
Issue Dt:
02/27/2007
Application #:
11123754
Filing Dt:
05/05/2005
Publication #:
Pub Dt:
06/01/2006
Title:
METHOD AND SYSTEM FOR REGULATING A PROGRAM VOLTAGE VALUE DURING MULTILEVEL MEMORY DEVICE PROGRAMMING
14
Patent #:
Issue Dt:
02/13/2007
Application #:
11123979
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
03/23/2006
Title:
COMPENSATED METHOD TO IMPLEMENT A HIGH VOLTAGE DISCHARGE PHASE AFTER ERASE PULSE IN A FLASH MEMORY DEVICE
15
Patent #:
Issue Dt:
02/13/2007
Application #:
11124871
Filing Dt:
05/09/2005
Publication #:
Pub Dt:
02/23/2006
Title:
METHOD AND APPARATUS FOR FAST POWER-ON OF THE BAND-GAP REFERENCE
16
Patent #:
Issue Dt:
09/11/2007
Application #:
11124939
Filing Dt:
05/09/2005
Publication #:
Pub Dt:
03/02/2006
Title:
SYSTEM AND METHOD FOR PRESERVING AN ERROR MARGIN FOR A NON-VOLATILE MEMORY
17
Patent #:
Issue Dt:
03/11/2008
Application #:
11126418
Filing Dt:
05/11/2005
Publication #:
Pub Dt:
09/29/2005
Title:
METHOD OF MAKING EEPROM TRANSISTOR PAIRS FOR BLOCK ALTERABLE MEMORY
18
Patent #:
Issue Dt:
02/19/2008
Application #:
11126441
Filing Dt:
05/11/2005
Publication #:
Pub Dt:
04/13/2006
Title:
COLUMN DECODING ARCHITECTURE FOR FLASH MEMORIES
19
Patent #:
Issue Dt:
11/27/2007
Application #:
11126473
Filing Dt:
05/11/2005
Publication #:
Pub Dt:
04/13/2006
Title:
SYSTEM AND METHOD FOR AVOIDING OFFSET IN AND REDUCING THE FOOTPRINT OF A NON-VOLATILE MEMORY
20
Patent #:
Issue Dt:
09/11/2007
Application #:
11128109
Filing Dt:
05/11/2005
Publication #:
Pub Dt:
10/05/2006
Title:
METHOD AND APPARATUS FOR REDUCING SYSTEM INACTIVITY DURING TIME DATA FLOAT DELAY AND EXTERNAL MEMORY WRITE
21
Patent #:
Issue Dt:
10/31/2006
Application #:
11128648
Filing Dt:
05/12/2005
Publication #:
Pub Dt:
04/20/2006
Title:
FLEXIBLE OTP SECTOR PROTECTION ARCHITECTURE FOR FLASH MEMORIES
22
Patent #:
Issue Dt:
03/18/2008
Application #:
11128939
Filing Dt:
05/12/2005
Publication #:
Pub Dt:
04/13/2006
Title:
METHOD AND SYSTEM FOR A PROGRAMMING APPROACH FOR A NONVOLATILE ELECTRONIC DEVICE
23
Patent #:
Issue Dt:
08/03/2010
Application #:
11128989
Filing Dt:
05/13/2005
Publication #:
Pub Dt:
11/16/2006
Title:
DISCRETE-TIME ANALOG, DIGITALLY PROGRAMMABLE FILTER AND METHOD
24
Patent #:
Issue Dt:
05/29/2007
Application #:
11130929
Filing Dt:
05/17/2005
Publication #:
Pub Dt:
09/07/2006
Title:
FAST READ PORT FOR REGISTER FILE
25
Patent #:
Issue Dt:
08/14/2007
Application #:
11136131
Filing Dt:
05/24/2005
Publication #:
Pub Dt:
11/30/2006
Title:
METHOD FOR CHANGING THRESHOLD VOLTAGE OF DEVICE IN RESIST ASHER
26
Patent #:
Issue Dt:
04/24/2007
Application #:
11136140
Filing Dt:
05/24/2005
Publication #:
Pub Dt:
11/30/2006
Title:
LOW-COST, LOW-VOLTAGE SINGLE-LAYER POLYCRYSTALLINE EEPROM MEMORY CELL INTEGRATION INTO BICMOS TECHNOLOGY
27
Patent #:
Issue Dt:
07/11/2006
Application #:
11137463
Filing Dt:
05/26/2005
Publication #:
Pub Dt:
12/08/2005
Title:
CIRCUIT FOR CURRENT MEASUREMENT AND CURRENT MONITORING
28
Patent #:
Issue Dt:
10/19/2010
Application #:
11140749
Filing Dt:
05/31/2005
Publication #:
Pub Dt:
12/21/2006
Title:
SYSTEM FOR INCREASING THE SPEED OF A SUM-OF-ABSOLUTE-DIFFERENCES OPERATION
29
Patent #:
Issue Dt:
07/10/2007
Application #:
11140750
Filing Dt:
05/31/2005
Publication #:
Pub Dt:
11/30/2006
Title:
EXTRACTED-INDEX ADDRESSING OF BYTE-ADDRESSABLE MEMORIES
30
Patent #:
Issue Dt:
09/06/2011
Application #:
11142920
Filing Dt:
06/01/2005
Publication #:
Pub Dt:
12/07/2006
Title:
APPARATUS AND METHOD FOR PERFORMING EFFICIENT MULTIPLY-ACCUMULATE OPERATIONS IN MICROPROCESSORS
31
Patent #:
Issue Dt:
11/27/2007
Application #:
11145457
Filing Dt:
06/02/2005
Publication #:
Pub Dt:
07/20/2006
Title:
METHOD AND SYSTEM FOR MANAGING A SUSPEND REQUEST IN A FLASH MEMORY
32
Patent #:
Issue Dt:
08/09/2011
Application #:
11145613
Filing Dt:
06/06/2005
Publication #:
Pub Dt:
01/04/2007
Title:
MICROPROCESSOR INSTRUCTION THAT ALLOWS SYSTEM ROUTINE CALLS AND RETURNS FROM ALL CONTEXTS
33
Patent #:
Issue Dt:
03/30/2010
Application #:
11146253
Filing Dt:
06/06/2005
Publication #:
Pub Dt:
12/07/2006
Title:
METHOD AND APPARATUS FOR FORMATTING NUMBERS IN MICROPROCESSORS
34
Patent #:
Issue Dt:
03/17/2009
Application #:
11147498
Filing Dt:
06/07/2005
Publication #:
Pub Dt:
12/07/2006
Title:
MECHANISM FOR PROVIDING PROGRAM BREAKPOINTS IN A MICROCONTROLLER WITH FLASH PROGRAM MEMORY
35
Patent #:
NONE
Issue Dt:
Application #:
11148049
Filing Dt:
06/07/2005
Publication #:
Pub Dt:
12/07/2006
Title:
Mechanism for storing and extracting trace information using internal memory in microcontrollers
36
Patent #:
Issue Dt:
08/14/2007
Application #:
11151332
Filing Dt:
06/13/2005
Publication #:
Pub Dt:
12/14/2006
Title:
MEMORY DATA ACCESS SCHEME
37
Patent #:
Issue Dt:
08/14/2007
Application #:
11160885
Filing Dt:
07/14/2005
Publication #:
Pub Dt:
11/03/2005
Title:
KEYBOARD WITH REDUCED KEYING AMBIGUITY
38
Patent #:
Issue Dt:
06/28/2011
Application #:
11163944
Filing Dt:
11/04/2005
Publication #:
Pub Dt:
02/23/2006
Title:
TOUCH SENSITIVE CONTROL PANEL
39
Patent #:
Issue Dt:
08/21/2007
Application #:
11168833
Filing Dt:
06/28/2005
Publication #:
Pub Dt:
12/28/2006
Title:
EFFICIENT CHARGE PUMP FOR A WIDE RANGE OF SUPPLY VOLTAGES
40
Patent #:
Issue Dt:
09/09/2008
Application #:
11176883
Filing Dt:
07/07/2005
Title:
SELF-ALIGNED NON-VOLATILE MEMORY CELL
41
Patent #:
Issue Dt:
12/29/2009
Application #:
11178713
Filing Dt:
07/11/2005
Publication #:
Pub Dt:
01/11/2007
Title:
HIGH-SPEED INTERFACE FOR HIGH-DENSITY FLASH WITH TWO LEVELS OF PIPELINED CACHE
42
Patent #:
Issue Dt:
02/20/2007
Application #:
11178965
Filing Dt:
07/11/2005
Publication #:
Pub Dt:
01/11/2007
Title:
MEMORY ARCHITECTURE WITH ENHANCED OVER-ERASE TOLERANT CONTROL GATE SCHEME
43
Patent #:
Issue Dt:
11/13/2007
Application #:
11179243
Filing Dt:
07/12/2005
Publication #:
Pub Dt:
01/18/2007
Title:
MEMORY ARCHITECTURE WITH ADVANCED MAIN-BITLINE PARTITIONING CIRCUITRY FOR ENHANCED ERASE/PROGRAM/VERIFY OPERATIONS
44
Patent #:
Issue Dt:
02/06/2007
Application #:
11181222
Filing Dt:
07/13/2005
Publication #:
Pub Dt:
11/10/2005
Title:
METHOD AND APPARATUS FOR CURRENT LIMITATION IN VOLTAGE REGULATORS WITH IMPROVED CIRCUITRY FOR PROVIDING A CONTROL VOLTAGE
45
Patent #:
Issue Dt:
06/14/2011
Application #:
11182335
Filing Dt:
07/14/2005
Publication #:
Pub Dt:
02/08/2007
Title:
METHOD AND SYSTEM FOR ENCRYPTION-BASED DESIGN OBFUSCATION FOR AN INTEGRATED CIRCUIT
46
Patent #:
Issue Dt:
01/08/2008
Application #:
11182374
Filing Dt:
07/15/2005
Publication #:
Pub Dt:
01/18/2007
Title:
NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS
47
Patent #:
Issue Dt:
10/24/2006
Application #:
11183346
Filing Dt:
07/18/2005
Publication #:
Pub Dt:
09/07/2006
Title:
MULTI-PHASE REALIGNED VOLTAGE-CONTROLLED OSCILLATOR AND PHASE-LOCKED LOOP INCORPORATING THE SAME
48
Patent #:
Issue Dt:
06/19/2007
Application #:
11188612
Filing Dt:
07/25/2005
Publication #:
Pub Dt:
01/25/2007
Title:
REDUCTION OF PROGRAMMING TIME IN ELECTRICALLY PROGRAMMABLE DEVICES
49
Patent #:
Issue Dt:
03/25/2008
Application #:
11188921
Filing Dt:
07/25/2005
Publication #:
Pub Dt:
01/25/2007
Title:
METHODS OF FORMING REDUCED ELECTRIC FIELD DMOS USING SELF-ALIGNED TRENCH ISOLATION
50
Patent #:
Issue Dt:
07/08/2008
Application #:
11192187
Filing Dt:
07/29/2005
Publication #:
Pub Dt:
02/02/2006
Title:
METHOD FOR INTEGRATION OF THREE BIPOLAR TRANSISTORS IN A SEMICONDUCTOR BODY, MULTILAYER COMPONENT, AND SEMICONDUCTOR ARRANGEMENT
51
Patent #:
Issue Dt:
10/16/2007
Application #:
11193924
Filing Dt:
07/28/2005
Publication #:
Pub Dt:
12/14/2006
Title:
SYSTEM AND METHOD FOR MATCHING RESISTANCE IN A NON-VOLATILE MEMORY
52
Patent #:
Issue Dt:
01/30/2007
Application #:
11195434
Filing Dt:
08/02/2005
Publication #:
Pub Dt:
12/01/2005
Title:
METHOD AND APPARATUS TO ELIMINATE GALVANIC CORROSION ON COPPER DOPED ALUMINUM BOND PADS ON INTEGRATED CIRCUITS
53
Patent #:
Issue Dt:
11/17/2009
Application #:
11196277
Filing Dt:
08/04/2005
Publication #:
Pub Dt:
02/09/2006
Title:
INTEGRATED CIRCUIT HAVING A PREDEFINED DIELECTRIC STRENGTH
54
Patent #:
Issue Dt:
12/01/2009
Application #:
11196415
Filing Dt:
08/04/2005
Publication #:
Pub Dt:
02/09/2006
Title:
VOLTAGE COMPARATOR UTILIZING VOLTAGE TO CURRENT CONVERSION
55
Patent #:
Issue Dt:
12/15/2009
Application #:
11197358
Filing Dt:
08/05/2005
Publication #:
Pub Dt:
02/09/2006
Title:
SEMICONDUCTOR STRUCTURE
56
Patent #:
Issue Dt:
05/26/2009
Application #:
11197442
Filing Dt:
08/05/2005
Publication #:
Pub Dt:
02/09/2006
Title:
CIRCUIT LAYOUT WITH ACTIVE COMPONENTS AND HIGH BREAKDOWN VOLTAGE
57
Patent #:
Issue Dt:
04/01/2008
Application #:
11198317
Filing Dt:
08/08/2005
Publication #:
Pub Dt:
02/16/2006
Title:
CASCODE, CASCODE CIRCUIT AND METHOD FOR VERTICAL INTEGRATION OF TWO BIPOLAR TRANSISTORS INTO A CASCODE ARRANGEMENT
58
Patent #:
Issue Dt:
02/20/2007
Application #:
11198469
Filing Dt:
08/05/2005
Publication #:
Pub Dt:
02/08/2007
Title:
METHOD OF SENSING AN EEPROM REFERENCE CELL
59
Patent #:
Issue Dt:
02/12/2008
Application #:
11203938
Filing Dt:
08/15/2005
Publication #:
Pub Dt:
11/16/2006
Title:
SENSE AMPLIFIER CIRCUIT FOR PARALLEL SENSING OF FOUR CURRENT LEVELS
60
Patent #:
Issue Dt:
12/29/2009
Application #:
11206474
Filing Dt:
08/17/2005
Publication #:
Pub Dt:
02/22/2007
Title:
METHOD AND APPARATUS FOR SYNCHRONIZING DATA BETWEEN DIFFERENT CLOCK DOMAINS IN A MEMORY CONTROLLER
61
Patent #:
Issue Dt:
06/24/2008
Application #:
11207082
Filing Dt:
08/17/2005
Publication #:
Pub Dt:
01/25/2007
Title:
METHOD AND APPARATUS FOR DETERMINING STUCK-AT FAULT LOCATIONS IN CELL CHAINS USING SCAN CHAINS
62
Patent #:
Issue Dt:
06/12/2007
Application #:
11217250
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
REGISTRATION MARK WITHIN AN OVERLAP OF DOPANT REGIONS
63
Patent #:
Issue Dt:
03/15/2011
Application #:
11221008
Filing Dt:
09/07/2005
Publication #:
Pub Dt:
12/07/2006
Title:
OUTPUT LEVEL VOLTAGE REGULATION
64
Patent #:
Issue Dt:
08/04/2009
Application #:
11230358
Filing Dt:
09/19/2005
Publication #:
Pub Dt:
11/09/2006
Title:
METHOD AND SYSTEM FOR PROGRAM PULSE GENERATION DURING PROGRAMMING OF NONVOLATILE ELECTRONIC DEVICES
65
Patent #:
Issue Dt:
01/29/2008
Application #:
11231890
Filing Dt:
09/22/2005
Publication #:
Pub Dt:
05/04/2006
Title:
PLUG CONNECTOR MODULES OF A PLUG CONNECTOR FOR SIMULTANEOUSLY CONNECTING A PLURALITY OF ELECTRICAL CONTACTS
66
Patent #:
Issue Dt:
11/03/2009
Application #:
11248633
Filing Dt:
10/11/2005
Publication #:
Pub Dt:
04/12/2007
Title:
ELECTRONIC DEVICE WITH DOPANT DIFFUSION BARRIER AND TUNABLE WORK FUNCTION AND METHODS OF MAKING SAME
67
Patent #:
Issue Dt:
06/26/2007
Application #:
11252180
Filing Dt:
10/17/2005
Publication #:
Pub Dt:
04/19/2007
Title:
ANTIFUSE PROGRAMMING, PROTECTION, AND SENSING DEVICE
68
Patent #:
Issue Dt:
07/22/2008
Application #:
11254387
Filing Dt:
10/20/2005
Publication #:
Pub Dt:
05/31/2007
Title:
ELECTROSTATIC DISCHARGE (ESD) PROTECTION STRUCTURE AND A CIRCUIT USING THE SAME
69
Patent #:
Issue Dt:
07/14/2009
Application #:
11254580
Filing Dt:
10/20/2005
Publication #:
Pub Dt:
04/26/2007
Title:
METHOD AND SYSTEM FOR INCORPORATING HIGH VOLTAGE DEVICES IN AN EEPROM
70
Patent #:
Issue Dt:
05/27/2008
Application #:
11260124
Filing Dt:
10/28/2005
Publication #:
Pub Dt:
05/04/2006
Title:
PLANAR MICROWAVE LINE WITH A DIRECTIONAL CHANGE
71
Patent #:
Issue Dt:
02/26/2008
Application #:
11261698
Filing Dt:
10/28/2005
Publication #:
Pub Dt:
05/03/2007
Title:
HIGH VOLTAGE TOLERANT PORT DRIVER
72
Patent #:
Issue Dt:
06/30/2009
Application #:
11265854
Filing Dt:
11/03/2005
Publication #:
Pub Dt:
05/03/2007
Title:
LOW VOLTAGE NON-VOLATILE MEMORY CELL WITH ELECTRICALLY TRANSPARENT CONTROL GATE
73
Patent #:
Issue Dt:
02/10/2009
Application #:
11266209
Filing Dt:
11/04/2005
Publication #:
Pub Dt:
05/11/2006
Title:
SEMICONDUCTOR ARTICLE AND METHOD FOR MANUFACTURING WITH REDUCED BASE RESISTANCE
74
Patent #:
Issue Dt:
10/13/2009
Application #:
11266210
Filing Dt:
11/04/2005
Publication #:
Pub Dt:
05/11/2006
Title:
SEMICONDUCTOR ARRAY AND METHOD FOR MANUFACTURING A SEMICONDUCTOR ARRAY
75
Patent #:
Issue Dt:
11/27/2007
Application #:
11266501
Filing Dt:
11/03/2005
Publication #:
Pub Dt:
05/03/2007
Title:
COMPACT COLUMN REDUNDANCY CAM ARCHITECTURE FOR CONCURRENT READ AND WRITE OPERATIONS IN MULTI-SEGMENT MEMORY ARRAYS
76
Patent #:
Issue Dt:
11/27/2007
Application #:
11266797
Filing Dt:
11/04/2005
Publication #:
Pub Dt:
05/17/2007
Title:
BANDGAP ENGINEERED MONO-CRYSTALLINE SILICON CAP LAYERS FOR SIGE HBT PERFORMANCE ENHANCEMENT
77
Patent #:
Issue Dt:
10/21/2008
Application #:
11267473
Filing Dt:
11/04/2005
Publication #:
Pub Dt:
05/10/2007
Title:
METHOD AND SYSTEM FOR CONTROLLED OXYGEN INCORPORATION IN COMPOUND SEMICONDUCTOR FILMS FOR DEVICE PERFORMANCE ENHANCEMENT
78
Patent #:
Issue Dt:
01/26/2010
Application #:
11267553
Filing Dt:
11/04/2005
Publication #:
Pub Dt:
05/10/2007
Title:
BANDGAP AND RECOMBINATION ENGINEERED EMITTER LAYERS FOR SIGE HBT PERFORMANCE OPTIMIZATION
79
Patent #:
Issue Dt:
09/10/2013
Application #:
11268008
Filing Dt:
11/07/2005
Publication #:
Pub Dt:
05/10/2007
Title:
ELASTIC SHARED RAM ARRAY INCLUDING CONTIGUOUS INSTRUCTION AND DATA PORTIONS DISTINCT FROM EACH OTHER
80
Patent #:
Issue Dt:
03/11/2008
Application #:
11271094
Filing Dt:
11/10/2005
Publication #:
Pub Dt:
05/10/2007
Title:
SELF-ALIGNED NANOMETER-LEVEL TRANSISTOR DEFINED WITHOUT LITHOGRAPHY
81
Patent #:
Issue Dt:
02/20/2007
Application #:
11272206
Filing Dt:
11/10/2005
Publication #:
Pub Dt:
11/09/2006
Title:
METHOD AND SYSTEM FOR CONFIGURING PARAMETERS FOR FLASH MEMORY
82
Patent #:
Issue Dt:
01/22/2008
Application #:
11273083
Filing Dt:
11/15/2005
Publication #:
Pub Dt:
05/18/2006
Title:
INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT ON A SEMICONDUCTOR CHIP
83
Patent #:
Issue Dt:
04/14/2009
Application #:
11278223
Filing Dt:
03/31/2006
Publication #:
Pub Dt:
11/15/2007
Title:
METHOD AND APPARATUS TO TEST THE POWER-ON-RESET TRIP POINT OF AN INTEGRATED CIRCUIT
84
Patent #:
Issue Dt:
10/26/2010
Application #:
11279402
Filing Dt:
04/12/2006
Publication #:
Pub Dt:
08/31/2006
Title:
CAPACITIVE KEYBOARD WITH NON-LOCKING REDUCED KEYING AMBIGUITY
85
Patent #:
Issue Dt:
08/03/2010
Application #:
11281542
Filing Dt:
11/18/2005
Publication #:
Pub Dt:
07/13/2006
Title:
METHOD AND DEVICE FOR DATA TRANSMISSION
86
Patent #:
Issue Dt:
12/05/2006
Application #:
11284779
Filing Dt:
11/21/2005
Title:
NEGATIVE VOLTAGE REGULATOR
87
Patent #:
Issue Dt:
10/09/2007
Application #:
11284780
Filing Dt:
11/21/2005
Publication #:
Pub Dt:
05/24/2007
Title:
CHARGE PUMP FOR INTERMEDIATE VOLTAGE
88
Patent #:
Issue Dt:
03/04/2008
Application #:
11285089
Filing Dt:
11/21/2005
Publication #:
Pub Dt:
05/24/2007
Title:
ARRAY SOURCE LINE (AVSS) CONTROLLED HIGH VOLTAGE REGULATION FOR PROGRAMMING FLASH OR EE ARRAY
89
Patent #:
Issue Dt:
03/18/2008
Application #:
11285106
Filing Dt:
11/23/2005
Publication #:
Pub Dt:
06/01/2006
Title:
DRIVER CIRCUIT WITH AUTOMATIC OFFSET COMPENSATION OF AN AMPLIFIER AND METHOD FOR OFFSET COMPENSATION OF AN AMPLIFIER OF A DRIVER CIRCUIT
90
Patent #:
Issue Dt:
10/06/2009
Application #:
11288509
Filing Dt:
11/28/2005
Publication #:
Pub Dt:
02/14/2008
Title:
MICROCONTROLLER BASED FLASH MEMORY DIGITAL CONTROLLER SYSTEM
91
Patent #:
Issue Dt:
08/11/2009
Application #:
11288753
Filing Dt:
11/28/2005
Publication #:
Pub Dt:
05/31/2007
Title:
COMMAND DECODER FOR MICROCONTROLLER BASED FLASH MEMORY DIGITAL CONTROLLER SYSTEM
92
Patent #:
Issue Dt:
12/11/2007
Application #:
11291498
Filing Dt:
11/30/2005
Publication #:
Pub Dt:
05/31/2007
Title:
METHOD AND APPARATUS FOR IMPLEMENTING WALKOUT OF DEVICE JUNCTIONS
93
Patent #:
Issue Dt:
03/31/2009
Application #:
11291606
Filing Dt:
11/30/2005
Publication #:
Pub Dt:
05/31/2007
Title:
CIRCUIT TO CONTROL VOLTAGE RAMP RATE
94
Patent #:
Issue Dt:
07/06/2010
Application #:
11298155
Filing Dt:
12/09/2005
Publication #:
Pub Dt:
06/14/2007
Title:
STACK UNDERFLOW DEBUG WITH STICKY BASE
95
Patent #:
Issue Dt:
09/06/2011
Application #:
11298697
Filing Dt:
12/12/2005
Publication #:
Pub Dt:
06/15/2006
Title:
METHOD FOR WIRELESS DATA TRANSMISSION
96
Patent #:
Issue Dt:
07/17/2007
Application #:
11301040
Filing Dt:
12/12/2005
Publication #:
Pub Dt:
06/14/2007
Title:
AUTOMATIC ADDRESS TRANSITION DETECTION (ATD) CONTROL FOR REDUCTION OF SENSE AMPLIFIER POWER CONSUMPTION
97
Patent #:
Issue Dt:
12/04/2007
Application #:
11301401
Filing Dt:
12/13/2005
Publication #:
Pub Dt:
07/26/2007
Title:
DOUBLE BYTE SELECT HIGH VOLTAGE LINE FOR EEPROM MEMORY BLOCK
98
Patent #:
Issue Dt:
11/10/2009
Application #:
11302228
Filing Dt:
12/14/2005
Publication #:
Pub Dt:
06/15/2006
Title:
POWER SUPPLY CIRCUIT FOR PRODUCING A REFERENCE CURRENT WITH A PRESCRIBABLE TEMPERATURE DEPENDENCE
99
Patent #:
Issue Dt:
12/25/2007
Application #:
11302954
Filing Dt:
12/14/2005
Publication #:
Pub Dt:
08/03/2006
Title:
POWER FAILURE DETECTION CIRCUIT WITH FAST DROP RESPONSE
100
Patent #:
Issue Dt:
11/13/2007
Application #:
11303368
Filing Dt:
12/16/2005
Publication #:
Pub Dt:
06/21/2007
Title:
USE OF RECOVERY TRANSISTORS DURING WRITE OPERATIONS TO PREVENT DISTURBANCE OF UNSELECTED CELLS
Assignor
1
Exec Dt:
04/04/2016
Assignee
1
1600 TECHNOLOGY DRIVE
SAN JOSE, CALIFORNIA 95110
Correspondence name and address
JOANNA MCCALL
1025 VERMONT AVE NW, SUITE 1130
NATIONAL CORPORATE RESEARCH, LTD
WASHINGTON, DC 20005

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