|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
12053946
|
Filing Dt:
|
03/24/2008
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
Title:
|
DESIGN STRUCTURE FOR TIME BASED DRIVER OUTPUT TRANSITION (SLEW) RATE COMPENSATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2011
|
Application #:
|
12053958
|
Filing Dt:
|
03/24/2008
|
Publication #:
|
|
Pub Dt:
|
10/02/2008
| | | | |
Title:
|
STRUCTURE FOR INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
|
Application #:
|
12053969
|
Filing Dt:
|
03/24/2008
|
Publication #:
|
|
Pub Dt:
|
09/24/2009
| | | | |
Title:
|
METHOD AND STRUCTURE OF INTEGRATED RHODIUM CONTACTS WITH COPPER INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
12054022
|
Filing Dt:
|
03/24/2008
|
Publication #:
|
|
Pub Dt:
|
09/24/2009
| | | | |
Title:
|
BOOTSTRAP DEVICE AND METHODS THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
12054572
|
Filing Dt:
|
03/25/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
METHOD AND APPARATUS FOR OPTIMIZING AN OPTICAL PROXIMITY CORRECTION MODEL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2011
|
Application #:
|
12054580
|
Filing Dt:
|
03/25/2008
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
CONTROLLING POWER CHANGE FOR A SEMICONDUCTOR MODULE TO PRESERVE THERMAL INTERFACE THEREIN
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
12054713
|
Filing Dt:
|
03/25/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
UNDERBUMP METALLURGY FOR ENHANCED ELECTROMIGRATION RESISTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12054835
|
Filing Dt:
|
03/25/2008
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2012
|
Application #:
|
12054886
|
Filing Dt:
|
03/25/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
SUPER LATTICE/QUANTUM WELL NANOWIRES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2012
|
Application #:
|
12055336
|
Filing Dt:
|
03/26/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
INDUCTOR HAVING OPENING ENCLOSED WITHIN CONDUCTIVE LINE AND RELATED METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12055509
|
Filing Dt:
|
03/26/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2012
|
Application #:
|
12055513
|
Filing Dt:
|
03/26/2008
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
AROMATIC VINYL ETHER BASED REVERSE-TONE STEP AND FLASH IMPRINT LITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12055600
|
Filing Dt:
|
03/26/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
12055622
|
Filing Dt:
|
03/26/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12055686
|
Filing Dt:
|
03/26/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2012
|
Application #:
|
12055888
|
Filing Dt:
|
03/26/2008
|
Publication #:
|
|
Pub Dt:
|
07/17/2008
| | | | |
Title:
|
METHODS AND APPARATUS FOR PROVIDING FLEXIBLE TIMING-DRIVEN ROUTING TREES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
12056047
|
Filing Dt:
|
03/26/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
APPARATUS FOR REAL-TIME CONTAMINATION, ENVIRONMENTAL, OR PHYSICAL MONITORING OF A PHOTOMASK
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2010
|
Application #:
|
12056305
|
Filing Dt:
|
03/27/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
CMOS IMAGE SENSOR WITH REDUCED DARK CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12056412
|
Filing Dt:
|
03/27/2008
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
METHOD FOR HIGH DENSITY DATA STORAGE AND IMAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
12056477
|
Filing Dt:
|
03/27/2008
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
HIGH DENSITY DATA STORAGE MEDIUM, METHOD AND DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
12056795
|
Filing Dt:
|
03/27/2008
|
Publication #:
|
|
Pub Dt:
|
07/17/2008
| | | | |
Title:
|
DESIGN STRUCTURE FOR SWITCHING SYSTEM FOR SIGNAL MONITORING AND SWITCH-BACK CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
12057443
|
Filing Dt:
|
03/28/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
STRAINED ULTRA-THIN SOI TRANSISTOR FORMED BY REPLACEMENT GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
|
Application #:
|
12057472
|
Filing Dt:
|
03/28/2008
|
Publication #:
|
|
Pub Dt:
|
03/26/2009
| | | | |
Title:
|
FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2011
|
Application #:
|
12057478
|
Filing Dt:
|
03/28/2008
|
Publication #:
|
|
Pub Dt:
|
03/26/2009
| | | | |
Title:
|
FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
12057565
|
Filing Dt:
|
03/28/2008
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
METHODS FOR FORMING SURFACE FEATURES USING SELF-ASSEMBLING MASKS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12057686
|
Filing Dt:
|
03/28/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR TRANSFORMING AN INPUT VOLTAGE TO OBTAIN LINEARITY BETWEEN INPUT AND OUTPUT FUNCTIONS AND SYSTEM AND METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
|
Application #:
|
12057693
|
Filing Dt:
|
03/28/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
SYSTEMS AND METHODS FOR A COMBINED MATRIX-VECTOR AND MATRIX TRANSPOSE VECTOR MULTIPLY FOR A BLOCK-SPARSE MATRIX
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2012
|
Application #:
|
12057742
|
Filing Dt:
|
03/28/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
AUTONOMIC VERIFICATION OF HDL MODELS USING REAL-TIME STATISTICAL ANALYSIS AND LAYERED FEEDBACK STAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
12058006
|
Filing Dt:
|
03/28/2008
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
Title:
|
METHODS FOR ALIGNING POLYMER FILMS AND RELATED STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12058990
|
Filing Dt:
|
03/31/2008
|
Publication #:
|
|
Pub Dt:
|
08/21/2008
| | | | |
Title:
|
SYSTEM AND METHOD FOR AUTOMATIC SELECTION OF TRANSMISSION LINE MACROMODELS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
12059114
|
Filing Dt:
|
03/31/2008
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
CONTACT MICROSCOPE USING POINT SOURCE ILLUMINATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12059163
|
Filing Dt:
|
03/31/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
METHOD AND SYSTEM FOR THE CALCULATION OF THE SENSITIVITIES OF AN ELECTRICAL PARAMETER OF AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2011
|
Application #:
|
12059174
|
Filing Dt:
|
03/31/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
SHALLOW TRENCH CAPACITOR COMPATIBLE WITH HIGH-K / METAL GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2012
|
Application #:
|
12059543
|
Filing Dt:
|
03/31/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
LOW OVERHEAD SOFT ERROR TOLERANT FLIP FLOP
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
12059595
|
Filing Dt:
|
03/31/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
CASCODE DRIVER WITH GATE OXIDE PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
12059641
|
Filing Dt:
|
03/31/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
DATA DRIVER CIRCUIT FOR A DYNAMIC RANDOM ACCESS MEMORY (DRAM) CONTROLLER OR THE LIKE AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2009
|
Application #:
|
12059888
|
Filing Dt:
|
03/31/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
TWO STEP OPTICAL PLANARIZING LAYER ETCH
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2011
|
Application #:
|
12060075
|
Filing Dt:
|
03/31/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
MEMORY ARRAY WITH DIODE DRIVER AND METHOD FOR FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2009
|
Application #:
|
12060500
|
Filing Dt:
|
04/01/2008
|
Title:
|
METHOD OF USE OF EPOXY-CONTAINING CYCLOALIPHATIC ACRYLIC POLYMERS AS ORIENTATION CONTROL LAYERS FOR BLOCK COPOLYMER THIN FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
12060516
|
Filing Dt:
|
04/01/2008
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
Method of Controlling Orientation of Domains in Block Copolymer Films
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2012
|
Application #:
|
12060551
|
Filing Dt:
|
04/01/2008
|
Publication #:
|
|
Pub Dt:
|
07/31/2008
| | | | |
Title:
|
SYSTEM AND METHOD FOR AUTOMATIC SELECTION OF TRANSMISSION LINE MACROMODELS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
12060563
|
Filing Dt:
|
04/01/2008
|
Publication #:
|
|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICALLY CONDUCTIVE FEATURE AND METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2011
|
Application #:
|
12060615
|
Filing Dt:
|
04/01/2008
|
Publication #:
|
|
Pub Dt:
|
07/31/2008
| | | | |
Title:
|
SELECTIVE LINKS IN SILICON HETERO-JUNCTION BIPOLAR TRANSISTORS USING CARBON DOPING AND METHOD OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
12060768
|
Filing Dt:
|
04/01/2008
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
METHOD OF LOGIC CIRCUIT SYNTHESIS AND DESIGN USING A DYNAMIC CIRCUIT LIBRARY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
12060889
|
Filing Dt:
|
04/02/2008
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
ON-CHIP ELECTRICALLY ALTERABLE RESISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
12060922
|
Filing Dt:
|
04/02/2008
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
SIMULTANEOUS CONDITIONING OF A PLURALITY OF MEMORY CELLS THROUGH SERIES RESISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2009
|
Application #:
|
12060937
|
Filing Dt:
|
04/02/2008
|
Title:
|
A METHOD OF FORMING CRACK TRAPPING AND ARREST IN THIN FILM STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
12061045
|
Filing Dt:
|
04/02/2008
|
Publication #:
|
|
Pub Dt:
|
10/08/2009
| | | | |
Title:
|
SYSTEM AND METHOD FOR PROVIDING A NON-POWER-OF-TWO BURST LENGTH IN A MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12061104
|
Filing Dt:
|
04/02/2008
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
METHOD FOR PREDICTION OF PREMATURE DIELECTRIC BREAKDOWN IN A SEMICONDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
12061113
|
Filing Dt:
|
04/02/2008
|
Publication #:
|
|
Pub Dt:
|
10/08/2009
| | | | |
Title:
|
SUBGROUNDRULE SPACE FOR IMPROVED METAL HIGH-K DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
12061155
|
Filing Dt:
|
04/02/2008
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT DESIGN UTILIZING ARRAY OF FUNCTIONALLY INTERCHANGEABLE DYNAMIC LOGIC CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
|
Application #:
|
12061268
|
Filing Dt:
|
04/02/2008
|
Publication #:
|
|
Pub Dt:
|
10/08/2009
| | | | |
Title:
|
SAMPLED CURRENT-INTEGRATING DECISION FEEDBACK EQUALIZER AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2011
|
Application #:
|
12061269
|
Filing Dt:
|
04/02/2008
|
Publication #:
|
|
Pub Dt:
|
07/31/2008
| | | | |
Title:
|
METHODS AND APPARATUS FOR ANALYZING TRANSMISSION LINES WITH DECOUPLING OF CONNECTORS AND OTHER CIRCUIT ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
12061283
|
Filing Dt:
|
04/02/2008
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
Title:
|
MATERIALS HAVING PREDEFINED MORPHOLOGIES AND METHODS OF FORMATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
12061662
|
Filing Dt:
|
04/03/2008
|
Publication #:
|
|
Pub Dt:
|
10/08/2009
| | | | |
Title:
|
EFFICIENT PRESENTATION OF FUNCTIONAL COVERAGE RESULTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
12061693
|
Filing Dt:
|
04/03/2008
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
METHOD OF FORMING POLYMER FEATURES BY DIRECTED SELF-ASSEMBLY OF BLOCK COPOLYMERS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2011
|
Application #:
|
12061774
|
Filing Dt:
|
04/03/2008
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
|
METHOD OF PRODUCING A LAND GRID ARRAY INTERPOSER STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2010
|
Application #:
|
12061777
|
Filing Dt:
|
04/03/2008
|
Publication #:
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Pub Dt:
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09/25/2008
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Title:
|
ORIENTING, POSITIONING, AND FORMING NANOSCALE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2012
|
Application #:
|
12062055
|
Filing Dt:
|
04/03/2008
|
Publication #:
|
|
Pub Dt:
|
10/08/2009
| | | | |
Title:
|
SILICON BASED MICROCHANNEL COOLING AND ELECTRICAL PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
12062130
|
Filing Dt:
|
04/03/2008
|
Publication #:
|
|
Pub Dt:
|
10/08/2009
| | | | |
Title:
|
SURFACE TREATMENT FOR SELECTIVE METAL CAP APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
|
Application #:
|
12062164
|
Filing Dt:
|
04/03/2008
|
Publication #:
|
|
Pub Dt:
|
07/31/2008
| | | | |
Title:
|
STRUCTURE AND METHOD TO FORM SEMICONDUCTOR-ON-PORES (SOP) FOR HIGH DEVICE PERFORMANCE AND LOW MANUFACTURING COST
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2011
|
Application #:
|
12062262
|
Filing Dt:
|
04/03/2008
|
Publication #:
|
|
Pub Dt:
|
10/08/2009
| | | | |
Title:
|
METHOD AND STRUCTURE FOR BALLAST RESISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
12062270
|
Filing Dt:
|
04/03/2008
|
Publication #:
|
|
Pub Dt:
|
07/31/2008
| | | | |
Title:
|
PROCESS FOR SOFTWARE SUPPORT RESOURCE ALLOCATION BASED ON ANALYSIS OF CATEGORIZED FIELD PROBLEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2010
|
Application #:
|
12062310
|
Filing Dt:
|
04/03/2008
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
12062586
|
Filing Dt:
|
04/04/2008
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
TEST YIELD ESTIMATE FOR SEMICONDUCTOR PRODUCTS CREATED FROM A LIBRARY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2010
|
Application #:
|
12062665
|
Filing Dt:
|
04/04/2008
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
VERSATILE SI-BASED PACKAGING WITH INTEGRATED PASSIVE COMPONENTS FOR MMWAVE APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2010
|
Application #:
|
12062972
|
Filing Dt:
|
04/04/2008
|
Publication #:
|
|
Pub Dt:
|
07/31/2008
| | | | |
Title:
|
LOW THRESHOLD VOLTAGE SEMICONDUCTOR DEVICE WITH DUAL THRESHOLD VOLTAGE CONTROL MEANS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
12072885
|
Filing Dt:
|
02/27/2008
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
Title:
|
METHOD FOR FORMING A ONE-TRANSISTOR MEMORY CELL AND RELATED STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
12080266
|
Filing Dt:
|
04/01/2008
|
Publication #:
|
|
Pub Dt:
|
12/23/2010
| | | | |
Title:
|
SILICON BASED OPTICAL VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2012
|
Application #:
|
12082637
|
Filing Dt:
|
04/10/2008
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
P-CHANNEL GERMANIUM ON INSULATOR (GOI) ONE TRANSISTOR MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
12098038
|
Filing Dt:
|
04/04/2008
|
Title:
|
SYSTEM FOR EXPANDING A WINDOW OF VALID DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2012
|
Application #:
|
12098172
|
Filing Dt:
|
04/04/2008
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR GENERATING PROFILE OF SOLUTIONS TRADING OFF NUMBER OF ACTIVITIES UTILIZED AND OBJECTIVE VALUE FOR BILINEAR INTEGER OPTIMIZATION MODELS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
12098303
|
Filing Dt:
|
04/04/2008
|
Publication #:
|
|
Pub Dt:
|
07/31/2008
| | | | |
Title:
|
SHARED RESOURCES IN A CHIP MULTIPROCESSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2011
|
Application #:
|
12098895
|
Filing Dt:
|
04/07/2008
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
Title:
|
ELECTRONICS STRUCTURES USING A SACRIFICIAL MULTI-LAYER HARDMASK SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2014
|
Application #:
|
12099175
|
Filing Dt:
|
04/08/2008
|
Publication #:
|
|
Pub Dt:
|
10/08/2009
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12099211
|
Filing Dt:
|
04/08/2008
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
SUBSTRATE BACKGATE FOR TRIGATE FET
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2011
|
Application #:
|
12099307
|
Filing Dt:
|
04/08/2008
|
Publication #:
|
|
Pub Dt:
|
10/08/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR ALPHA PARTICLE SENSOR IN SOI TECHNOLOGY AND STRUCTURE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2010
|
Application #:
|
12099339
|
Filing Dt:
|
04/08/2008
|
Publication #:
|
|
Pub Dt:
|
10/08/2009
| | | | |
Title:
|
PIXEL SENSOR WITH REDUCED IMAGE LAG
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2010
|
Application #:
|
12099381
|
Filing Dt:
|
04/08/2008
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
12099412
|
Filing Dt:
|
04/08/2008
|
Publication #:
|
|
Pub Dt:
|
09/18/2008
| | | | |
Title:
|
ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12099423
|
Filing Dt:
|
04/08/2008
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
DESIGN STRUCTURE FOR DYNAMIC LATCH STATE SAVING DEVICE AND PROTOCOL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
12100052
|
Filing Dt:
|
04/09/2008
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
PROGRAMMABLE SAMPLE CLOCK FOR EMPIRICAL SETUP TIME SELECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
12100441
|
Filing Dt:
|
04/10/2008
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
2-T SRAM CELL STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
12100481
|
Filing Dt:
|
04/10/2008
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
ASSESSING RESOURCES REQUIRED TO COMPLETE A VLSI DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
12100592
|
Filing Dt:
|
04/10/2008
|
Publication #:
|
|
Pub Dt:
|
10/02/2008
| | | | |
Title:
|
DESIGN STRUCTURE FOR ELECTRICALLY TUNABLE RESISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
12100598
|
Filing Dt:
|
04/10/2008
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH REDUCED GATE HEIGHT, AND RELATED FABRICATION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2010
|
Application #:
|
12100644
|
Filing Dt:
|
04/10/2008
|
Publication #:
|
|
Pub Dt:
|
08/21/2008
| | | | |
Title:
|
PRE-EPITAXIAL DISPOSABLE SPACER INTEGRATION SCHEME WITH VERY LOW TEMPERATURE SELECTIVE EPITAXY FOR ENHANCED DEVICE PERFORMANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
12100708
|
Filing Dt:
|
04/10/2008
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
METAL GATE COMPATIBLE FLASH MEMORY GATE STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2011
|
Application #:
|
12100996
|
Filing Dt:
|
04/10/2008
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
PROGRAMMABLE DATA SAMPLING RECEIVER FOR DIGITAL DATA SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2010
|
Application #:
|
12101439
|
Filing Dt:
|
04/11/2008
|
Publication #:
|
|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
STRUCTURE AND METHOD FOR DETERMINING AN OVERLAY ACCURACY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
12101449
|
Filing Dt:
|
04/11/2008
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
CONTROLLING IMPEDANCE AND THICKNESS VARIATIONS FOR MULTILAYER ELECTRONIC STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2011
|
Application #:
|
12101455
|
Filing Dt:
|
04/11/2008
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
CONTROLLING IMPEDANCE AND THICKNESS VARIATIONS FOR MULTILAYER ELECTRONIC STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2012
|
Application #:
|
12102032
|
Filing Dt:
|
04/14/2008
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES WITH A BODY-TO-SUBSTRATE CONNECTION FOR ENHANCED ELECTROSTATIC DISCHARGE PROTECTION, AND DESIGN STRUCTURES FOR SUCH SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2010
|
Application #:
|
12102051
|
Filing Dt:
|
04/14/2008
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
RADIO FREQUENCY (RF) INTEGRATED CIRCUIT (IC) PACKAGES WITH INTEGRATED APERTURE-COUPLED PATCH ANTENNA(S) IN RING AND/OR OFFSET CAVITIES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2011
|
Application #:
|
12102097
|
Filing Dt:
|
04/14/2008
|
Publication #:
|
|
Pub Dt:
|
02/04/2010
| | | | |
Title:
|
HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
12102510
|
Filing Dt:
|
04/14/2008
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
PERFORMING TEMPORAL CHECKING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
12103000
|
Filing Dt:
|
04/15/2008
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
TRENCH WIDENING WITHOUT MERGING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
12103038
|
Filing Dt:
|
04/15/2008
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
SYSTEM AND METHOD FOR DESIGNING A LOW LEAKAGE MONOTONIC CMOS LOGIC CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2009
|
Application #:
|
12103129
|
Filing Dt:
|
04/15/2008
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
METHOD FOR DIVIDING A HIGH-FREQUENCY SIGNAL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
12103256
|
Filing Dt:
|
04/15/2008
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
PARTIALLY UNDERFILLED SOLDER GRID ARRAYS
|
|