|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
09939432
|
Filing Dt:
|
08/24/2001
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
Title:
|
APPARATUS AND METHOD FOR CONDITIONING A CONTACT SURFACE OF A PROCESSING PAD USED IN PROCESSING MICROELECTRONIC WORKPIECES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
09939651
|
Filing Dt:
|
08/28/2001
|
Publication #:
|
|
Pub Dt:
|
02/14/2002
| | | | |
Title:
|
METHOD OF CONTROLLING STRIATIONS AND CD LOSS IN CONTACT OXIDE ETCH
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09939652
|
Filing Dt:
|
08/28/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
METHOD AND APPARATUS FOR MAGNETIC SHIELDING OF AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2003
|
Application #:
|
09939655
|
Filing Dt:
|
08/28/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
SENSING METHOD AND APPARATUS FOR RESISTANCE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09939905
|
Filing Dt:
|
08/27/2001
|
Publication #:
|
|
Pub Dt:
|
01/03/2002
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE USEFUL IN A SELF-ALIGNED CONTACT ETCH AND METHOD FOR MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2002
|
Application #:
|
09940008
|
Filing Dt:
|
08/27/2001
|
Publication #:
|
|
Pub Dt:
|
05/02/2002
| | | | |
Title:
|
REDUCED TERMINAL TESTING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09940010
|
Filing Dt:
|
08/27/2001
|
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT HAVING COMPRESSION CIRCUITRY FOR COMPRESSING TEST DATA, AND THE TEST SYSTEM AND METHOD FOR UTILIZING THE SEMICONDUCTOR INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09940203
|
Filing Dt:
|
08/27/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
CONCAVE FACE WIRE BOND CAPILLARY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2003
|
Application #:
|
09940229
|
Filing Dt:
|
08/27/2001
|
Publication #:
|
|
Pub Dt:
|
01/24/2002
| | | | |
Title:
|
EXPANDED IMPLANTATION OF CONTACT HOLES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2003
|
Application #:
|
09940328
|
Filing Dt:
|
08/27/2001
|
Publication #:
|
|
Pub Dt:
|
10/24/2002
| | | | |
Title:
|
ELECTRONIC DEVICE WITH INTERLEAVED PORTIONS FOR USE IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09940333
|
Filing Dt:
|
08/27/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
THRESHOLD VOLTAGE COMPENSATION CIRCUITS FOR LOW VOLTAGE AND LOW POWER CMOS INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2007
|
Application #:
|
09940792
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
06/13/2002
| | | | |
Title:
|
BURIED CONDUCTOR PATTERNS FORMED BY SURFACE TRANSFORMATION OF EMPTY SPACES IN SOLID STATE MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09940915
|
Filing Dt:
|
08/28/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
FULL PAGE INCREMENT/DECREMENT BURST FOR DDR SDRAM/SGRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
09940968
|
Filing Dt:
|
08/28/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
SRAM ARRAY WITH TEMPERATURE-COMPENSATED THRESHOLD VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2003
|
Application #:
|
09940976
|
Filing Dt:
|
08/28/2001
|
Title:
|
THREE TERMINAL MAGNETIC RANDOM ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09941020
|
Filing Dt:
|
08/28/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
MULTI-LAYER LEAD FRAME FOR A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09941021
|
Filing Dt:
|
08/28/2001
|
Publication #:
|
|
Pub Dt:
|
04/25/2002
| | | | |
Title:
|
DEVICE AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
09941068
|
Filing Dt:
|
08/28/2001
|
Publication #:
|
|
Pub Dt:
|
05/15/2003
| | | | |
Title:
|
CO-SIMULATION OF VERILOG/PLI AND SYSTEM C MODULES USING REMOTE PROCEDURE CALL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2003
|
Application #:
|
09941130
|
Filing Dt:
|
08/28/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
MEMORY CIRCUIT REGULATION SYSTEM AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2002
|
Application #:
|
09941201
|
Filing Dt:
|
08/28/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
BI-LEVEL DIGIT LINE ARCHITECTURE FOR HIGH DENSITY DRAMS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2002
|
Application #:
|
09941203
|
Filing Dt:
|
08/28/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
METHOD AND APPARATUS FOR IMPLEMENTING SELECTED FUNCTIONALITY ON AN INTEGRATED CIRCUIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2003
|
Application #:
|
09941315
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
MULTI-CHIP MODULE WITH EXTENSION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2003
|
Application #:
|
09941317
|
Filing Dt:
|
08/28/2001
|
Publication #:
|
|
Pub Dt:
|
04/18/2002
| | | | |
Title:
|
APPARATUS AND METHODS OF PACKAGING AND TESTING DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
09941557
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
OPTICAL INTERCONNECT IN HIGH-SPEED MEMORY SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
09941602
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
SMALL ANTI-FUSE CIRCUIT TO FACILITATE PARALLEL FUSE BLOWING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09941749
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
04/25/2002
| | | | |
Title:
|
CSP BGA TEST SOCKET WITH INSERT AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
09941760
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
04/04/2002
| | | | |
Title:
|
PHOTOLITHOGRAPHIC STRUCTURES USING MULTIPLE ANTI-REFLECTING COATINGS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2005
|
Application #:
|
09941763
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
METHOD AND APPARATUS FOR REFRESHING MEMORY TO PRESERVE DATA INTEGRITY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
09941827
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
METHOD OF IMPROVED HIGH K DIELECTRIC-POLYSILICON INTERFACE FOR CMOS DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2006
|
Application #:
|
09941853
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
ELECTRICAL CONTACT ARRAY FOR SUBSTRATE ASSEMBLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
09942108
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
DIFFUSION BARRIER LAYER FOR SEMICONDUCTOR WAFER FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09942136
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
03/14/2002
| | | | |
Title:
|
LASER MARKING TECHNIQUES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
09942140
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
03/14/2002
| | | | |
Title:
|
LOC SEMICONDUCTOR ASSEMBLED WITH ROOM TEMPERATURE ADHESIVE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09942178
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
IC PACKAGE WITH DUAL HEAT SPREADERS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
09942182
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
04/25/2002
| | | | |
Title:
|
LEADFRAMES INCLUDING OFFSETS EXTENDING FROM A MAJOR PLANE THEREOF, PACKAGED SEMICONDUCTOR DEVICES INCLUDING SAME, AND METHODS OF DESIGNING AND FABRICATING SUCH LEADFRAMES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2003
|
Application #:
|
09942191
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
01/10/2002
| | | | |
Title:
|
TECHNIQUE FOR ELIMINATION OF PITTING ON SILICON SUBSTRATE DURING GATE STACK ETCH
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09942207
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
08/29/2002
| | | | |
Title:
|
GATE VOLTAGE TESTKEY FOR ISOLATION TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2002
|
Application #:
|
09942221
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
08/15/2002
| | | | |
Title:
|
CIRCUIT AND METHOD FOR HEATING AN ADHESIVE TO PACKAGE OR REWORK A SEMICONDUCTOR DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2003
|
Application #:
|
09942246
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
01/17/2002
| | | | |
Title:
|
METHOD AND APPARATUS FOR FORMING METAL CONTACTS ON A SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
09942247
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
HEAT SINK WITH ALIGNMENT AND RETAINING FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2004
|
Application #:
|
09942284
|
Filing Dt:
|
08/27/2001
|
Publication #:
|
|
Pub Dt:
|
03/14/2002
| | | | |
Title:
|
THRESHOLD VOLTAGE COMPENSATION CIRCUITS FOR LOW VOLTAGE AND LOW POWER CMOS INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
09942389
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
SYSTEM AND METHOD FOR CONTROLLING MULTI-BANK EMBEDDED DRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2003
|
Application #:
|
09942681
|
Filing Dt:
|
08/31/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
COMBINED DYNAMIC LOGIC GATE AND LEVEL SHIFTER AND METHOD EMPLOYING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
09943134
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
PROGRAMMABLE ARRAY LOGIC OR MEMORY DEVICES WITH ASYMMETRICAL TUNNEL BARRIERS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09943146
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
10/17/2002
| | | | |
Title:
|
METHODS, COMPLEXES, AND SYSTEM FOR FORMING METAL-CONTAINING FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
09943187
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
03/13/2003
| | | | |
Title:
|
METHOD OF FORMING CHALCOGENIDE COMPRISING DEVICES AND METHOD OF FORMING A PROGRAMMABLE MEMORY CELL OF MEMORY CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2005
|
Application #:
|
09943190
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
METHOD OF FORMING CHALCOGENIDE COMPRISING DEVICES, METHOD OF FORMING A PROGRAMMABLE MEMORY CELL OF MEMORY CIRCUITRY, AND A CHALCOGENIDE COMPRISING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
09943199
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
METHOD OF FORMING CHALCOGENIDE COMPRISING DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
09943324
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
01/10/2002
| | | | |
Title:
|
STRUCTURE AND METHOD FOR DUAL GATE OXIDE THICKNESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2003
|
Application #:
|
09943367
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/13/2003
| | | | |
Title:
|
TESTMODE TO INCREASE ACCLERATION IN BURN-IN
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2003
|
Application #:
|
09943381
|
Filing Dt:
|
08/30/2001
|
Title:
|
SELECTIVE CMP SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2004
|
Application #:
|
09943393
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
01/10/2002
| | | | |
Title:
|
STRUCTURE AND METHOD FOR DUAL GATE OXIDE THICKNESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2004
|
Application #:
|
09943398
|
Filing Dt:
|
08/30/2001
|
Title:
|
STRUCTURE AND METHOD FOR DUAL GATE OXIDE THICKNESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2004
|
Application #:
|
09943426
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
10/02/2003
| | | | |
Title:
|
INTEGRATED CIRCUIT DEVICE AND FABRICATION USING METAL-DOPED CHALCOGENIDE MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09943473
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
04/24/2003
| | | | |
Title:
|
SYNCHRONOUS FLASH MEMORY COMMAND SEQUENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2003
|
Application #:
|
09943474
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
NON-VOLATILE MEMORY WITH ADDRESS DESCRAMBLING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09943478
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
02/07/2002
| | | | |
Title:
|
METAL COMPLEXES WITH CHELATING C-, N-DONOR LIGANDS FOR FORMING METAL-CONTAINING FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
09943479
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/13/2003
| | | | |
Title:
|
ERASE VERIFY FOR NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2003
|
Application #:
|
09943480
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
NON-VOLATILE MEMORY WITH TEST ROWS FOR DISTURB DETECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2006
|
Application #:
|
09943586
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
PROGRAM LOADING MECHANISM THROUGH A SINGLE INPUT DATA PATH
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2005
|
Application #:
|
09943642
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
08/29/2002
| | | | |
Title:
|
DATA COMPRESSION READ MODE FOR MEMORY TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
09943643
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
09/05/2002
| | | | |
Title:
|
FLASH CELL FUSE CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09943726
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
04/11/2002
| | | | |
Title:
|
METHOD FOR ERASING DATA FROM A SINGLE ELECTRON RESSISTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2003
|
Application #:
|
09943844
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
METHOD OF REDUCING WATER SPOTTING AND OXIDE GROWTH ON A SEMICONDUCTOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09943845
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/07/2002
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE ELECTRICAL ENHANCEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2003
|
Application #:
|
09943897
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/13/2003
| | | | |
Title:
|
METHOD OF MANUFACTURING WIRE BONDED MICROELECTRONIC DEVICE ASSEMBLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
09943967
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/14/2002
| | | | |
Title:
|
METHOD FOR CONTROLLING THE DEPTH OF IMMERSION OF A SEMICONDUCTOR ELEMENT IN AN EXPOSED SURFACE OF A VISCOUS FLUID
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
09943968
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
Technique to simultaneously distribute clock signals and data on integrated circuits, interposers and circuit boards
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09943993
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
01/17/2002
| | | | |
Title:
|
FUSE FOR USE IN A SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICES INCLUDING THE FUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09943995
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
01/24/2002
| | | | |
Title:
|
METHOD FOR REDUCING PHOTOLITHOGRAPHIC STEPS IN A SEMICONDUCTOR INTERCONNECT PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2003
|
Application #:
|
09944224
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
03/07/2002
| | | | |
Title:
|
ORGANOMETALLIC COMPOUND MIXTURES IN CHEMICAL VAPOR DEPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
09944233
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/14/2002
| | | | |
Title:
|
APPARATUS AND METHOD FOR MODIFYING THE CONFIGURATION OF AN EXPOSED SURFACE OF A VISCOUS FLUID
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09944238
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
04/25/2002
| | | | |
Title:
|
METHOD AND APPARATUS FOR REDUCING BLEED CURRENTS WITHIN A DRAM ARRAY HAVING ROW-TO-COLUMN SHORTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2003
|
Application #:
|
09944245
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
METHODS OF THINNING MICROELECTRONIC WORKPIECES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2005
|
Application #:
|
09944246
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
PACKAGED MICROELECTRONIC DEVICES AND METHODS OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09944258
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
02/14/2002
| | | | |
Title:
|
SINGLE ELECTRON RESISTOR MEMORY DEVICE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09944259
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
02/21/2002
| | | | |
Title:
|
METHOD FOR FORMING SINGLE ELECTRON RESISTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2003
|
Application #:
|
09944436
|
Filing Dt:
|
08/31/2001
|
Publication #:
|
|
Pub Dt:
|
01/10/2002
| | | | |
Title:
|
METHOD OF FABRICATING A CONTACT STRUCTURE HAVING A COMPOSITE BARRIER LAYER BETWEEN A PLATINUM LAYER AND A POLYSILICON PLUG
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
09944463
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
PRINTING STENCILS FOR ELECTRONIC SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
09944465
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
METHOD OF MANUFACTURING MICROELECTRONIC DEVICES, INCLUDING METHODS OF UNDERFILLING MICROELECTRONIC COMPONENTS THROUGH AN UNDERFILL APERTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2003
|
Application #:
|
09944484
|
Filing Dt:
|
08/29/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
SYSTEM AND METHOD FOR SKEW COMPENSATING A CLOCK SIGNAL AND FOR CAPTURING A DIGITAL SIGNAL USING THE SKEW COMPENSATED CLOCK SIGNAL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09944502
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/14/2002
| | | | |
Title:
|
APPARATUS FOR FILLING A GAP BETWEEN SPACED LAYERS OF A SEMICONDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2003
|
Application #:
|
09944505
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/14/2002
| | | | |
Title:
|
METHOD AND APPARATUS FOR IMPLEMENTING SELECTED FUNCTIONALITY ON AN INTEGRATED CIRCUIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09944723
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/14/2002
| | | | |
Title:
|
PACKAGED MICROELECTRONIC DIE ASSEMBLIES AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2003
|
Application #:
|
09944726
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
APPARATUS AND METHOD FOR ENHANCED PROCESSING OF MICROELECTRONIC WORKPIECES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2003
|
Application #:
|
09944750
|
Filing Dt:
|
08/31/2001
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
Title:
|
ON-CHIP TESTING CIRCUIT AND METHOD FOR INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
09944903
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
HIGH ASPECT RATIO CONTACT STRUCTURE WITH REDUCED SILICON CONSUMPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
09944936
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
INPUT STAGE APPARATUS AND METHOD HAVING A VARIABLE REFERENCE VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2002
|
Application #:
|
09944948
|
Filing Dt:
|
08/30/2001
|
Title:
|
LOW VOLTAGE CHARGE PUMP APPARATUS AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2002
|
Application #:
|
09944956
|
Filing Dt:
|
08/30/2001
|
Title:
|
MRAM SENSE LAYER ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2005
|
Application #:
|
09944981
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
CRYSTALLINE OR AMORPHOUS MEDIUM-K GATE OXIDES, Y2O3 AND GD2O3
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
09944985
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
SCALABLE FLASH/NV STRUCTURES AND DEVICES WITH EXTENDED ENDURANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2004
|
Application #:
|
09944986
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
Title:
|
DECOUPLING CAPACITOR FOR HIGH FREQUENCY NOISE IMMUNITY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2009
|
Application #:
|
09944993
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
BIT INVERSION IN MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
09945042
|
Filing Dt:
|
08/31/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
MULTIPLE CHIP STACK STRUCTURE AND COOLING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2004
|
Application #:
|
09945077
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/20/2003
| | | | |
Title:
|
METHODS FOR MAKING SEMICONDUCTOR STRUCTURES HAVING HIGH-SPEED AREAS AND HIGH-DENSITY AREAS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
09945084
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
METHOD AND APPARATUS FOR CIRCUIT COMPLETION THROUGH THE USE OF BALL BONDS OR OTHER CONNECTIONS DURING THE FORMATION OF SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2004
|
Application #:
|
09945137
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
METHODS OF FORMING PEROVSKITE-TYPE MATERIAL AND CAPACITOR DIELECTRIC HAVING PEROVSKITE-TYPE CRYSTALLINE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
09945167
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
METHOD AND APPARATUS FOR IRRADIATING A MICROLITHOGRAPHIC SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2003
|
Application #:
|
09945253
|
Filing Dt:
|
08/30/2001
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
Title:
|
APPARATUS AND METHOD FOR GENERATING AN OSCILLATING SIGNAL
|
|