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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036550/0001   Pages: 983
Recorded: 09/03/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
10/28/2008
Application #:
11657154
Filing Dt:
01/24/2007
Publication #:
Pub Dt:
05/31/2007
Title:
METHOD OF APPLYING STRESSES TO PFET AND NFET TRANSISTOR CHANNELS FOR IMPROVED PERFORMANCE
2
Patent #:
Issue Dt:
01/13/2009
Application #:
11668097
Filing Dt:
01/29/2007
Publication #:
Pub Dt:
07/31/2008
Title:
INTEGRATED HEAT SPREADER AND EXCHANGER
3
Patent #:
Issue Dt:
12/09/2008
Application #:
11668224
Filing Dt:
01/29/2007
Publication #:
Pub Dt:
07/31/2008
Title:
FABRICATION OF PHASE CHANGE MEMORY ELEMENT WITH PHASE-CHANGE ELECTRODES USING CONFORMAL DEPOSITION
4
Patent #:
Issue Dt:
03/22/2011
Application #:
11668542
Filing Dt:
01/30/2007
Publication #:
Pub Dt:
07/31/2008
Title:
PRINT EVENTS IN THE SIMULATION OF A DIGITAL SYSTEM
5
Patent #:
Issue Dt:
02/24/2009
Application #:
11668545
Filing Dt:
01/30/2007
Publication #:
Pub Dt:
07/31/2008
Title:
TECHNIQUES FOR IMPROVING WRITE STABILITY OF MEMORY WITH DECOUPLED READ AND WRITE BIT LINES
6
Patent #:
Issue Dt:
06/28/2011
Application #:
11668717
Filing Dt:
01/30/2007
Publication #:
Pub Dt:
07/31/2008
Title:
CONTACT FORMING METHOD AND RELATED SEMICONDUCTOR DEVICE
7
Patent #:
Issue Dt:
09/06/2011
Application #:
11668731
Filing Dt:
01/30/2007
Publication #:
Pub Dt:
07/31/2008
Title:
METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR PRODUCT RANDOMIZATION AND ANALYSIS IN A MANUFACTURING ENVIRONMENT
8
Patent #:
Issue Dt:
06/23/2009
Application #:
11668790
Filing Dt:
01/30/2007
Publication #:
Pub Dt:
05/31/2007
Title:
STRESS ENGINEERING USING DUAL PAD NITRIDE WITH SELECTIVE SOI DEVICE ARCHITECTURE
9
Patent #:
Issue Dt:
09/14/2010
Application #:
11669158
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
07/31/2008
Title:
METHOD AND SYSTEM FOR DESIGN AND MODELING OF TRANSMISSION LINES
10
Patent #:
Issue Dt:
08/26/2008
Application #:
11669175
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
07/31/2008
Title:
PELLICLE FILM OPTIMIZED FOR IMMERSION LITHOGRAPHY SYSTEMS WITH NA>1
11
Patent #:
Issue Dt:
05/31/2011
Application #:
11669179
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
07/19/2007
Title:
METHOD AND SYSTEM FOR INTELLIGENT AUTOMATED RETICLE MANAGMENT
12
Patent #:
Issue Dt:
10/05/2010
Application #:
11669214
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
07/31/2008
Title:
METHOD AND SYSTEM FOR PAD CONDITIONING IN AN ECMP PROCESS
13
Patent #:
Issue Dt:
10/21/2008
Application #:
11669250
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
07/31/2008
Title:
ELECTRONIC CIRCUIT FOR MEASUREMENT OF TRANSISTOR VARIABILITY AND THE LIKE
14
Patent #:
NONE
Issue Dt:
Application #:
11669267
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
07/31/2008
Title:
WAVEGUIDE COUPLING DEVICES
15
Patent #:
Issue Dt:
09/07/2010
Application #:
11669362
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
07/31/2008
Title:
ELECTRONIC COMPONENT FOR AN ELECTRONIC CARRIER SUBSTRATE
16
Patent #:
Issue Dt:
09/14/2010
Application #:
11669496
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
07/31/2008
Title:
METHOD FOR FORMING AN INDIUM CAP LAYER
17
Patent #:
Issue Dt:
01/01/2008
Application #:
11669598
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
05/31/2007
Title:
STRUCTURE AND METHOD FOR MANUFACTURING STRAINED FINFET
18
Patent #:
NONE
Issue Dt:
Application #:
11669645
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
07/31/2008
Title:
METHOD OF FORMING DISPOSABLE SPACERS FOR IMPROVED STRESSED NITRIDE FILM EFFECTIVENESS
19
Patent #:
Issue Dt:
04/28/2009
Application #:
11669902
Filing Dt:
01/31/2007
Publication #:
Pub Dt:
07/31/2008
Title:
STRAINED MOS DEVICES USING SOURCE/DRAIN EPITAXY
20
Patent #:
Issue Dt:
03/26/2013
Application #:
11670017
Filing Dt:
02/01/2007
Publication #:
Pub Dt:
08/07/2008
Title:
METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR USING DIRECT MEMORY ACCESS TO INITIALIZE A PROGRAMMABLE LOGIC DEVICE
21
Patent #:
Issue Dt:
04/26/2011
Application #:
11670080
Filing Dt:
02/01/2007
Publication #:
Pub Dt:
08/07/2008
Title:
REDUCED FRICTION MOLDS FOR INJECTION MOLDED SOLDER PROCESSING
22
Patent #:
NONE
Issue Dt:
Application #:
11670262
Filing Dt:
02/01/2007
Publication #:
Pub Dt:
06/07/2007
Title:
ULTRA-THIN SILICON BRIDGING LAYERS OVERLYING AIR CAVITIES
23
Patent #:
Issue Dt:
07/22/2008
Application #:
11670537
Filing Dt:
02/02/2007
Publication #:
Pub Dt:
08/07/2008
Title:
FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH
24
Patent #:
Issue Dt:
08/23/2011
Application #:
11670621
Filing Dt:
02/02/2007
Publication #:
Pub Dt:
08/07/2008
Title:
SYSTEMS AND METHODS FOR CONTROLLING POSITION OF CHARGED POLYMER INSIDE NANOPORE
25
Patent #:
Issue Dt:
08/25/2009
Application #:
11670778
Filing Dt:
02/02/2007
Publication #:
Pub Dt:
05/31/2007
Title:
METHODS OF FORMING LOW-K DIELECTRIC LAYERS CONTAINING CARBON NANOSTRUCTURES
26
Patent #:
NONE
Issue Dt:
Application #:
11671113
Filing Dt:
02/05/2007
Publication #:
Pub Dt:
06/07/2007
Title:
METHOD AND APPARATUS FOR FABRICATING CMOS FIELD EFFECT TRANSISTORS
27
Patent #:
Issue Dt:
05/19/2009
Application #:
11671795
Filing Dt:
02/06/2007
Publication #:
Pub Dt:
06/14/2007
Title:
METHOD AND STRUCTURE TO CREATE MULTIPLE DEVICE WIDTHS IN FINFET TECHNOLOGY IN BOTH BULK AND SOI
28
Patent #:
Issue Dt:
03/02/2010
Application #:
11672050
Filing Dt:
02/07/2007
Publication #:
Pub Dt:
08/07/2008
Title:
SYSTEMATIC COMPLIANCE CHECKING OF A PROCESS
29
Patent #:
Issue Dt:
05/18/2010
Application #:
11672059
Filing Dt:
02/07/2007
Publication #:
Pub Dt:
08/07/2008
Title:
STRUCTURE AND METHOD FOR MONITORING AND CHARACTERIZING PATTERN DENSITY DEPENDENCE ON THERMAL ABSORPTION IN A SEMICONDUCTOR MANUFACTURING PROCESS
30
Patent #:
Issue Dt:
02/23/2010
Application #:
11672109
Filing Dt:
02/07/2007
Publication #:
Pub Dt:
08/07/2008
Title:
SEMICONDUCTOR STRUCTURE INCLUDING DOPED SILICON CARBON LINER LAYER AND METHOD FOR FABRICATION THEREOF
31
Patent #:
Issue Dt:
08/12/2008
Application #:
11672110
Filing Dt:
02/07/2007
Publication #:
Pub Dt:
08/07/2008
Title:
PROGRAMMABLE FUSE/NON-VOLATILE MEMORY STRUCTURES USING EXTERNALLY HEATED PHASE CHANGE MATERIAL
32
Patent #:
Issue Dt:
01/25/2011
Application #:
11672217
Filing Dt:
02/07/2007
Publication #:
Pub Dt:
08/07/2008
Title:
METHOD, SYSTEM, PROGRAM PRODUCT FOR BONDING TWO CIRCUITRY-INCLUDING SUBSTRATES AND RELATED STAGE
33
Patent #:
Issue Dt:
04/15/2008
Application #:
11672251
Filing Dt:
02/07/2007
Publication #:
Pub Dt:
06/07/2007
Title:
SILICON-ON-INSULATOR (SOI) READ ONLY MEMORY (ROM) ARRAY AND METHOD OF MAKING A SOI ROM
34
Patent #:
Issue Dt:
09/07/2010
Application #:
11672309
Filing Dt:
02/07/2007
Publication #:
Pub Dt:
08/07/2008
Title:
METHODS AND APPARATUS FOR CALIBRATING OUTPUT VOLTAGE LEVELS ASSOCIATED WITH CURRENT-INTEGRATING SUMMING AMPLIFIER
35
Patent #:
NONE
Issue Dt:
Application #:
11672363
Filing Dt:
02/07/2007
Publication #:
Pub Dt:
06/07/2007
Title:
METHOD FOR ENHANCED UNI-DIRECTIONAL DIFFUSION OF METAL AND SUBSEQUENT SILICIDE FORMATION
36
Patent #:
Issue Dt:
05/05/2009
Application #:
11672527
Filing Dt:
02/08/2007
Publication #:
Pub Dt:
08/14/2008
Title:
RANDOM TEST GENERATION USING AN OPTIMIZATION SOLVER
37
Patent #:
Issue Dt:
05/11/2010
Application #:
11672599
Filing Dt:
02/08/2007
Publication #:
Pub Dt:
08/14/2008
Title:
SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE STRUCTURE
38
Patent #:
Issue Dt:
03/31/2009
Application #:
11672737
Filing Dt:
02/08/2007
Publication #:
Pub Dt:
08/14/2008
Title:
AUTOMATIC STATIC PHASE ERROR AND JITTER COMPENSATION IN PLL CIRCUITS
39
Patent #:
Issue Dt:
03/23/2010
Application #:
11672973
Filing Dt:
02/09/2007
Publication #:
Pub Dt:
08/14/2008
Title:
METHOD AND APPARATUS FOR SHUTTING OFF DATA CAPTURE ACROSS ASYNCHRONOUS CLOCK DOMAINS DURING AT-SPEED TESTING
40
Patent #:
NONE
Issue Dt:
Application #:
11673128
Filing Dt:
02/09/2007
Publication #:
Pub Dt:
08/14/2008
Title:
METHOD AND SYSTEM FOR PLASMA ETCHING HAVING IMPROVED ACROSS-WAFER ETCH UNIFORMITY
41
Patent #:
Issue Dt:
06/09/2009
Application #:
11673276
Filing Dt:
02/09/2007
Publication #:
Pub Dt:
08/14/2008
Title:
METHOD FOR INTEGRATING LINER FORMATION IN BACK END OF LINE PROCESSING
42
Patent #:
Issue Dt:
10/06/2009
Application #:
11673298
Filing Dt:
02/09/2007
Publication #:
Pub Dt:
08/14/2008
Title:
SYSTEM AND METHOD FOR GENERATING CONSTRAINT PRESERVING TESTCASES IN THE PRESENCE OF DEAD-END CONSTRAINTS
43
Patent #:
Issue Dt:
03/03/2009
Application #:
11673369
Filing Dt:
02/09/2007
Publication #:
Pub Dt:
06/07/2007
Title:
NON-DESTRUCTIVE EVALUATION OF MICROSTRUCTURE AND INTERFACE ROUGHNESS OF ELECTRICALLY CONDUCTING LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS IN DEEP SUB-MICRON REGIME
44
Patent #:
Issue Dt:
06/15/2010
Application #:
11673611
Filing Dt:
02/12/2007
Publication #:
Pub Dt:
08/14/2008
Title:
FORMATION OF MASKS/RETICLES HAVING DUMMY FEATURES
45
Patent #:
Issue Dt:
07/20/2010
Application #:
11673824
Filing Dt:
02/12/2007
Publication #:
Pub Dt:
08/14/2008
Title:
SEMICONDUCTOR DEVICE STRESS MODELING METHODOLOGY
46
Patent #:
Issue Dt:
11/03/2009
Application #:
11673901
Filing Dt:
02/12/2007
Publication #:
Pub Dt:
08/14/2008
Title:
METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-K GATE DIELECTRIC STACKS
47
Patent #:
Issue Dt:
09/02/2008
Application #:
11674292
Filing Dt:
02/13/2007
Publication #:
Pub Dt:
08/14/2008
Title:
SINGLE-ENDED MEMORY CELL WITH IMPROVED READ STABILITY AND MEMORY USING THE CELL
48
Patent #:
NONE
Issue Dt:
Application #:
11674453
Filing Dt:
02/13/2007
Publication #:
Pub Dt:
08/14/2008
Title:
SELF-ALIGNED EPITAXIAL GROWTH OF SEMICONDUCTOR NANOWIRES
49
Patent #:
Issue Dt:
11/15/2011
Application #:
11674598
Filing Dt:
02/13/2007
Publication #:
Pub Dt:
08/14/2008
Title:
METHODOLOGIES AND ANALYTICS TOOLS FOR IDENTIFYING WHITE SPACE OPPORTUNITIES IN A GIVEN INDUSTRY
50
Patent #:
NONE
Issue Dt:
Application #:
11674775
Filing Dt:
02/14/2007
Publication #:
Pub Dt:
08/14/2008
Title:
APPARRATUS AND METHOD FOR UNIVERSAL PROGRAMMABLE ERROR DETECTION AND REAL TIME ERROR DETECTION
51
Patent #:
NONE
Issue Dt:
Application #:
11675296
Filing Dt:
02/15/2007
Publication #:
Pub Dt:
08/21/2008
Title:
STRUCTURE FOR METAL CAP APPLICATIONS
52
Patent #:
Issue Dt:
06/21/2011
Application #:
11675445
Filing Dt:
02/15/2007
Publication #:
Pub Dt:
08/21/2008
Title:
METHOD AND APPARATUS FOR MANUFACTURING ELECTRONIC INTEGRATED CIRCUIT CHIP
53
Patent #:
Issue Dt:
06/29/2010
Application #:
11675705
Filing Dt:
02/16/2007
Publication #:
Pub Dt:
08/21/2008
Title:
INTERCONNECT STRUCTURE WITH BI-LAYER METAL CAP
54
Patent #:
Issue Dt:
11/18/2008
Application #:
11676030
Filing Dt:
02/16/2007
Publication #:
Pub Dt:
06/21/2007
Title:
SELF-ALIGNED PLANAR DOUBLE-GATE TRANSISTOR STRUCTURE
55
Patent #:
Issue Dt:
03/30/2010
Application #:
11676447
Filing Dt:
02/19/2007
Publication #:
Pub Dt:
06/21/2007
Title:
RECOVERY OF HYDROPHOBICITY OF LOW-K AND ULTRA LOW-K ORGANOSILICATE FILMS USED AS INTER METAL DIELECTRICS
56
Patent #:
Issue Dt:
12/07/2010
Application #:
11676522
Filing Dt:
02/20/2007
Publication #:
Pub Dt:
08/21/2008
Title:
BEOL INTERCONNECT STRUCTURES WITH IMPROVED RESISTANCE TO STRESS
57
Patent #:
Issue Dt:
11/01/2011
Application #:
11676674
Filing Dt:
02/20/2007
Publication #:
Pub Dt:
06/21/2007
Title:
SYSTEM AND METHOD FOR PLASMA INDUCED MODIFICATION AND IMPROVEMENT OF CRITICAL DIMENSION UNIFORMITY
58
Patent #:
Issue Dt:
01/04/2011
Application #:
11676853
Filing Dt:
02/20/2007
Publication #:
Pub Dt:
08/21/2008
Title:
METHOD AND SYSTEM FOR DETECTING SYNCHRONIZATION ERRORS IN PROGRAMS
59
Patent #:
Issue Dt:
10/06/2009
Application #:
11677100
Filing Dt:
02/21/2007
Publication #:
Pub Dt:
08/21/2008
Title:
METHOD TO REMOVE BEOL SACRIFICIAL MATERIALS AND CHEMICAL RESIDUES BY IRRADIATION
60
Patent #:
Issue Dt:
08/24/2010
Application #:
11677207
Filing Dt:
02/21/2007
Publication #:
Pub Dt:
08/21/2008
Title:
SEMICONDUCTOR STRUCTURE INCLUDING GATE ELECTRODE HAVING LATERALLY VARIABLE WORK FUNCTION
61
Patent #:
Issue Dt:
02/23/2010
Application #:
11677598
Filing Dt:
02/22/2007
Publication #:
Pub Dt:
08/28/2008
Title:
METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR
62
Patent #:
Issue Dt:
03/20/2012
Application #:
11677652
Filing Dt:
02/22/2007
Publication #:
Pub Dt:
08/28/2008
Title:
SEQUENTIAL ENCODING FOR RELATIONAL ANALYSIS (SERA) OF A SOFTWARE MODEL
63
Patent #:
Issue Dt:
06/23/2009
Application #:
11677666
Filing Dt:
02/22/2007
Publication #:
Pub Dt:
06/21/2007
Title:
INCORPORATION OF UNCERTAINTY INFORMATION IN MODELING A CHARACTERISTIC OF A DEVICE
64
Patent #:
Issue Dt:
11/03/2009
Application #:
11677776
Filing Dt:
02/22/2007
Publication #:
Pub Dt:
06/28/2007
Title:
BIPOLAR TRANSISTOR WITH ISOLATION AND DIRECT CONTACTS
65
Patent #:
Issue Dt:
04/20/2010
Application #:
11678069
Filing Dt:
02/23/2007
Publication #:
Pub Dt:
08/28/2008
Title:
STICHED IC LAYOUT METHODS, SYSTEMS AND PROGRAM PRODUCT
66
Patent #:
Issue Dt:
10/26/2010
Application #:
11678089
Filing Dt:
02/23/2007
Publication #:
Pub Dt:
09/25/2008
Title:
RECYCLING OF ELECTROCHEMICAL-MECHANICAL PLANARIZATION (ECMP) SLURRIES/ELECTROLYTES
67
Patent #:
Issue Dt:
04/12/2011
Application #:
11678163
Filing Dt:
02/23/2007
Publication #:
Pub Dt:
08/28/2008
Title:
VARIABLE FILL AND CHEESE FOR MITIGATION OF BEOL TOPOGRAPHY
68
Patent #:
Issue Dt:
02/01/2011
Application #:
11678338
Filing Dt:
02/23/2007
Publication #:
Pub Dt:
08/28/2008
Title:
LOW-TEMPERATURE ELECTRICALLY ACTIVATED GATE ELECTRODE AND METHOD OF FABRICATING SAME
69
Patent #:
Issue Dt:
08/24/2010
Application #:
11679171
Filing Dt:
02/26/2007
Publication #:
Pub Dt:
08/28/2008
Title:
ESTIMATION OF PROCESS VARIATION IMPACT OF SLACK IN MULTI-CORNER PATH-BASED STATIC TIMING ANALYSIS
70
Patent #:
NONE
Issue Dt:
Application #:
11679192
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/28/2008
Title:
Device, System and Method of Verification of Address Translation Mechanisms
71
Patent #:
NONE
Issue Dt:
Application #:
11679226
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/28/2008
Title:
REWORKABLE CHIP STACK
72
Patent #:
Issue Dt:
05/10/2011
Application #:
11679247
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/28/2008
Title:
METHOD OF REMOVING GRAPHITIC AND/OR FLUORINATED ORGANIC LAYERS FROM THE SURFACE OF A CHIP PASSIVATION LAYER HAVING SI-CONTAINING COMPOUNDS
73
Patent #:
NONE
Issue Dt:
Application #:
11679308
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/28/2008
Title:
STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY
74
Patent #:
NONE
Issue Dt:
Application #:
11679407
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/28/2008
Title:
ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME
75
Patent #:
Issue Dt:
12/28/2010
Application #:
11679483
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/28/2008
Title:
STRUCTURE INCLUDING VIA HAVING REFRACTORY METAL COLLAR AT COPPER WIRE AND DIELECTRIC LAYER LINER-LESS INTERFACE AND RELATED METHOD
76
Patent #:
Issue Dt:
06/03/2008
Application #:
11679785
Filing Dt:
02/27/2007
Title:
RECTIFYING ELEMENT FOR A CROSSPOINT BASED MEMORY ARRAY ARCHITECTURE
77
Patent #:
Issue Dt:
09/14/2010
Application #:
11679831
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/28/2008
Title:
PARAMETER ORDERING FOR MULTI-CORNER STATIC TIMING ANALYSIS
78
Patent #:
Issue Dt:
07/15/2008
Application #:
11679862
Filing Dt:
02/28/2007
Title:
FORMATION OF SPACERS FOR FINFETS (FIELD EFFECT TRANSISTORS)
79
Patent #:
Issue Dt:
05/27/2014
Application #:
11679869
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
08/28/2008
Title:
RADIATION HARDENED FINFET
80
Patent #:
Issue Dt:
02/26/2008
Application #:
11679873
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
10/18/2007
Title:
BORDERLESS CONTACT STRUCTURES
81
Patent #:
NONE
Issue Dt:
Application #:
11679971
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
08/28/2008
Title:
BIPOLAR TRANSISTOR USING SELECTIVE DIELECTRIC DEPOSITION AND METHODS FOR FABRICATION THEREOF
82
Patent #:
Issue Dt:
03/31/2009
Application #:
11680003
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
08/28/2008
Title:
METHODS AND APPARATUS FOR ASSESSING HEALTH OF MEMORY UTILIZATION OF A PROGRAM
83
Patent #:
Issue Dt:
02/23/2010
Application #:
11680081
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
08/28/2008
Title:
INTEGRATION CIRCUITS FOR REDUCING ELECTROMIGRATION EFFECT
84
Patent #:
NONE
Issue Dt:
Application #:
11680108
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
08/28/2008
Title:
STRAINED METAL GATE STRUCTURE FOR CMOS DEVICES WITH IMPROVED CHANNEL MOBILITY AND METHODS OF FORMING THE SAME
85
Patent #:
Issue Dt:
08/31/2010
Application #:
11680131
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
08/28/2008
Title:
ELECTRONIC FUSES IN SEMICONDUCTOR INTEGRATED CIRCUITS
86
Patent #:
Issue Dt:
02/22/2011
Application #:
11680163
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
08/28/2008
Title:
BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION
87
Patent #:
Issue Dt:
04/20/2010
Application #:
11680204
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
08/28/2008
Title:
SIDEWALL IMAGE TRANSFER PROCESSES FOR FORMING MULTIPLE LINE-WIDTHS
88
Patent #:
Issue Dt:
08/27/2013
Application #:
11680221
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
08/28/2008
Title:
FINFET WITH REDUCED GATE TO FIN OVERLAY SENSITIVITY
89
Patent #:
Issue Dt:
11/25/2008
Application #:
11680371
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
07/05/2007
Title:
DYNAMIC MEMORY ALLOCATION BETWEEN INBOUND AND OUTBOUND BUFFERS IN A PROTOCOL HANDLER
90
Patent #:
Issue Dt:
02/09/2010
Application #:
11680695
Filing Dt:
03/01/2007
Publication #:
Pub Dt:
09/04/2008
Title:
DATA BUS BANDWIDTH SCHEDULING IN AN FBDIMM MEMORY SYSTEM OPERATING IN VARIABLE LATENCY MODE
91
Patent #:
Issue Dt:
12/02/2008
Application #:
11681454
Filing Dt:
03/02/2007
Publication #:
Pub Dt:
06/28/2007
Title:
METHOD OF FORMING PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL
92
Patent #:
Issue Dt:
12/23/2008
Application #:
11681994
Filing Dt:
03/05/2007
Publication #:
Pub Dt:
09/11/2008
Title:
METHOD AND STRUCTURE TO IMPROVE THERMAL DISSIPATION FROM SEMICONDUCTOR DEVICES
93
Patent #:
NONE
Issue Dt:
Application #:
11682347
Filing Dt:
03/06/2007
Publication #:
Pub Dt:
09/11/2008
Title:
PROTECTION OF POLYMER SURFACES DURING MICRO-FABRICATION
94
Patent #:
Issue Dt:
08/17/2010
Application #:
11682403
Filing Dt:
03/06/2007
Publication #:
Pub Dt:
09/11/2008
Title:
DEFECT-FREE HYBRID ORIENTATION TECHNOLOGY FOR SEMICONDUCTOR DEVICES
95
Patent #:
Issue Dt:
08/05/2008
Application #:
11682542
Filing Dt:
03/06/2007
Title:
PULSED RING OSCILLATOR CIRCUIT FOR STORAGE CELL READ TIMING EVALUATION
96
Patent #:
Issue Dt:
05/03/2011
Application #:
11682554
Filing Dt:
03/06/2007
Publication #:
Pub Dt:
09/11/2008
Title:
ENHANCED TRANSISTOR PERFORMANCE BY NON-CONFORMAL STRESSED LAYERS
97
Patent #:
Issue Dt:
03/03/2009
Application #:
11682581
Filing Dt:
03/06/2007
Publication #:
Pub Dt:
06/28/2007
Title:
PLATING SEED LAYER INCLUDING AN OXYGEN/NITROGEN TRANSITION REGION FOR BARRIER ENHANCEMENT
98
Patent #:
Issue Dt:
02/10/2009
Application #:
11682638
Filing Dt:
03/06/2007
Publication #:
Pub Dt:
09/11/2008
Title:
METHOD FOR PREPARING 2-DIMENSIONAL SEMICONDUCTOR DEVICES FOR INTEGRATION IN A THIRD DIMENSION
99
Patent #:
Issue Dt:
08/10/2010
Application #:
11683058
Filing Dt:
03/07/2007
Publication #:
Pub Dt:
09/11/2008
Title:
STRUCTURE AND METHOD OF MAPPING SIGNAL INTENSITY TO SURFACE VOLTAGE FOR INTEGRATED CIRCUIT INSPECTION
100
Patent #:
Issue Dt:
03/09/2010
Application #:
11683068
Filing Dt:
03/07/2007
Publication #:
Pub Dt:
09/11/2008
Title:
METHOD OF MANUFACTURING AN ELECTRICAL ANTIFUSE
Assignor
1
Exec Dt:
06/29/2015
Assignee
1
2070 ROUTE 52
HOPEWELL JUNCTION, NEW YORK 12533
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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