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|
Patent #:
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|
Issue Dt:
|
10/28/2008
|
Application #:
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11657154
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Filing Dt:
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01/24/2007
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Publication #:
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|
Pub Dt:
|
05/31/2007
| | | | |
Title:
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METHOD OF APPLYING STRESSES TO PFET AND NFET TRANSISTOR CHANNELS FOR IMPROVED PERFORMANCE
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Patent #:
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Issue Dt:
|
01/13/2009
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Application #:
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11668097
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Filing Dt:
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01/29/2007
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Publication #:
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Pub Dt:
|
07/31/2008
| | | | |
Title:
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INTEGRATED HEAT SPREADER AND EXCHANGER
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Patent #:
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|
Issue Dt:
|
12/09/2008
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Application #:
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11668224
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Filing Dt:
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01/29/2007
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Publication #:
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|
Pub Dt:
|
07/31/2008
| | | | |
Title:
|
FABRICATION OF PHASE CHANGE MEMORY ELEMENT WITH PHASE-CHANGE ELECTRODES USING CONFORMAL DEPOSITION
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Patent #:
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Issue Dt:
|
03/22/2011
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Application #:
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11668542
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Filing Dt:
|
01/30/2007
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Publication #:
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Pub Dt:
|
07/31/2008
| | | | |
Title:
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PRINT EVENTS IN THE SIMULATION OF A DIGITAL SYSTEM
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|
Patent #:
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|
Issue Dt:
|
02/24/2009
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Application #:
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11668545
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Filing Dt:
|
01/30/2007
|
Publication #:
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|
Pub Dt:
|
07/31/2008
| | | | |
Title:
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TECHNIQUES FOR IMPROVING WRITE STABILITY OF MEMORY WITH DECOUPLED READ AND WRITE BIT LINES
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Patent #:
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Issue Dt:
|
06/28/2011
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Application #:
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11668717
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Filing Dt:
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01/30/2007
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Publication #:
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Pub Dt:
|
07/31/2008
| | | | |
Title:
|
CONTACT FORMING METHOD AND RELATED SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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09/06/2011
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Application #:
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11668731
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Filing Dt:
|
01/30/2007
|
Publication #:
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|
Pub Dt:
|
07/31/2008
| | | | |
Title:
|
METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR PRODUCT RANDOMIZATION AND ANALYSIS IN A MANUFACTURING ENVIRONMENT
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Patent #:
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Issue Dt:
|
06/23/2009
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Application #:
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11668790
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Filing Dt:
|
01/30/2007
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Publication #:
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|
Pub Dt:
|
05/31/2007
| | | | |
Title:
|
STRESS ENGINEERING USING DUAL PAD NITRIDE WITH SELECTIVE SOI DEVICE ARCHITECTURE
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|
Patent #:
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Issue Dt:
|
09/14/2010
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Application #:
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11669158
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Filing Dt:
|
01/31/2007
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Publication #:
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Pub Dt:
|
07/31/2008
| | | | |
Title:
|
METHOD AND SYSTEM FOR DESIGN AND MODELING OF TRANSMISSION LINES
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|
Patent #:
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|
Issue Dt:
|
08/26/2008
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Application #:
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11669175
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Filing Dt:
|
01/31/2007
|
Publication #:
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|
Pub Dt:
|
07/31/2008
| | | | |
Title:
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PELLICLE FILM OPTIMIZED FOR IMMERSION LITHOGRAPHY SYSTEMS WITH NA>1
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|
Patent #:
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Issue Dt:
|
05/31/2011
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Application #:
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11669179
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Filing Dt:
|
01/31/2007
|
Publication #:
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Pub Dt:
|
07/19/2007
| | | | |
Title:
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METHOD AND SYSTEM FOR INTELLIGENT AUTOMATED RETICLE MANAGMENT
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|
Patent #:
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|
Issue Dt:
|
10/05/2010
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Application #:
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11669214
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Filing Dt:
|
01/31/2007
|
Publication #:
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|
Pub Dt:
|
07/31/2008
| | | | |
Title:
|
METHOD AND SYSTEM FOR PAD CONDITIONING IN AN ECMP PROCESS
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|
|
Patent #:
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Issue Dt:
|
10/21/2008
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Application #:
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11669250
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Filing Dt:
|
01/31/2007
|
Publication #:
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|
Pub Dt:
|
07/31/2008
| | | | |
Title:
|
ELECTRONIC CIRCUIT FOR MEASUREMENT OF TRANSISTOR VARIABILITY AND THE LIKE
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
11669267
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Filing Dt:
|
01/31/2007
|
Publication #:
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|
Pub Dt:
|
07/31/2008
| | | | |
Title:
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WAVEGUIDE COUPLING DEVICES
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|
|
Patent #:
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|
Issue Dt:
|
09/07/2010
|
Application #:
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11669362
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Filing Dt:
|
01/31/2007
|
Publication #:
|
|
Pub Dt:
|
07/31/2008
| | | | |
Title:
|
ELECTRONIC COMPONENT FOR AN ELECTRONIC CARRIER SUBSTRATE
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|
|
Patent #:
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|
Issue Dt:
|
09/14/2010
|
Application #:
|
11669496
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Filing Dt:
|
01/31/2007
|
Publication #:
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|
Pub Dt:
|
07/31/2008
| | | | |
Title:
|
METHOD FOR FORMING AN INDIUM CAP LAYER
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|
|
Patent #:
|
|
Issue Dt:
|
01/01/2008
|
Application #:
|
11669598
|
Filing Dt:
|
01/31/2007
|
Publication #:
|
|
Pub Dt:
|
05/31/2007
| | | | |
Title:
|
STRUCTURE AND METHOD FOR MANUFACTURING STRAINED FINFET
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11669645
|
Filing Dt:
|
01/31/2007
|
Publication #:
|
|
Pub Dt:
|
07/31/2008
| | | | |
Title:
|
METHOD OF FORMING DISPOSABLE SPACERS FOR IMPROVED STRESSED NITRIDE FILM EFFECTIVENESS
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|
|
Patent #:
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|
Issue Dt:
|
04/28/2009
|
Application #:
|
11669902
|
Filing Dt:
|
01/31/2007
|
Publication #:
|
|
Pub Dt:
|
07/31/2008
| | | | |
Title:
|
STRAINED MOS DEVICES USING SOURCE/DRAIN EPITAXY
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|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
11670017
|
Filing Dt:
|
02/01/2007
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR USING DIRECT MEMORY ACCESS TO INITIALIZE A PROGRAMMABLE LOGIC DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
04/26/2011
|
Application #:
|
11670080
|
Filing Dt:
|
02/01/2007
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
REDUCED FRICTION MOLDS FOR INJECTION MOLDED SOLDER PROCESSING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11670262
|
Filing Dt:
|
02/01/2007
|
Publication #:
|
|
Pub Dt:
|
06/07/2007
| | | | |
Title:
|
ULTRA-THIN SILICON BRIDGING LAYERS OVERLYING AIR CAVITIES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11670537
|
Filing Dt:
|
02/02/2007
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH
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|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
11670621
|
Filing Dt:
|
02/02/2007
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
SYSTEMS AND METHODS FOR CONTROLLING POSITION OF CHARGED POLYMER INSIDE NANOPORE
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|
|
Patent #:
|
|
Issue Dt:
|
08/25/2009
|
Application #:
|
11670778
|
Filing Dt:
|
02/02/2007
|
Publication #:
|
|
Pub Dt:
|
05/31/2007
| | | | |
Title:
|
METHODS OF FORMING LOW-K DIELECTRIC LAYERS CONTAINING CARBON NANOSTRUCTURES
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11671113
|
Filing Dt:
|
02/05/2007
|
Publication #:
|
|
Pub Dt:
|
06/07/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR FABRICATING CMOS FIELD EFFECT TRANSISTORS
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|
|
Patent #:
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|
Issue Dt:
|
05/19/2009
|
Application #:
|
11671795
|
Filing Dt:
|
02/06/2007
|
Publication #:
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|
Pub Dt:
|
06/14/2007
| | | | |
Title:
|
METHOD AND STRUCTURE TO CREATE MULTIPLE DEVICE WIDTHS IN FINFET TECHNOLOGY IN BOTH BULK AND SOI
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|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
11672050
|
Filing Dt:
|
02/07/2007
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
SYSTEMATIC COMPLIANCE CHECKING OF A PROCESS
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|
|
Patent #:
|
|
Issue Dt:
|
05/18/2010
|
Application #:
|
11672059
|
Filing Dt:
|
02/07/2007
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
STRUCTURE AND METHOD FOR MONITORING AND CHARACTERIZING PATTERN DENSITY DEPENDENCE ON THERMAL ABSORPTION IN A SEMICONDUCTOR MANUFACTURING PROCESS
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|
|
Patent #:
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|
Issue Dt:
|
02/23/2010
|
Application #:
|
11672109
|
Filing Dt:
|
02/07/2007
|
Publication #:
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|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE INCLUDING DOPED SILICON CARBON LINER LAYER AND METHOD FOR FABRICATION THEREOF
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|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
11672110
|
Filing Dt:
|
02/07/2007
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
PROGRAMMABLE FUSE/NON-VOLATILE MEMORY STRUCTURES USING EXTERNALLY HEATED PHASE CHANGE MATERIAL
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|
|
Patent #:
|
|
Issue Dt:
|
01/25/2011
|
Application #:
|
11672217
|
Filing Dt:
|
02/07/2007
|
Publication #:
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|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
METHOD, SYSTEM, PROGRAM PRODUCT FOR BONDING TWO CIRCUITRY-INCLUDING SUBSTRATES AND RELATED STAGE
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|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11672251
|
Filing Dt:
|
02/07/2007
|
Publication #:
|
|
Pub Dt:
|
06/07/2007
| | | | |
Title:
|
SILICON-ON-INSULATOR (SOI) READ ONLY MEMORY (ROM) ARRAY AND METHOD OF MAKING A SOI ROM
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|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11672309
|
Filing Dt:
|
02/07/2007
|
Publication #:
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|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
METHODS AND APPARATUS FOR CALIBRATING OUTPUT VOLTAGE LEVELS ASSOCIATED WITH CURRENT-INTEGRATING SUMMING AMPLIFIER
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11672363
|
Filing Dt:
|
02/07/2007
|
Publication #:
|
|
Pub Dt:
|
06/07/2007
| | | | |
Title:
|
METHOD FOR ENHANCED UNI-DIRECTIONAL DIFFUSION OF METAL AND SUBSEQUENT SILICIDE FORMATION
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|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
11672527
|
Filing Dt:
|
02/08/2007
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
RANDOM TEST GENERATION USING AN OPTIMIZATION SOLVER
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|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
11672599
|
Filing Dt:
|
02/08/2007
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
03/31/2009
|
Application #:
|
11672737
|
Filing Dt:
|
02/08/2007
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
AUTOMATIC STATIC PHASE ERROR AND JITTER COMPENSATION IN PLL CIRCUITS
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|
|
Patent #:
|
|
Issue Dt:
|
03/23/2010
|
Application #:
|
11672973
|
Filing Dt:
|
02/09/2007
|
Publication #:
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|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR SHUTTING OFF DATA CAPTURE ACROSS ASYNCHRONOUS CLOCK DOMAINS DURING AT-SPEED TESTING
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11673128
|
Filing Dt:
|
02/09/2007
|
Publication #:
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|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
METHOD AND SYSTEM FOR PLASMA ETCHING HAVING IMPROVED ACROSS-WAFER ETCH UNIFORMITY
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|
|
Patent #:
|
|
Issue Dt:
|
06/09/2009
|
Application #:
|
11673276
|
Filing Dt:
|
02/09/2007
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
METHOD FOR INTEGRATING LINER FORMATION IN BACK END OF LINE PROCESSING
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|
|
Patent #:
|
|
Issue Dt:
|
10/06/2009
|
Application #:
|
11673298
|
Filing Dt:
|
02/09/2007
|
Publication #:
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|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
SYSTEM AND METHOD FOR GENERATING CONSTRAINT PRESERVING TESTCASES IN THE PRESENCE OF DEAD-END CONSTRAINTS
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|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
11673369
|
Filing Dt:
|
02/09/2007
|
Publication #:
|
|
Pub Dt:
|
06/07/2007
| | | | |
Title:
|
NON-DESTRUCTIVE EVALUATION OF MICROSTRUCTURE AND INTERFACE ROUGHNESS OF ELECTRICALLY CONDUCTING LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS IN DEEP SUB-MICRON REGIME
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|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
11673611
|
Filing Dt:
|
02/12/2007
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
FORMATION OF MASKS/RETICLES HAVING DUMMY FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
11673824
|
Filing Dt:
|
02/12/2007
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
SEMICONDUCTOR DEVICE STRESS MODELING METHODOLOGY
|
|
|
Patent #:
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|
Issue Dt:
|
11/03/2009
|
Application #:
|
11673901
|
Filing Dt:
|
02/12/2007
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-K GATE DIELECTRIC STACKS
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|
|
Patent #:
|
|
Issue Dt:
|
09/02/2008
|
Application #:
|
11674292
|
Filing Dt:
|
02/13/2007
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
SINGLE-ENDED MEMORY CELL WITH IMPROVED READ STABILITY AND MEMORY USING THE CELL
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11674453
|
Filing Dt:
|
02/13/2007
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
SELF-ALIGNED EPITAXIAL GROWTH OF SEMICONDUCTOR NANOWIRES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2011
|
Application #:
|
11674598
|
Filing Dt:
|
02/13/2007
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
METHODOLOGIES AND ANALYTICS TOOLS FOR IDENTIFYING WHITE SPACE OPPORTUNITIES IN A GIVEN INDUSTRY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11674775
|
Filing Dt:
|
02/14/2007
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
APPARRATUS AND METHOD FOR UNIVERSAL PROGRAMMABLE ERROR DETECTION AND REAL TIME ERROR DETECTION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11675296
|
Filing Dt:
|
02/15/2007
|
Publication #:
|
|
Pub Dt:
|
08/21/2008
| | | | |
Title:
|
STRUCTURE FOR METAL CAP APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
11675445
|
Filing Dt:
|
02/15/2007
|
Publication #:
|
|
Pub Dt:
|
08/21/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR MANUFACTURING ELECTRONIC INTEGRATED CIRCUIT CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2010
|
Application #:
|
11675705
|
Filing Dt:
|
02/16/2007
|
Publication #:
|
|
Pub Dt:
|
08/21/2008
| | | | |
Title:
|
INTERCONNECT STRUCTURE WITH BI-LAYER METAL CAP
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2008
|
Application #:
|
11676030
|
Filing Dt:
|
02/16/2007
|
Publication #:
|
|
Pub Dt:
|
06/21/2007
| | | | |
Title:
|
SELF-ALIGNED PLANAR DOUBLE-GATE TRANSISTOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
11676447
|
Filing Dt:
|
02/19/2007
|
Publication #:
|
|
Pub Dt:
|
06/21/2007
| | | | |
Title:
|
RECOVERY OF HYDROPHOBICITY OF LOW-K AND ULTRA LOW-K ORGANOSILICATE FILMS USED AS INTER METAL DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
11676522
|
Filing Dt:
|
02/20/2007
|
Publication #:
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|
Pub Dt:
|
08/21/2008
| | | | |
Title:
|
BEOL INTERCONNECT STRUCTURES WITH IMPROVED RESISTANCE TO STRESS
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|
|
Patent #:
|
|
Issue Dt:
|
11/01/2011
|
Application #:
|
11676674
|
Filing Dt:
|
02/20/2007
|
Publication #:
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|
Pub Dt:
|
06/21/2007
| | | | |
Title:
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SYSTEM AND METHOD FOR PLASMA INDUCED MODIFICATION AND IMPROVEMENT OF CRITICAL DIMENSION UNIFORMITY
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|
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Patent #:
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Issue Dt:
|
01/04/2011
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Application #:
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11676853
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Filing Dt:
|
02/20/2007
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Publication #:
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Pub Dt:
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08/21/2008
| | | | |
Title:
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METHOD AND SYSTEM FOR DETECTING SYNCHRONIZATION ERRORS IN PROGRAMS
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Patent #:
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Issue Dt:
|
10/06/2009
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Application #:
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11677100
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Filing Dt:
|
02/21/2007
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Publication #:
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Pub Dt:
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08/21/2008
| | | | |
Title:
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METHOD TO REMOVE BEOL SACRIFICIAL MATERIALS AND CHEMICAL RESIDUES BY IRRADIATION
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Patent #:
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Issue Dt:
|
08/24/2010
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Application #:
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11677207
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Filing Dt:
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02/21/2007
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Publication #:
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Pub Dt:
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08/21/2008
| | | | |
Title:
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SEMICONDUCTOR STRUCTURE INCLUDING GATE ELECTRODE HAVING LATERALLY VARIABLE WORK FUNCTION
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Patent #:
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Issue Dt:
|
02/23/2010
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Application #:
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11677598
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Filing Dt:
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02/22/2007
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Publication #:
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Pub Dt:
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08/28/2008
| | | | |
Title:
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METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR
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Patent #:
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Issue Dt:
|
03/20/2012
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Application #:
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11677652
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Filing Dt:
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02/22/2007
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Publication #:
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Pub Dt:
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08/28/2008
| | | | |
Title:
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SEQUENTIAL ENCODING FOR RELATIONAL ANALYSIS (SERA) OF A SOFTWARE MODEL
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Patent #:
|
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Issue Dt:
|
06/23/2009
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Application #:
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11677666
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Filing Dt:
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02/22/2007
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Publication #:
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Pub Dt:
|
06/21/2007
| | | | |
Title:
|
INCORPORATION OF UNCERTAINTY INFORMATION IN MODELING A CHARACTERISTIC OF A DEVICE
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Patent #:
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|
Issue Dt:
|
11/03/2009
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Application #:
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11677776
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Filing Dt:
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02/22/2007
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Publication #:
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Pub Dt:
|
06/28/2007
| | | | |
Title:
|
BIPOLAR TRANSISTOR WITH ISOLATION AND DIRECT CONTACTS
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|
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Patent #:
|
|
Issue Dt:
|
04/20/2010
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Application #:
|
11678069
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Filing Dt:
|
02/23/2007
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Publication #:
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Pub Dt:
|
08/28/2008
| | | | |
Title:
|
STICHED IC LAYOUT METHODS, SYSTEMS AND PROGRAM PRODUCT
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|
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Patent #:
|
|
Issue Dt:
|
10/26/2010
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Application #:
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11678089
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Filing Dt:
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02/23/2007
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Publication #:
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|
Pub Dt:
|
09/25/2008
| | | | |
Title:
|
RECYCLING OF ELECTROCHEMICAL-MECHANICAL PLANARIZATION (ECMP) SLURRIES/ELECTROLYTES
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|
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Patent #:
|
|
Issue Dt:
|
04/12/2011
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Application #:
|
11678163
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Filing Dt:
|
02/23/2007
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Publication #:
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|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
VARIABLE FILL AND CHEESE FOR MITIGATION OF BEOL TOPOGRAPHY
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|
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Patent #:
|
|
Issue Dt:
|
02/01/2011
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Application #:
|
11678338
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Filing Dt:
|
02/23/2007
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Publication #:
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Pub Dt:
|
08/28/2008
| | | | |
Title:
|
LOW-TEMPERATURE ELECTRICALLY ACTIVATED GATE ELECTRODE AND METHOD OF FABRICATING SAME
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|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
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Application #:
|
11679171
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Filing Dt:
|
02/26/2007
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Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
ESTIMATION OF PROCESS VARIATION IMPACT OF SLACK IN MULTI-CORNER PATH-BASED STATIC TIMING ANALYSIS
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11679192
|
Filing Dt:
|
02/27/2007
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Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
Device, System and Method of Verification of Address Translation Mechanisms
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11679226
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Filing Dt:
|
02/27/2007
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Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
REWORKABLE CHIP STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
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Application #:
|
11679247
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Filing Dt:
|
02/27/2007
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Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
METHOD OF REMOVING GRAPHITIC AND/OR FLUORINATED ORGANIC LAYERS FROM THE SURFACE OF A CHIP PASSIVATION LAYER HAVING SI-CONTAINING COMPOUNDS
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11679308
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Filing Dt:
|
02/27/2007
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Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11679407
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Filing Dt:
|
02/27/2007
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Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2010
|
Application #:
|
11679483
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Filing Dt:
|
02/27/2007
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Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
STRUCTURE INCLUDING VIA HAVING REFRACTORY METAL COLLAR AT COPPER WIRE AND DIELECTRIC LAYER LINER-LESS INTERFACE AND RELATED METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
11679785
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Filing Dt:
|
02/27/2007
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Title:
|
RECTIFYING ELEMENT FOR A CROSSPOINT BASED MEMORY ARRAY ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
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Application #:
|
11679831
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Filing Dt:
|
02/27/2007
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Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
PARAMETER ORDERING FOR MULTI-CORNER STATIC TIMING ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2008
|
Application #:
|
11679862
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Filing Dt:
|
02/28/2007
|
Title:
|
FORMATION OF SPACERS FOR FINFETS (FIELD EFFECT TRANSISTORS)
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
11679869
|
Filing Dt:
|
02/28/2007
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Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
RADIATION HARDENED FINFET
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
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Application #:
|
11679873
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Filing Dt:
|
02/28/2007
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
BORDERLESS CONTACT STRUCTURES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11679971
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Filing Dt:
|
02/28/2007
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Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
BIPOLAR TRANSISTOR USING SELECTIVE DIELECTRIC DEPOSITION AND METHODS FOR FABRICATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2009
|
Application #:
|
11680003
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Filing Dt:
|
02/28/2007
|
Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
METHODS AND APPARATUS FOR ASSESSING HEALTH OF MEMORY UTILIZATION OF A PROGRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2010
|
Application #:
|
11680081
|
Filing Dt:
|
02/28/2007
|
Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
INTEGRATION CIRCUITS FOR REDUCING ELECTROMIGRATION EFFECT
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11680108
|
Filing Dt:
|
02/28/2007
|
Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
STRAINED METAL GATE STRUCTURE FOR CMOS DEVICES WITH IMPROVED CHANNEL MOBILITY AND METHODS OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
11680131
|
Filing Dt:
|
02/28/2007
|
Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
ELECTRONIC FUSES IN SEMICONDUCTOR INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
11680163
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Filing Dt:
|
02/28/2007
|
Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
11680204
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Filing Dt:
|
02/28/2007
|
Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
SIDEWALL IMAGE TRANSFER PROCESSES FOR FORMING MULTIPLE LINE-WIDTHS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
11680221
|
Filing Dt:
|
02/28/2007
|
Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
FINFET WITH REDUCED GATE TO FIN OVERLAY SENSITIVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
11680371
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Filing Dt:
|
02/28/2007
|
Publication #:
|
|
Pub Dt:
|
07/05/2007
| | | | |
Title:
|
DYNAMIC MEMORY ALLOCATION BETWEEN INBOUND AND OUTBOUND BUFFERS IN A PROTOCOL HANDLER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
11680695
|
Filing Dt:
|
03/01/2007
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
Title:
|
DATA BUS BANDWIDTH SCHEDULING IN AN FBDIMM MEMORY SYSTEM OPERATING IN VARIABLE LATENCY MODE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
11681454
|
Filing Dt:
|
03/02/2007
|
Publication #:
|
|
Pub Dt:
|
06/28/2007
| | | | |
Title:
|
METHOD OF FORMING PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2008
|
Application #:
|
11681994
|
Filing Dt:
|
03/05/2007
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
METHOD AND STRUCTURE TO IMPROVE THERMAL DISSIPATION FROM SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11682347
|
Filing Dt:
|
03/06/2007
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
PROTECTION OF POLYMER SURFACES DURING MICRO-FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
11682403
|
Filing Dt:
|
03/06/2007
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
DEFECT-FREE HYBRID ORIENTATION TECHNOLOGY FOR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
11682542
|
Filing Dt:
|
03/06/2007
|
Title:
|
PULSED RING OSCILLATOR CIRCUIT FOR STORAGE CELL READ TIMING EVALUATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
11682554
|
Filing Dt:
|
03/06/2007
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
ENHANCED TRANSISTOR PERFORMANCE BY NON-CONFORMAL STRESSED LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
11682581
|
Filing Dt:
|
03/06/2007
|
Publication #:
|
|
Pub Dt:
|
06/28/2007
| | | | |
Title:
|
PLATING SEED LAYER INCLUDING AN OXYGEN/NITROGEN TRANSITION REGION FOR BARRIER ENHANCEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11682638
|
Filing Dt:
|
03/06/2007
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
METHOD FOR PREPARING 2-DIMENSIONAL SEMICONDUCTOR DEVICES FOR INTEGRATION IN A THIRD DIMENSION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
11683058
|
Filing Dt:
|
03/07/2007
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
STRUCTURE AND METHOD OF MAPPING SIGNAL INTENSITY TO SURFACE VOLTAGE FOR INTEGRATED CIRCUIT INSPECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11683068
|
Filing Dt:
|
03/07/2007
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
METHOD OF MANUFACTURING AN ELECTRICAL ANTIFUSE
|
|