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07/18/2002
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07/18/2002
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09/18/2003
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07/25/2002
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07/25/2002
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07/25/2002
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07/25/2002
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07/25/2002
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08/01/2002
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10/02/2003
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08/15/2002
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04/08/2002
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Publication #:
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Pub Dt:
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08/22/2002
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Title:
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A CAPACITOR WITH NOBLE METAL PATTERN
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10117145
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Filing Dt:
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04/05/2002
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Publication #:
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Pub Dt:
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12/12/2002
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Title:
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METHOD AND APPARATUS FOR PLANARIZING A MICROELECTRONIC SUBSTRATE WITH A TILTED PLANARIZING SURFACE
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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10117244
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Filing Dt:
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04/05/2002
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Publication #:
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Pub Dt:
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08/15/2002
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Title:
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NONLOT BASED METHOD FOR ASSEMBLING INTEGRATED CIRCUIT DEVICES
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Patent #:
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Issue Dt:
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01/18/2005
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Application #:
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10117551
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Filing Dt:
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04/04/2002
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Publication #:
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Pub Dt:
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10/09/2003
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Title:
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MICROELECTRONIC PACKAGE WITH REDUCED UNDERFILL AND METHODS FOR FORMING SUCH PACKAGES
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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10117738
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Filing Dt:
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04/05/2002
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Publication #:
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Pub Dt:
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09/26/2002
| | | | |
Title:
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METHOD AND APPARATUS FOR PLANARIZING A MICROELECTRONIC SUBSTRATE WITH A TILTED PLANARIZING SURFACE
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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10118281
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Filing Dt:
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04/08/2002
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Publication #:
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Pub Dt:
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10/09/2003
| | | | |
Title:
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DISTRIBUTED FIFO IN SYNCHRONOUS MEMORY
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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10118349
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Filing Dt:
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04/08/2002
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Publication #:
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Pub Dt:
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10/09/2003
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Title:
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METHODS AND APPARATUS FOR DETERMINING A FLOATING-POINT EXPONENT ASSOCIATED WITH AN UNDERFLOW CONDITION OR AN OVERFLOW CONDITION
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Patent #:
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Issue Dt:
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04/04/2006
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Application #:
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10118350
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Filing Dt:
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04/09/2002
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Publication #:
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Pub Dt:
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10/09/2003
| | | | |
Title:
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METHOD OF FORMING SPATIAL REGIONS OF A SECOND MATERIAL IN A FIRST MATERIAL
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Patent #:
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Issue Dt:
|
03/11/2003
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Application #:
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10118365
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Filing Dt:
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04/08/2002
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Publication #:
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Pub Dt:
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08/22/2002
| | | | |
Title:
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METHODS FOR TRANSVERSE HYBRID LOC PACKAGE
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Patent #:
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Issue Dt:
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02/24/2009
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Application #:
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10118393
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Filing Dt:
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04/05/2002
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Publication #:
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Pub Dt:
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10/09/2003
| | | | |
Title:
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METHODS OF FORMING SEMICONDUCTOR-ON-INSULATOR CONSTRUCTIONS
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Patent #:
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Issue Dt:
|
08/31/2004
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Application #:
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10118569
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Filing Dt:
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04/08/2002
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Publication #:
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Pub Dt:
|
10/09/2003
| | | | |
Title:
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PROCESS FOR MAKING A SILICON-ON-INSULATOR LEDGE BY IMPLANTING IONS FROM SILICON SOURCE
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Patent #:
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Issue Dt:
|
01/09/2007
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Application #:
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10118580
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Filing Dt:
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04/08/2002
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Publication #:
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Pub Dt:
|
03/13/2003
| | | | |
Title:
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BOW CONTROL IN AN ELECTRONIC PACKAGE
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Patent #:
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Issue Dt:
|
07/08/2003
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Application #:
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10118582
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Filing Dt:
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04/08/2002
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Publication #:
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Pub Dt:
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08/15/2002
| | | | |
Title:
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COMPUTER HOUSING WITH EXPANSION BAY COVER AND METHODS FOR OPERATING EXPANSION BAY COVERS
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Patent #:
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Issue Dt:
|
12/02/2003
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Application #:
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10118660
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Filing Dt:
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04/08/2002
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Publication #:
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Pub Dt:
|
12/12/2002
| | | | |
Title:
|
READING CIRCUIT AND METHOD FOR A MULTILEVEL NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
|
05/20/2003
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Application #:
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10118844
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Filing Dt:
|
04/09/2002
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Publication #:
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Pub Dt:
|
08/15/2002
| | | | |
Title:
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REMOTE SEMICONDUCTOR MICROSCOPY
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10118891
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Filing Dt:
|
04/10/2002
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Publication #:
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Pub Dt:
|
10/16/2003
| | | | |
Title:
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WORDLINE DRIVEN METHOD FOR SENSING DATA IN A RESISTIVE MEMORY ARRAY
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Patent #:
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Issue Dt:
|
01/13/2004
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Application #:
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10118947
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Filing Dt:
|
04/10/2002
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Publication #:
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Pub Dt:
|
08/15/2002
| | | | |
Title:
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METHOD OF FORMING A METAL TO POLYSILICON CONTACT IN OXYGEN ENVIRONMENT
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Patent #:
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Issue Dt:
|
01/27/2004
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Application #:
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10119461
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Filing Dt:
|
04/10/2002
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Publication #:
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Pub Dt:
|
08/15/2002
| | | | |
Title:
|
METHOD OF USING A SEMICONDUCTOR CHIP PACKAGE
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Patent #:
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Issue Dt:
|
09/07/2004
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Application #:
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10119523
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Filing Dt:
|
04/09/2002
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Publication #:
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Pub Dt:
|
12/19/2002
| | | | |
Title:
|
METHOD FOR PROGRAMMING NONVOLATILE MEMORY CELLS WITH PROGRAM AND VERIFY ALGORITHM USING A STAIRCASE VOLTAGE WITH VARYING STEP AMPLITUDE
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Patent #:
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Issue Dt:
|
01/04/2005
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Application #:
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10119550
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Filing Dt:
|
04/09/2002
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Publication #:
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Pub Dt:
|
10/09/2003
| | | | |
Title:
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METHOD AND SYSTEM FOR DYNAMICALLY OPERATING MEMORY IN A POWER-SAVING ERROR CORRECTION MODE
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Patent #:
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Issue Dt:
|
12/09/2003
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Application #:
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10119655
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Filing Dt:
|
04/10/2002
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Publication #:
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Pub Dt:
|
08/15/2002
| | | | |
Title:
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METHOD AND APPARATUS FOR PACKAGING FLIP CHIP BARE DIE ON PRINTED CIRCUIT BOARDS
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Patent #:
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Issue Dt:
|
09/07/2004
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Application #:
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10120169
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Filing Dt:
|
04/10/2002
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Publication #:
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Pub Dt:
|
10/16/2003
| | | | |
Title:
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SOLDER MASKS FOR USE ON CARRIER SUBSTRATES, CARRIER SUBSTRATES AND SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING SUCH SOLDER MASKS, AND METHODS
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Patent #:
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Issue Dt:
|
02/03/2004
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Application #:
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10121085
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Filing Dt:
|
04/10/2002
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Publication #:
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Pub Dt:
|
10/16/2003
| | | | |
Title:
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METHOD AND SYSTEM FOR WRITING DATA IN AN MRAM MEMORY DEVICE
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Patent #:
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Issue Dt:
|
10/21/2003
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Application #:
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10121218
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Filing Dt:
|
04/11/2002
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Publication #:
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Pub Dt:
|
08/22/2002
| | | | |
Title:
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STRESS REDUCTION FEATURE FOR LOC LEAD FRAME
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Patent #:
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Issue Dt:
|
04/06/2004
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Application #:
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10121265
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Filing Dt:
|
04/11/2002
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Publication #:
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|
Pub Dt:
|
10/03/2002
| | | | |
Title:
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METHODS EMPLOYING HYBRID ADHESIVE MATERIALS TO SECURE COMPONENTS OF SEMICONDUCTOR DEVICE ASSEMBLIES AND PACKAGES TO ONE ANOTHER AND ASSEMBLIES AND PACKAGES INCLUDING COMPONENTS SECURED TO ONE ANOTHER WITH SUCH HYBRID ADHESIVE MATERIALS
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Patent #:
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Issue Dt:
|
09/30/2003
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Application #:
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10121298
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Filing Dt:
|
04/11/2002
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Publication #:
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Pub Dt:
|
10/16/2003
| | | | |
Title:
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SEMICONDUCTOR CONSTRUCTIONS AND METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
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Patent #:
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Issue Dt:
|
09/02/2003
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Application #:
|
10121302
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Filing Dt:
|
04/11/2002
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Title:
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A METHOD OF REPLACING AT LEAST A PORTION OF A SEMICONDUCTOR SUBSTRATE DEPOSITION CHAMBER LINER
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Patent #:
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Issue Dt:
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01/25/2005
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Application #:
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10121320
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Filing Dt:
|
04/11/2002
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Publication #:
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Pub Dt:
|
10/16/2003
| | | | |
Title:
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DEPOSITION METHODS UTILIZING MICROWAVE EXCITATION, AND DEPOSITION APPARATUSES
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Patent #:
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Issue Dt:
|
06/01/2004
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Application #:
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10121341
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Filing Dt:
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04/11/2002
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Publication #:
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Pub Dt:
|
10/16/2003
| | | | |
Title:
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REACTIVE GASEOUS DEPOSITION PRECURSOR FEED APPARATUS
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Patent #:
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Issue Dt:
|
12/30/2003
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Application #:
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10121645
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Filing Dt:
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04/12/2002
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Publication #:
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Pub Dt:
|
08/15/2002
| | | | |
Title:
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METHOD OF DECONTAMINATING PROCESS CHAMBERS, METHODS OF REDUCING DEFECTS IN ANTI-REFLECTIVE COATINGS, AND RESULTING SEMICONDUCTOR STRUCTURES
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Patent #:
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Issue Dt:
|
11/11/2003
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Application #:
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10121694
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Filing Dt:
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04/15/2002
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Publication #:
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Pub Dt:
|
09/26/2002
| | | | |
Title:
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EFFICIENT FABRICATION PROCESS FOR DUAL WELL TYPE STRUCTURES
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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10121792
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Filing Dt:
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04/10/2002
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Publication #:
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Pub Dt:
|
10/16/2003
| | | | |
Title:
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METHOD OF MANUFACTURE OF PROGRAMMABLE CONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10121826
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Filing Dt:
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04/11/2002
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Publication #:
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Pub Dt:
|
08/15/2002
| | | | |
Title:
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METHOD AND APPARATUS FOR UNIFORMLY PLANARIZING A MICROELECTRONIC SUBSTRATE
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Patent #:
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Issue Dt:
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07/03/2007
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10122381
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Filing Dt:
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04/16/2002
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Publication #:
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Pub Dt:
|
11/06/2003
| | | | |
Title:
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APPARATUS AND METHOD TO FACILITATE HIERARCHICAL NETLIST CHECKING
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Patent #:
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Issue Dt:
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04/05/2005
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Application #:
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10123050
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Filing Dt:
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04/12/2002
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Publication #:
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Pub Dt:
|
10/16/2003
| | | | |
Title:
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LARGE SCALE SYNTHESIS OF GERMANIUM SELENIDE GLASS AND GERMANIUM SELENIDE GLASS COMPOUNDS
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Patent #:
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Issue Dt:
|
03/25/2003
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Application #:
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10123328
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Filing Dt:
|
04/15/2002
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Title:
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METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS WITH TERMINAL CONTACTS HAVING ALTERNATE ELECTRICAL PATHS
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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10123579
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Filing Dt:
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04/15/2002
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Publication #:
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Pub Dt:
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10/17/2002
| | | | |
Title:
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METHOD OF MANUFACTURING A SINGLE ELECTRON RESISTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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10123580
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Filing Dt:
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04/15/2002
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Publication #:
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Pub Dt:
|
10/17/2002
| | | | |
Title:
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METHOD OF MANUFACTURING A SINGLE ELECTRON RESISTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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10/02/2007
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Application #:
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10123827
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Filing Dt:
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04/15/2002
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Publication #:
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Pub Dt:
|
10/16/2003
| | | | |
Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE HAVING ELECTRICALLY DISCONNECTED SOLDER BALLS FOR MOUNTING
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Patent #:
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Issue Dt:
|
04/27/2004
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Application #:
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10123874
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Filing Dt:
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04/16/2002
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Publication #:
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Pub Dt:
|
12/05/2002
| | | | |
Title:
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METHOD AND CIRCUIT FOR TIMING DYNAMIC READING OF A MEMORY CELL WITH CONTROL OF THE INTEGRATION TIME
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Patent #:
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Issue Dt:
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08/12/2008
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Application #:
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10124019
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Filing Dt:
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04/16/2002
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Publication #:
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Pub Dt:
|
02/27/2003
| | | | |
Title:
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VERTICAL TRANSISTOR WITH HORIZONTAL GATE LAYERS
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