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12/05/2002
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12/10/2002
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12/05/2002
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04/08/2003
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12/19/2002
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05/11/2004
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10/30/2003
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10/30/2003
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02/03/2004
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10/30/2003
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12/10/2002
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08/22/2002
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02/10/2004
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01/22/2004
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09/12/2002
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08/29/2002
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08/29/2002
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10/30/2003
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08/29/2002
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04/20/2004
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12/19/2002
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09/06/2005
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04/26/2002
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02/27/2003
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10/30/2003
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03/01/2005
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10/30/2003
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05/20/2008
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10/30/2003
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09/12/2006
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04/25/2002
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10/30/2003
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04/29/2002
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09/12/2002
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08/10/2004
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05/01/2002
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11/07/2002
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08/31/2004
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04/30/2002
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10/30/2003
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02/17/2004
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05/01/2002
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10/24/2002
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10/16/2003
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09/27/2005
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04/30/2002
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03/06/2003
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04/30/2002
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09/05/2002
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11/06/2003
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03/30/2004
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09/19/2002
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10/04/2005
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11/06/2003
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11/06/2003
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11/06/2003
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09/12/2002
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12/26/2006
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11/06/2003
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05/13/2003
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09/12/2002
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01/27/2004
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09/12/2002
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04/17/2003
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10/05/2004
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09/12/2002
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06/22/2004
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11/06/2003
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11/13/2003
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11/13/2003
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11/20/2003
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11/20/2003
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09/25/2003
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11/20/2003
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11/20/2003
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09/12/2002
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HEAT SINK CHIP PACKAGE
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11/20/2003
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05/24/2005
|
Application #:
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10150144
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Filing Dt:
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05/17/2002
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Title:
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METHOD AND SYSTEM FOR FABRICATING SEMICONDUCTOR COMPONENTS USING WAFER LEVEL CONTACT PRINTING
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Patent #:
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Issue Dt:
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09/26/2006
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Application #:
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10150516
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Filing Dt:
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05/17/2002
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Publication #:
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Pub Dt:
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09/04/2003
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Title:
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SEMICONDUCTOR DIE PACKAGES WITH RECESSED INTERCONNECTING STRUCTURES AND METHODS FOR ASSEMBLING THE SAME
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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10150622
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Filing Dt:
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05/17/2002
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Publication #:
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Pub Dt:
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11/20/2003
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Title:
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DOUBLE-SIDED CAPACITOR STRUCTURE FOR A SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING THE STRUCTURE
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Patent #:
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Issue Dt:
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01/26/2010
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Application #:
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10150623
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Filing Dt:
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05/17/2002
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Publication #:
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Pub Dt:
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11/20/2003
| | | | |
Title:
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METHODS OF FORMING PROGRAMMABLE MEMORY DEVICES
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Patent #:
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Issue Dt:
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01/09/2007
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Application #:
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10150653
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Filing Dt:
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05/17/2002
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Publication #:
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Pub Dt:
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09/04/2003
| | | | |
Title:
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FLIP CHIP PACKAGING USING RECESSED INTERPOSER TERMINALS
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Patent #:
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Issue Dt:
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12/05/2006
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Application #:
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10150893
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Filing Dt:
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05/17/2002
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Publication #:
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Pub Dt:
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09/04/2003
| | | | |
Title:
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INTERPOSER CONFIGURED TO REDUCE THE PROFILES OF SEMICONDUCTOR DEVICE ASSEMBLIES AND PACKAGES INCLUDING THE SAME AND METHODS
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Patent #:
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Issue Dt:
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03/25/2008
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Application #:
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10150901
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Filing Dt:
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05/17/2002
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Publication #:
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Pub Dt:
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09/04/2003
| | | | |
Title:
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METHODS FOR ASSEMBLY AND PACKAGING OF FLIP CHIP CONFIGURED DICE WITH INTERPOSER
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Patent #:
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Issue Dt:
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12/13/2005
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Application #:
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10150902
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Filing Dt:
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05/17/2002
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Publication #:
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Pub Dt:
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09/04/2003
| | | | |
Title:
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METHOD AND APPARATUS FOR DIELECTRIC FILLING OF FLIP CHIP ON INTERPOSER ASSEMBLY
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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10152649
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Filing Dt:
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05/20/2002
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Publication #:
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Pub Dt:
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09/26/2002
| | | | |
Title:
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FLASH MEMORY WITH ULTRA THIN VERTICAL BODY TRANSISTORS
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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10152842
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Filing Dt:
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05/23/2002
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Publication #:
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Pub Dt:
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09/12/2002
| | | | |
Title:
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TRENCH DRAM CELL WITH VERTICAL DEVICE AND BURIED WORD LINES
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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10152969
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Filing Dt:
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05/20/2002
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Title:
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INCREASING THE MEMORY PERFORMANCE OF FLASH MEMORY DEVICES BY WRITING SECTORS SIMULTANEOUSLY TO MULTIPLE FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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10153830
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Filing Dt:
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05/21/2002
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Title:
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SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY
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Patent #:
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Issue Dt:
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07/22/2003
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Application #:
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10154019
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Filing Dt:
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05/23/2002
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Publication #:
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Pub Dt:
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01/02/2003
| | | | |
Title:
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CHARGING A CAPACITANCE OF A MEMORY CELL AND CHARGER
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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10154549
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Filing Dt:
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05/24/2002
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Title:
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METHOD OF FORMING A STACK OF PACKAGED MEMORY DICE
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Patent #:
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Issue Dt:
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12/28/2004
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Application #:
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10154640
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Filing Dt:
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05/24/2002
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Publication #:
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Pub Dt:
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11/27/2003
| | | | |
Title:
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METHODS FOR MOLDING A SEMICONDUCTOR DIE PACKAGE WITH ENHANCED THERMAL CONDUCTIVITY
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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10155132
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Filing Dt:
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05/23/2002
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Publication #:
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Pub Dt:
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10/03/2002
| | | | |
Title:
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BI-LEVEL DIGIT LINE ARCHITECTURE FOR HIGH DENSITY DRAMS
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Patent #:
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Issue Dt:
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07/22/2003
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Application #:
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10155317
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Filing Dt:
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05/23/2002
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Publication #:
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Pub Dt:
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09/26/2002
| | | | |
Title:
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CONCAVE FACE WIRE BOND CAPILLARY AND METHOD
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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10155398
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Filing Dt:
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05/22/2002
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Publication #:
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Pub Dt:
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10/03/2002
| | | | |
Title:
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METHOD TO PREVENT INADVERTENT TEST MODE ENTRY
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Patent #:
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Issue Dt:
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01/04/2005
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Application #:
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10155547
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Filing Dt:
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05/24/2002
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Publication #:
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Pub Dt:
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11/27/2003
| | | | |
Title:
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APPARATUS AND METHODS FOR CONTROLLING GAS PULSING IN PROCESSES FOR DEPOSITING MATERIALS ONTO MICRO-DEVICE WORKPIECES
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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10155654
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Filing Dt:
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05/23/2002
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Publication #:
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Pub Dt:
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10/03/2002
| | | | |
Title:
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METHOD AND STENCIL FOR EXTRUDING MATERIAL ON A SUBSTRATE
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Patent #:
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Issue Dt:
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01/03/2006
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Application #:
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10155668
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Filing Dt:
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05/24/2002
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Publication #:
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Pub Dt:
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11/27/2003
| | | | |
Title:
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MEMORY DEVICE SEQUENCER AND METHOD SUPPORTING MULTIPLE MEMORY DEVICE CLOCK SPEEDS
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10156097
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Filing Dt:
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05/29/2002
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Publication #:
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Pub Dt:
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12/18/2003
| | | | |
Title:
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HIGH ASPECT RATIO FILL METHOD AND RESULTING STRUCTURE
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|
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Patent #:
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Issue Dt:
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07/31/2007
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Application #:
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10156420
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Filing Dt:
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05/28/2002
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Publication #:
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Pub Dt:
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12/04/2003
| | | | |
Title:
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APPARATUS AND METHODS HAVING A COMMAND SEQUENCE
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Patent #:
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Issue Dt:
|
08/12/2003
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Application #:
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10156976
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Filing Dt:
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05/29/2002
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Publication #:
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Pub Dt:
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10/10/2002
| | | | |
Title:
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METHODS FOR STACKING WIRE-BONDED INTEGRATED CIRCUIT DICE ON FLIP-CHIP BONDED INTEGRATED CIRCUIT DICE
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|
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Patent #:
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Issue Dt:
|
04/06/2004
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Application #:
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10157049
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Filing Dt:
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05/29/2002
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Publication #:
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Pub Dt:
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12/04/2003
| | | | |
Title:
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METHOD OF FORMING BIASABLE ISOLATION REGIONS USING EPITAXIALLY GROWN SILICON BETWEEN THE ISOLATION REGIONS
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|
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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10157422
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Filing Dt:
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05/29/2002
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Publication #:
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Pub Dt:
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10/03/2002
| | | | |
Title:
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USE OF RESIDUAL ORGANIC COMPOUNDS TO FACILITATE GATE BREAK ON A CARRIER SUBSTRATE FOR A SEMICONDUCTOR DEVICE
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|
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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10157479
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Filing Dt:
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05/29/2002
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Publication #:
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Pub Dt:
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10/03/2002
| | | | |
Title:
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APPARATUS FOR IMPLEMENTING SELECTED FUNCTIONALITY ON AN INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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10158424
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Filing Dt:
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05/29/2002
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Publication #:
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Pub Dt:
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10/03/2002
| | | | |
Title:
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PROCESS FOR INTEGRATING IN A SAME CHIP A NON-VOLATILE MEMORY AND A HIGH-PERFORMANCE LOGIC CIRCUITRY
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Patent #:
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Issue Dt:
|
04/22/2003
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Application #:
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10158553
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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12/26/2002
| | | | |
Title:
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COLUMN MULTIPLEXER FOR SEMICONDUCTOR MEMORIES
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Patent #:
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Issue Dt:
|
07/15/2003
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Application #:
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10158554
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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12/26/2002
| | | | |
Title:
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SEMICONDUCTOR MEMORY SYSTEM
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|
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Patent #:
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Issue Dt:
|
03/23/2004
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Application #:
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10158706
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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10/03/2002
| | | | |
Title:
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METHOD OF MAKING FLOATING GATE NON-VOLATILE MEMORY CELL WITH LOW ERASING VOLTAGE HAVING DOUBLE LAYER GATE DIELECTRIC
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Patent #:
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Issue Dt:
|
06/15/2004
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Application #:
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10159085
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Filing Dt:
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05/29/2002
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Publication #:
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Pub Dt:
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12/04/2003
| | | | |
Title:
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INTEGRATED CIRCUIT RESET CIRCUITRY
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Patent #:
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Issue Dt:
|
03/22/2005
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Application #:
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10159780
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
|
02/06/2003
| | | | |
Title:
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METHOD FOR ERASING AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE, AND AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
|
03/21/2006
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Application #:
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10159782
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
|
01/23/2003
| | | | |
Title:
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METHOD FOR ERROR CONTROL IN MULTILEVEL CELLS WITH CONFIGURABLE NUMBER OF STORED BITS
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|
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Patent #:
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Issue Dt:
|
09/21/2004
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Application #:
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10159885
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Filing Dt:
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05/29/2002
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Publication #:
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Pub Dt:
|
12/04/2003
| | | | |
Title:
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METHOD AND APPARATUS FOR ERASING FLASH MEMORY
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|
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Patent #:
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Issue Dt:
|
09/16/2003
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Application #:
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10160063
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Filing Dt:
|
06/04/2002
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Title:
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METHOD AND APPARATUS FOR PROGRAMMING ROW REDUNDANCY FUSES SO DECODING MATCHES INTERNAL PATTERN OF A MEMORY ARRAY
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Patent #:
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Issue Dt:
|
06/01/2010
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Application #:
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10160641
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Filing Dt:
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05/31/2002
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Publication #:
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Pub Dt:
|
12/04/2003
| | | | |
Title:
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FORMING FERROELECTRIC POLYMER MEMORIES
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|
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Patent #:
|
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Issue Dt:
|
05/16/2006
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Application #:
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10160698
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
|
10/17/2002
| | | | |
Title:
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SEMICONDUCTOR PROCESSING METHODS OF TRANSFERRING PATTERNS FROM PATTERNED PHOTORESISTS TO MATERIALS, AND STRUCTURES COMPRISING SILICON NITRIDE
|
|
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Patent #:
|
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Issue Dt:
|
07/18/2006
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Application #:
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10160705
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Filing Dt:
|
05/30/2002
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Publication #:
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Pub Dt:
|
10/17/2002
| | | | |
Title:
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SEMICONDUCTOR PROCESSING METHODS OF TRANSFERRING PATTERNS FROM PATTERNED PHOTORESISTS TO MATERIALS, AND STRUCTURES COMPRISING SILICON NITRIDE
|
|
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Patent #:
|
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Issue Dt:
|
09/07/2004
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Application #:
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10161053
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Filing Dt:
|
05/30/2002
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Publication #:
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Pub Dt:
|
03/13/2003
| | | | |
Title:
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OUTPUT BUFFER FOR A NONVOLATILE MEMORY WITH OUTPUT SIGNAL SWITCHING NOISE REDUCTION, AND NONVOLATILE MEMORY COMPRISING THE SAME
|
|