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06/26/2001
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09377183
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08/19/1999
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Title:
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NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING ASSYMETRICALLY NITROGEN DOPED GATE OXIDE
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07/11/2000
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09379479
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08/23/1999
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Title:
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FLASH MEMORY ARCHITECTURE EMPLOYING THREE LAYER METAL INTERCONNECT FOR WORD LINE DECODING
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11/27/2001
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09384510
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08/27/1999
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Title:
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LOW DISTORTION LOGIC LEVEL TRANSLATOR
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06/05/2001
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09385550
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Filing Dt:
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08/30/1999
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Title:
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USING POLYSILICON FUSE FOR IC PROGRAMMING
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06/25/2002
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09387018
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08/31/1999
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CONTINOUS CAPACITOR DIVIDER SAMPLED REGULATION SCHEME
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07/09/2002
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09387421
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08/31/1999
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Title:
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EMBEDDED METHODOLOGY TO PROGRAM/ERASE REFERENCE CELLS USED IN SENSING FLASH CELLS
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06/10/2003
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09387710
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08/30/1999
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INTEGRATED CIRCUIT HAVING OPTIMIZED GATE COUPLING CAPACITANCE
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10/31/2000
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09388696
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09/02/1999
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Title:
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MULTI LEVEL SENSING OF NAND MEMORY CELLS BY EXTERNAL BIAS CURRENT
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10/31/2000
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09389161
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09/02/1999
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Title:
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1 TRANSISTOR CELL FOR EEPROM APPLICATION
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11/27/2001
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09390052
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09/03/1999
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Title:
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FLASH MEMORY DEVICE AND FABRICATION METHOD HAVING A HIGH COUPLING RATIO
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02/27/2001
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09390591
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09/03/1999
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Title:
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DIFFERENTIAL SIGNAL DETECTION CIRCUIT
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09/11/2001
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09392675
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09/08/1999
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Title:
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PROCESS FOR FABRICATING AN MNOS FLASH MEMORY DEVICE
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10/16/2001
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09394819
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09/13/1999
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Title:
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SYSTEM FOR CLEANING A SURFACE OF A DIELECTRIC MATERIAL
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12/04/2001
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09395057
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09/13/1999
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Title:
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METHOD AND APPARATUS FOR CONTROLLING A MEMORY ARRAY WITH A
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09/18/2001
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09396024
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09/15/1999
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Title:
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COLUMN REDUNDANCY SCHEME FOR BUS-MATCHING FIFOS
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05/08/2001
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09396344
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09/15/1999
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Title:
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HIGH SPEED CHARGE-PUMP
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02/25/2003
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09398736
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09/17/1999
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Title:
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FIFO BUS-SIZING, BUS-MATCHING DATAPATH ARCHITECTURE
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05/29/2001
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09398936
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09/17/1999
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Title:
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METHOD, ARCHITECTURE AND/OR CIRCUITRY FOR CONTROLLING THE PULSE WIDTH IN A PHASE AND/OR FREQUENCY DETECTOR
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03/09/2004
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09398956
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09/17/1999
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Title:
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FREQUENCY ACQUISITION RATE CONTROL IN PHASE LOCK LOOP CIRCUITS
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04/30/2002
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09399414
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09/20/1999
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Title:
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PROCESS TO IMPROVE READ DISTURB FOR NAND FLASH MEMORY DEVICES
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09/04/2001
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09399526
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09/20/1999
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Title:
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PROCESS TO REDUCE POST CYCLING PROGRAM VT DISPERSION FOR NAND FLASH MEMORY DEVICES
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02/20/2001
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09400685
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09/22/1999
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Title:
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INPUT BUFFER/LEVEL SHIFTER
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03/04/2003
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09401614
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09/22/1999
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Title:
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PARALLEL TEST IN ASYNCHRONOUS MEMORY WITH SINGLE-ENDED OUTPUT PATH
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01/09/2001
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09404078
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09/23/1999
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Title:
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CONCURRENT ERASE VERIFY SCHEME FOR FLASH MEMORY APPLICATIONS
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04/11/2000
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09404080
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Filing Dt:
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09/23/1999
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Title:
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OPERATIONAL APPROACH FOR THE SUPPRESSION OF BI-DIRECTIONAL TUNNEL OXIDE STRESS OF A FLASH CELL
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04/09/2002
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09404394
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09/23/1999
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Title:
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SEMICONDUCTOR DEVICE WITH CONTACTS HAVING A SLOPED PROFILE
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01/29/2002
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09404395
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09/23/1999
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02/28/2002
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Title:
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METHOD AND SYSTEM FOR PROVIDING REDUCED-SIZED CONTACTS IN A SEMICONDUCTOR DEVICE
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Patent #:
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05/11/2004
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09405945
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09/27/1999
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Title:
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SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING CONTACTS IN A SEMICONDUCTOR STRUCTURE
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07/11/2000
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09405950
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09/27/1999
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Title:
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CIRCUIT AND METHOD FOR CONTROLLING A WORDLINE AND/OR STABILIZING A MEMORY CELL
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Patent #:
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03/13/2001
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09409542
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09/30/1999
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Title:
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METHOD AND APPARATUS FOR MEASURING SUBTHRESHOLD CURRENT IN A MEMORY ARRAY
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Patent #:
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Issue Dt:
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06/13/2006
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09410160
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09/30/1999
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Title:
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METHOD AND APPARATUS FOR AUTOMATED ENUMERATION, SIMULATION, IDENTIFICATION AND/OR IRRADIATION OF DEVICE ATTRIBUTES
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07/24/2001
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09410512
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09/30/1999
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Title:
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DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE AND PROGRAMMING METHOD UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
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Issue Dt:
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09/17/2002
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09411169
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10/01/1999
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Title:
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LOW THRESHOLD VOLTAGE DEVICE WITH CHARGE PUMP FOR REDUCING STANDBY CURRENT IN AN INTEGRATED CIRCUIT HAVING REDUCED SUPPLY VOLTAGE
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01/23/2001
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09412278
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10/05/1999
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Title:
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POST BARRIER METAL CONTACT IMPLANTATION TO MINIMIZE OUT DIFFUSION FOR NAND DEVICE
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Patent #:
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05/22/2001
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09412544
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Filing Dt:
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10/05/1999
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Title:
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METHOD AND SYSTEM FOR REDUCING SHORT CHANNEL EFFECTS IN A MEMORY DEVICE
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Issue Dt:
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09/19/2000
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09413182
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10/05/1999
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Title:
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BIT BY BIT APDE VERIFY FOR FLASH MEMORY APPLICATIONS
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Issue Dt:
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01/14/2003
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09413621
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Filing Dt:
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10/06/1999
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Title:
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IN-SITU PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE WITH INTEGRAL REMOVAL OF ANTIREFLECTION AND ETCH STOP LAYERS
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Issue Dt:
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09/18/2001
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Application #:
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09416382
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Filing Dt:
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10/12/1999
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Title:
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METHOD FOR REMOVING ANTI-REFLECTIVE COATING LAYER USING PLASMA ETCH PROCESS BEFORE CONTACT CMP
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Issue Dt:
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10/24/2000
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09416389
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Filing Dt:
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10/12/1999
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Title:
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METHOD FOR REMOVING ANTI-REFLECTIVE COATING LAYER USING PLASMA ETCH PROCESS AFTER CONTACT CMP
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08/14/2001
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Application #:
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09416563
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Filing Dt:
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10/12/1999
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Title:
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MULTIPLE BYTE CHANNEL HOT ELECTRON PROGRAMMING USING RAMPED GATE AND SOURCE BIAS VOLTAGE
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Issue Dt:
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03/06/2001
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Application #:
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09417130
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Filing Dt:
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10/13/1999
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Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH REDUCED MASKING AND WITHOUT ARC LOSS IN PERIPHERAL CIRCUITRY REGION
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05/22/2001
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09417131
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Filing Dt:
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10/13/1999
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Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH REDUCED ARC LOSS IN PERIPHERAL CIRCUITRY REGION
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03/13/2001
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Application #:
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09417132
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Filing Dt:
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10/13/1999
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Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITHOUT ARC LOSS IN PERIPHERAL CIRCUIT REGION
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09417731
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Filing Dt:
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10/14/1999
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Title:
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DISTRIBUTING CFI DEVICES IN EXISTING DECODERS
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Issue Dt:
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11/07/2000
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Application #:
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09417732
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Filing Dt:
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10/14/1999
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Title:
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METHOD AND SYSTEM FOR BI-DIRECTIONAL VOLTAGE REGULATION DETECTION
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11/14/2000
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Application #:
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09419695
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Filing Dt:
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10/14/1999
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Title:
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METHOD AND SYSTEM FOR SAVING OVERHEAD PROGRAM TIME IN A MEMORY DEVICE
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Issue Dt:
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02/06/2001
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09420209
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Filing Dt:
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10/18/1999
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Title:
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PROGRAMMABLE CURRENT SOURCE
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09420220
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Filing Dt:
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10/18/1999
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Title:
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NITRIDE PLUG TO REDUCE GATE EDGE LIFTING
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Patent #:
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Issue Dt:
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12/09/2003
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Application #:
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09420535
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Filing Dt:
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10/19/1999
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Title:
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OTP SECTOR DOUBLE PROTECTION FOR A SIMULTANEOUS OPERATION FLASH MEMORY
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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09421105
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Filing Dt:
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10/19/1999
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Title:
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SECTOR WRITE PROTECT CAMS FOR A SIMULTANEOUS OPERATION FLASH MEMORY
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09421142
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Filing Dt:
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10/19/1999
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Title:
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LATCHING CAM DATA IN A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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09421333
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Filing Dt:
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10/18/1999
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Title:
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ALUMINUM METALLIZATION METHOD AND PRODUCT
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Issue Dt:
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09/04/2001
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Application #:
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09421471
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Filing Dt:
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10/19/1999
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Title:
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OUTPUT SWITCHING IMPLEMENTATION FOR A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/18/2001
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Application #:
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09421757
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Filing Dt:
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10/19/1999
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Title:
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WRITE PROTECT INPUT IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09421762
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Filing Dt:
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10/19/1999
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Title:
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SEPARATE OUTPUT POWER SUPPLY TO REDUCE OUTPUT NOISE FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09421774
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Filing Dt:
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10/19/1999
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Title:
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COMMON FLASH INTERFACE IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09421775
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Filing Dt:
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10/19/1999
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Title:
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REFERENCE CELL BITLINE PATH ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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09421776
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Filing Dt:
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10/19/1999
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Title:
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ADDRESS TRANSISTION DETECT TIMING ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY
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Patent #:
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Issue Dt:
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02/06/2001
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Application #:
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09421984
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Filing Dt:
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10/19/1999
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Title:
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REFERENCE CELL FOUR-WAY SWITCH FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/19/2002
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Application #:
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09421985
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Filing Dt:
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10/19/1999
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Title:
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LOW VOLTAGE READ CASCODE FOR 2V/3V AND DIFFERENT BANK COMBINATIONS WITHOUT METAL OPTIONS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09422198
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Filing Dt:
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10/19/1999
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Title:
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SENSE AMPLIFIER ARCHITECTURE FOR SLIDING BANKS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09422199
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Filing Dt:
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10/19/1999
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Title:
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OUTPUT MULTIPLEXING IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09426100
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Filing Dt:
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10/22/1999
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Title:
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SILICON-OXIDE-NITRIDE-OXIDE-SEMICONDUCTOR (SONOS) TYPE MEMORY CELL AND METHOD FOR RETAINING DATA IN THE SAME
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09426205
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Filing Dt:
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10/25/1999
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Title:
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PROCESS FOR FABRICATING A BIT-LINE IN A MONOS DEVICE USING A DUAL LAYER HARD MASK
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09426239
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Filing Dt:
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10/25/1999
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Title:
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METHOD TO GENERATE A MONOS TYPE FLASH CELL USING POLYCRYSTALLINE SILICON AS AN ONO TOP LAYER
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09426255
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Filing Dt:
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10/25/1999
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Title:
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METHOD OF USING SOURCE/DRAIN NITRIDE FOR PERIPHERY FIELD OXIDE AND BIT-LINE OXIDE
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09426427
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Filing Dt:
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10/25/1999
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Title:
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METHOD OF FABRICATING A MONOS FLASH CELL USING SHALLOW TRENCH ISOLATION
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09426430
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Filing Dt:
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10/25/1999
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Title:
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METHOD OF FABRICATING AN ONO DIELECTRIC BY NITRIDATION FOR MNOS MEMORY CELLS
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09426672
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Filing Dt:
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10/25/1999
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Title:
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HIGH TEMPERATURE OXIDE DEPOSITION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO BIT EEPROM DEVICE
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09426743
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Filing Dt:
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10/25/1999
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Title:
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PROCESS FOR FORMING A BIT-LINE IN A MONOS DEVICE
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09426757
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Filing Dt:
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10/26/1999
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Title:
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MICROPROCESSOR FOR CONTROLLING BUSSES
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09427402
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Filing Dt:
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10/25/1999
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Title:
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INTEGRATED METHOD BY USING HIGH TEMPERATURE OXIDE FOR TOP OXIDE AND PERIPHERY GATE OXIDE
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09427404
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Filing Dt:
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10/25/1999
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Title:
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PROCESS FOR FABRICATING A BIT-LINE USING BURIED DIFFUSION ISOLATION
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09427644
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Filing Dt:
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10/27/1999
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Title:
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MULTI-LAYER APPROACH FOR OPTIMIZING FERROELECTRIC FILM PERFORMANCE
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09428624
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Filing Dt:
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10/27/1999
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Title:
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CIRCUIT AND METHOD FOR PREVENTING RUNAWAY IN A PHASE LOCK LOOP
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09429722
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Filing Dt:
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10/29/1999
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Title:
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PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS USING A METALLIC HARD MASK
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09430336
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Filing Dt:
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10/29/1999
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Title:
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BIASING SCHEME TO REDUCE STRESS ON NON-SELECTED CELLS DURING READ
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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09430366
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Filing Dt:
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10/28/1999
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Title:
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METHOD OF MAKING A MEMORY CELL WITH POLISHED INSULATOR LAYER
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09430410
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Filing Dt:
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10/29/1999
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Title:
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SOLID-SOURCE DOPING FOR SOURCE/DRAIN TO ELIMINATE IMPLANT DAMAGE
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09430493
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Filing Dt:
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10/29/1999
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Title:
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PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS USING A POLYSILICON HARD MASK
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09430765
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Filing Dt:
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10/29/1999
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Title:
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METHOD FOR FORMING FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09430848
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Filing Dt:
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11/01/1999
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Title:
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SPACER NARROWED, DUAL WIDTH CONTACT FOR CHARGE GAIN REDUCTION
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09433037
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Filing Dt:
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10/25/1999
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Title:
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NITRIDATION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO-BIT EEPROM DEVICE
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09433041
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Filing Dt:
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10/25/1999
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Title:
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PROCESS FOR FABRICATING AN ONO STRUCTURE HAVING A SILICON-RICH SILICON NITRIDE LAYER
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09433186
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Filing Dt:
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10/25/1999
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Title:
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PROCESS FOR FABRICATING AN ONO STRUCTURE
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09433822
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Filing Dt:
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11/03/1999
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Title:
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CIRCUIT, ARCHITECTURE AND METHOD FOR REDUCING POWER CONSUMPTION IN A SYNCHRONOUS INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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09434908
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Filing Dt:
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11/05/1999
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Title:
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APPARATUS AND METHOD FOR CONTROLLING AN ELECTRONIC PRESENTATION
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09436155
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Filing Dt:
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11/09/1999
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Title:
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CIRCUIT AND METHOD FOR LINEAR CONTROL OF A SPREAD SPECTRUM TRANSITION
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09436503
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Filing Dt:
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11/09/1999
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Title:
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DOUBLE DENSITY NON-VOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09440934
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Filing Dt:
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11/16/1999
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Title:
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SEMICONDUCTOR ISOLATION PROCESS TO MINIMIZE WEAK OXIDE PROBLEMS
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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09441134
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Filing Dt:
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11/17/1999
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Publication #:
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Pub Dt:
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04/17/2003
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Title:
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SELECTOR AND MULTILAYER INTERCONNECTION WITH REDUCED OCCUPIED AREA ON SUBSTRATE
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Patent #:
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Issue Dt:
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12/03/2002
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Application #:
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09441649
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Filing Dt:
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11/17/1999
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Publication #:
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Pub Dt:
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11/21/2002
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Title:
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CIRCUITS, ARCHITECTURES, AND METHODS FOR GENERATING A PERIODIC SIGNAL IN A MEMORY
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09442851
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Filing Dt:
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11/18/1999
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Title:
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ARCHITECTURE, CIRCUITRY AND METHOD FOR CONFIGURING VOLATILE AND/OR NON-VOLATILE MEMORY FOR PROGRAMMABLE LOGIC APPLICATIONS
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09451958
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Filing Dt:
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11/30/1999
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Title:
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MOS OUTPUT DRIVER, AND CIRCUIT AND METHOD OF CONTROLLING SAME
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09451959
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Filing Dt:
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11/30/1999
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Title:
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METHOD AND APPARATUS FOR THE AUTOMATED GENERATION OF SINGLE AND MULTISTAGE PROGRAMMABLE INTERCONNECT MATRICES WITH AUTOMATIC ROUTING TOOLS
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09456801
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Filing Dt:
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12/08/1999
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Title:
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NON-VOLATILE INVERTER LATCH
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09458552
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Filing Dt:
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12/09/1999
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Title:
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Tristate output buffer with matched signals to pmos and nmos output transistors
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09461376
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Filing Dt:
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12/15/1999
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Title:
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BIASING METHOD AND STRUCTURE FOR REDUCING BAND-TO-BAND AND/OR AVALANCHE CURRENTS DURING THE ERASE OF FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09461632
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Filing Dt:
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12/15/1999
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Title:
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BLOCK REDUNDANCY IN ULTRA LOW POWER MEMORY CIRCUITS
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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09465067
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Filing Dt:
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12/16/1999
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Title:
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METHOD AND ARCHITECTURE FOR RE-PROGRAMMING CONVENTIONALLY NON-REPROGRAMMABLE TECHNOLOGY
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