|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
11859865
|
Filing Dt:
|
09/24/2007
|
Publication #:
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|
Pub Dt:
|
01/10/2008
| | | | |
Title:
|
SOI DEVICE WITH REDUCED JUNCTION CAPACITANCE
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|
|
Patent #:
|
|
Issue Dt:
|
12/08/2009
|
Application #:
|
11859889
|
Filing Dt:
|
09/24/2007
|
Publication #:
|
|
Pub Dt:
|
01/10/2008
| | | | |
Title:
|
HYBRID CRYSTAL ORIENTATION CMOS STRUCTURE FOR ADAPTIVE WELL BIASING AND FOR POWER AND PERFORMANCE ENHANCEMENT
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|
|
Patent #:
|
|
Issue Dt:
|
11/17/2009
|
Application #:
|
11859890
|
Filing Dt:
|
09/24/2007
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
METHOD OF ADDING FABRICATION MONITORS TO INTEGRATED CIRCUIT CHIPS
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11859965
|
Filing Dt:
|
09/24/2007
|
Publication #:
|
|
Pub Dt:
|
03/26/2009
| | | | |
Title:
|
SYSTEM FOR AND METHOD OF INTEGRATING TEST STRUCTURES INTO AN INTEGRATED CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
11860226
|
Filing Dt:
|
09/24/2007
|
Publication #:
|
|
Pub Dt:
|
03/26/2009
| | | | |
Title:
|
METHOD AND STRUCTURE FOR DISPENSING CHIP UNDERFILL THROUGH AN OPENING IN THE CHIP
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|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
11860459
|
Filing Dt:
|
09/24/2007
|
Publication #:
|
|
Pub Dt:
|
01/20/2011
| | | | |
Title:
|
METHODS OF MANUFACTURE OF VERTICAL NANOWIRE FET DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2010
|
Application #:
|
11860613
|
Filing Dt:
|
09/25/2007
|
Publication #:
|
|
Pub Dt:
|
03/26/2009
| | | | |
Title:
|
STRESS RELIEF STRUCTURES FOR SILICON INTERPOSERS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2010
|
Application #:
|
11860616
|
Filing Dt:
|
09/25/2007
|
Publication #:
|
|
Pub Dt:
|
01/17/2008
| | | | |
Title:
|
EARLY HSS RX DATA SAMPLING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
11860840
|
Filing Dt:
|
09/25/2007
|
Publication #:
|
|
Pub Dt:
|
03/26/2009
| | | | |
Title:
|
DUAL METAL GATE FINFETS WITH SINGLE OR DUAL HIGH-K GATE DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
11860851
|
Filing Dt:
|
09/25/2007
|
Publication #:
|
|
Pub Dt:
|
03/26/2009
| | | | |
Title:
|
SEMICONDUCTOR-ON-INSULATOR STRUCTURES INCLUDING A TRENCH CONTAINING AN INSULATOR STRESSOR PLUG AND METHOD OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11861369
|
Filing Dt:
|
09/26/2007
|
Publication #:
|
|
Pub Dt:
|
01/10/2008
| | | | |
Title:
|
PRESSURIZED OXYGEN FOR EVALUATION OF MOLDING COMPOUND STABILITY IN SEMICONDUCTOR PACKAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
11861614
|
Filing Dt:
|
09/26/2007
|
Publication #:
|
|
Pub Dt:
|
03/26/2009
| | | | |
Title:
|
SHALLOW TRENCH ISOLATION STRUCTURE COMPATIBLE WITH SOI EMBEDDED DRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
11861704
|
Filing Dt:
|
09/26/2007
|
Title:
|
STRUCTURE AND METHOD FOR FORMING SOI TRENCH MEMORY WITH SINGLE-SIDED STRAP
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11861787
|
Filing Dt:
|
09/26/2007
|
Publication #:
|
|
Pub Dt:
|
01/17/2008
| | | | |
Title:
|
POLISHING INHIBITING LAYER FORMING ADDITIVE, SLURRY AND CMP METHOD
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|
|
Patent #:
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|
Issue Dt:
|
06/07/2011
|
Application #:
|
11862255
|
Filing Dt:
|
09/27/2007
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
PHOTORESIST TRIMMING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
|
Application #:
|
11862540
|
Filing Dt:
|
09/27/2007
|
Publication #:
|
|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
SLIP RING POSITIVE Z FORCE LIQUID ISOLATION FIXTURE PERMITTING ZERO NET FORCE ON WORKPIECE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
11862545
|
Filing Dt:
|
09/27/2007
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
PRINTED CIRCUIT BOARD MANUFACTURING METHOD AND PRINTED CIRCUIT BOARD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
11862706
|
Filing Dt:
|
09/27/2007
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
PROCESS FOR INTERFACIAL ADHESION IN LAMINATE STRUCTURES THROUGH PATTERNED ROUGHING OF A SURFACE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11863349
|
Filing Dt:
|
09/28/2007
|
Publication #:
|
|
Pub Dt:
|
05/22/2008
| | | | |
Title:
|
Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM Arrays
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
11863356
|
Filing Dt:
|
09/28/2007
|
Publication #:
|
|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
METHODS TO PREVENT ECC (EDGE CHIPPING AND CRACKING) DAMAGE DURING DIE PICKING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
11863502
|
Filing Dt:
|
09/28/2007
|
Publication #:
|
|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
COPPER CONTAMINATION DETECTION METHOD AND SYSTEM FOR MONITORING COPPER CONTAMINATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11863618
|
Filing Dt:
|
09/28/2007
|
Publication #:
|
|
Pub Dt:
|
01/17/2008
| | | | |
Title:
|
ELECTRICALLY PROGRAMMABLE PI-SHAPED FUSE STRUCTURES AND METHODS OF FABRICATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
11863623
|
Filing Dt:
|
09/28/2007
|
Publication #:
|
|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
COPPER CONTAMINATION DETECTION METHOD AND SYSTEM FOR MONITORING COPPER CONTAMINATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
|
Application #:
|
11863724
|
Filing Dt:
|
09/28/2007
|
Publication #:
|
|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
STRUCTURES AND METHODS FOR REDUCTION OF PARASITIC CAPACITANCES IN SEMICONDUCTOR INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
11863757
|
Filing Dt:
|
09/28/2007
|
Publication #:
|
|
Pub Dt:
|
10/02/2008
| | | | |
Title:
|
HIGH MOBILITY CMOS CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2012
|
Application #:
|
11863759
|
Filing Dt:
|
09/28/2007
|
Publication #:
|
|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11863814
|
Filing Dt:
|
09/28/2007
|
Publication #:
|
|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
SEMICONDUCTOR FUSE STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
11865170
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
NICKEL ALLOY PLATED STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
11865217
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
11865231
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2011
|
Application #:
|
11865252
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
LAYOUT QUALITY GAUGE FOR INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
11865253
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
11865293
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11865305
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
11865321
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11865327
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER STRUCTURE PROVIDING FOR ELECTRICAL CONTACTS ON OPPOSITE SIDES OF A CARRIER PLANE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2008
|
Application #:
|
11865353
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
LGA UTILIZING METAL-ON-ELASTOMER HEMI-TORUS HAVING A SLITTED WALL SURFACE FOR VENTING GASES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2009
|
Application #:
|
11865383
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2008
|
Application #:
|
11865395
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2008
|
Application #:
|
11865396
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
11865423
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2009
|
Application #:
|
11865436
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER GROUPS OF DIFFERENT HEIGHTS UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
11865440
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
11865458
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
11865728
|
Filing Dt:
|
10/01/2007
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR MANUFACTURING DIAMOND SHAPED CHIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2012
|
Application #:
|
11865780
|
Filing Dt:
|
10/02/2007
|
Publication #:
|
|
Pub Dt:
|
12/10/2009
| | | | |
Title:
|
HIGH DENSITY STABLE STATIC RANDOM ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11865797
|
Filing Dt:
|
10/02/2007
|
Publication #:
|
|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
DETERMINING FLEET MATCHING PROBLEM AND ROOT CAUSE ISSUE FOR MEASUREMENT SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
11865820
|
Filing Dt:
|
10/02/2007
|
Publication #:
|
|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
STACKED POWER CLAMP HAVING A BIGFET GATE PULL-UP CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
11865982
|
Filing Dt:
|
10/02/2007
|
Publication #:
|
|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
PHOTOMASK AND METHOD OF MAKING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2012
|
Application #:
|
11866110
|
Filing Dt:
|
10/02/2007
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
RATIOED FEEDBACK BODY VOLTAGE BIAS GENERATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
11866435
|
Filing Dt:
|
10/03/2007
|
Publication #:
|
|
Pub Dt:
|
04/17/2008
| | | | |
Title:
|
CORNER DOMINATED TRIGATE FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
11866455
|
Filing Dt:
|
10/03/2007
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
METHODS FOR FABRICATING CONTACTS TO PILLAR STRUCTURES IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
11866502
|
Filing Dt:
|
10/03/2007
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
CIRCUITS AND METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
11866537
|
Filing Dt:
|
10/03/2007
|
Publication #:
|
|
Pub Dt:
|
01/22/2009
| | | | |
Title:
|
DESIGN STRUCTURES, METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11866627
|
Filing Dt:
|
10/03/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETs
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11866629
|
Filing Dt:
|
10/03/2007
|
Publication #:
|
|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
DRILL STACK FORMATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11866741
|
Filing Dt:
|
10/03/2007
|
Publication #:
|
|
Pub Dt:
|
03/27/2008
| | | | |
Title:
|
METHOD OF FABRICATING A WIRE BOND PAD WITH Ni/Au METALLIZATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11866796
|
Filing Dt:
|
10/03/2007
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
DEVICE MODELING FOR PROXIMITY EFFECTS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11867162
|
Filing Dt:
|
10/04/2007
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR AUTOMATING PROCESS AND EQUIPMENT QUALIFICATIONS IN A MANUFACTURING ENVIRONMENT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11867213
|
Filing Dt:
|
10/04/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
11867235
|
Filing Dt:
|
10/04/2007
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
FABRICATION OF SOI WITH GETTERING LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11867264
|
Filing Dt:
|
10/04/2007
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
CHANNEL STRESS ENGINEERING USING LOCALIZED ION IMPLANTATION INDUCED GATE ELECTRODE VOLUMETRIC CHANGE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2010
|
Application #:
|
11867266
|
Filing Dt:
|
10/04/2007
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
HIGH PERFORMANCE MOSFET
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
11867271
|
Filing Dt:
|
10/04/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
HIGH PERFORMANCE CMOS DEVICE STRUCTURES AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
11867428
|
Filing Dt:
|
10/04/2007
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
MIXED LITHOGRAPHY WITH DUAL RESIST AND A SINGLE PATTERN TRANSFER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2010
|
Application #:
|
11867840
|
Filing Dt:
|
10/05/2007
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
Title:
|
SIDEWALL SEMICONDUCTOR TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
11867995
|
Filing Dt:
|
10/05/2007
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
Title:
|
STRUCTURES AND METHODS OF FORMING SIGE AND SIGEC BURIED LAYER FOR SOI/SIGE TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2009
|
Application #:
|
11868046
|
Filing Dt:
|
10/05/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
METHOD FOR IMPROVING SENSING MARGIN OF ELECTRICALLY PROGRAMMABLE FUSES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2010
|
Application #:
|
11868320
|
Filing Dt:
|
10/05/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
IMMERSION TOPCOAT MATERIALS WITH IMPROVED PERFORMANCE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11868567
|
Filing Dt:
|
10/08/2007
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
DUAL STRESS LINER STRUCTURE HAVING SUBSTANTIALLY PLANAR INTERFACE BETWEEN LINERS AND RELATED METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
|
Application #:
|
11869145
|
Filing Dt:
|
10/09/2007
|
Publication #:
|
|
Pub Dt:
|
01/22/2009
| | | | |
Title:
|
ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2009
|
Application #:
|
11869146
|
Filing Dt:
|
10/09/2007
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR A HIGH-SPEED LEVEL SHIFTER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2010
|
Application #:
|
11869171
|
Filing Dt:
|
10/09/2007
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
SELF-ASSEMBLED SIDEWALL SPACER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
11869178
|
Filing Dt:
|
10/09/2007
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
SELF-ASSEMBLED SIDEWALL SPACER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
11869179
|
Filing Dt:
|
10/09/2007
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
AN ON-CHIP IDENTIFICATION CIRCUIT INCORPORATING PAIRS OF CONDUCTORS, EACH HAVING AN ESSENTIALLY RANDOM CHANCE OF BEING SHORTED TOGETHER AS A RESULT OF PROCESS VARIATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
|
Application #:
|
11869216
|
Filing Dt:
|
10/09/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
STRUCTURE FOR DYNAMICALLY ADJUSTING PIPELINED DATA PATHS FOR IMPROVED POWER MANAGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2009
|
Application #:
|
11869218
|
Filing Dt:
|
10/09/2007
|
Publication #:
|
|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
METAL RESISTOR AND RESISTOR MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
11869306
|
Filing Dt:
|
10/09/2007
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
11869373
|
Filing Dt:
|
10/09/2007
|
Publication #:
|
|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
PHOTORESIST TRIMMING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
11869593
|
Filing Dt:
|
10/09/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
SPIN-CURRENT SWITCHABLE MAGNETIC MEMORY ELEMENT AND METHOD OF FABRICATING THE MEMORY ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
11869787
|
Filing Dt:
|
10/10/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
SOLDER BUMPS IN FLIP-CHIP TECHNOLOGIES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
11869841
|
Filing Dt:
|
10/10/2007
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
IMPLEMENTING APS VOLTAGE LEVEL ACTIVATION WITH SECONDARY CHIP IN STACKED-CHIP TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2009
|
Application #:
|
11869850
|
Filing Dt:
|
10/10/2007
|
Publication #:
|
|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
METHOD AND SYSTEM TO DEVELOP A PROCESS IMPROVEMENT METHODOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11869921
|
Filing Dt:
|
10/10/2007
|
Publication #:
|
|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
FPGA POWERUP TO KNOWN FUNCTIONAL STATE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11869958
|
Filing Dt:
|
10/10/2007
|
Publication #:
|
|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
STRUCTURE AND METHOD FOR FORMING A DIELECTRIC CHAMBER AND ELECTRONIC DEVICE INCLUDING DIELECTRIC CHAMBER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2010
|
Application #:
|
11870167
|
Filing Dt:
|
10/10/2007
|
Publication #:
|
|
Pub Dt:
|
04/16/2009
| | | | |
Title:
|
PHOTOSENSITIVE SELF-ASSEMBLED MONOLAYER FOR SELECTIVE PLACEMENT OF HYDROPHILIC STRUCTURES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11870263
|
Filing Dt:
|
10/10/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
ULTRA LOW K (ULK) SiCOH FILM AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2008
|
Application #:
|
11870436
|
Filing Dt:
|
10/11/2007
|
Publication #:
|
|
Pub Dt:
|
04/17/2008
| | | | |
Title:
|
HYBRID SOI-BULK SEMICONDUCTOR TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
11870437
|
Filing Dt:
|
10/11/2007
|
Publication #:
|
|
Pub Dt:
|
04/10/2008
| | | | |
Title:
|
LOCAL COLLECTOR IMPLANT STRUCTURE FOR HETEROJUNCTION BIPOLAR TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
11870463
|
Filing Dt:
|
10/11/2007
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
WAVEGUIDE POLARIZATION BEAM SPLITTERS AND METHOD OF FABRICATING A WAVEGUIDE WIRE-GRID POLARIZATION BEAM SPLITTER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2012
|
Application #:
|
11870551
|
Filing Dt:
|
10/11/2007
|
Publication #:
|
|
Pub Dt:
|
04/16/2009
| | | | |
Title:
|
STRUCTURE AND METHODS OF FORMING CONTACT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2009
|
Application #:
|
11870567
|
Filing Dt:
|
10/11/2007
|
Publication #:
|
|
Pub Dt:
|
02/14/2008
| | | | |
Title:
|
SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
11870575
|
Filing Dt:
|
10/11/2007
|
Publication #:
|
|
Pub Dt:
|
01/22/2009
| | | | |
Title:
|
STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2012
|
Application #:
|
11870875
|
Filing Dt:
|
10/11/2007
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
SOLID STATE KLYSTRON
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
11871179
|
Filing Dt:
|
10/12/2007
|
Publication #:
|
|
Pub Dt:
|
04/16/2009
| | | | |
Title:
|
METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR AUTOMATICALLY WAIVING NON-COMPUTE INDICATIONS FOR A TIMING ANALYSIS PROCESS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11871198
|
Filing Dt:
|
10/12/2007
|
Publication #:
|
|
Pub Dt:
|
04/16/2009
| | | | |
Title:
|
Device Threshold Calibration Through State Dependent Burnin
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
|
Application #:
|
11871204
|
Filing Dt:
|
10/12/2007
|
Publication #:
|
|
Pub Dt:
|
04/16/2009
| | | | |
Title:
|
SEMICONDUCTOR CHIP PACKAGES HAVING REDUCED STRESS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
11871249
|
Filing Dt:
|
10/12/2007
|
Publication #:
|
|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
SELECTIVE SILICON-ON-INSULATOR ISOLATION STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2009
|
Application #:
|
11871368
|
Filing Dt:
|
10/12/2007
|
Publication #:
|
|
Pub Dt:
|
04/16/2009
| | | | |
Title:
|
DIAGNOSTIC METHOD FOR ROOT-CAUSE ANALYSIS OF FET PERFORMANCE VARIATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2010
|
Application #:
|
11871484
|
Filing Dt:
|
10/12/2007
|
Publication #:
|
|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
PROGRAMMABLE RANDOM LOGIC ARRAYS USING PN ISOLATION
|
|