|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11923919
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
HIGH-PERFORMANCE FET DEVICE LAYOUT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11923924
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
05/08/2008
| | | | |
Title:
|
OPTICALLY CONNECTABLE CIRCUIT BOARD WITH OPTICAL COMPONENT(S) MOUNTED THEREON
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2009
|
Application #:
|
11923956
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
05/29/2008
| | | | |
Title:
|
OPTICALLY CONNECTABLE CIRCUIT BOARD WITH OPTICAL COMPONENT(S) MOUNTED THEREON
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11923965
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
METHOD TO ELIMINATE ARSENIC CONTAMINATION IN TRENCH CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2009
|
Application #:
|
11924005
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
09/25/2008
| | | | |
Title:
|
NEGATIVE RESISTS BASED ON ACID-CATALYZED ELIMINATION OF POLAR MOLECULES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11924015
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXIAL COMPRESSIVE STRAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2008
|
Application #:
|
11924024
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> SI UNDER BIAXIAL COMPRESSIVE STRAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2010
|
Application #:
|
11924045
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
DUAL WORKFUNCTION SILICIDE DIODE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2010
|
Application #:
|
11924053
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
INTEGRATION SCHEME FOR MULTIPLE METAL GATE WORK FUNCTION STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2011
|
Application #:
|
11924059
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
SRAM CELL HAVING A RECTANGULAR COMBINED ACTIVE AREA FOR PLANAR PASS GATE AND PLANAR PULL-DOWN NFETS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2011
|
Application #:
|
11924073
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
SELF ALIGNED RING ELECTRODES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
11924207
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
METHOD FOR FABRICATING SIGE-ON-INSULATOR (SGOI) AND GE-ON-INSULATOR (GOI) SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
11924239
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
HIGH SPEED DATA CHANNEL INCLUDING A CMOS VCSEL DRIVER AND A HIGH PERFORMANCE PHOTODETECTOR AND CMOS PHOTORECEIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2009
|
Application #:
|
11924283
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
HIGH SPEED DATA CHANNEL INCLUDING A CMOS VCSEL DRIVER AND A HIGH PERFORMANCE PHOTODETECTOR AND CMOS PHOTORECEIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
11924650
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH ASYMMETRIC GATE DIELECTRIC PROFILE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
11924651
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
05/22/2008
| | | | |
Title:
|
CUT-AND-PASTE IMPRINT LITHOGRAPHIC MOLD AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
11924662
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
SUBSTRATE ANCHOR STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
11924735
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
TECHNIQUES FOR IMPEDING REVERSE ENGINEERING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11924807
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
VERTICAL PARALLEL PLATE CAPACITOR USING SPACER SHAPED ELECTRODES AND METHOD FOR FABRICATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2009
|
Application #:
|
11924825
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
METHOD FOR PRODUCING A DOPED NITRIDE FILM, DOPED OXIDE FILM AND OTHER DOPED FILMS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11924875
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
METHODS FOR FABRICATING A SEMICONDUCTOR STRUCTURE USING A MANDREL AND SEMICONDUCTOR STRUCTURES FORMED THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
11924894
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT CHIP UTILIZING ORIENTED CARBON NANOTUBE CONDUCTIVE LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2011
|
Application #:
|
11924935
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11924955
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
DETERMINING HISTORY STATE OF DATA IN DATA RETAINING DEVICE BASED ON STATE OF PARTIALLY DEPLETED SILICON-ON-INSULATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2012
|
Application #:
|
11925069
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
METHOD FOR FABRICATING SUPER-STEEP RETROGRADE WELL MOSFET ON SOI OR BULK SILICON SUBSTRATE, AND DEVICE FABRICATED IN ACCORDANCE WITH THE METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
11925077
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
Method, Apparatus and Computer Program Product for Rule-Based Directed Problem Resolution for Servers with Scalable Proactive Monitoring
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11925088
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
STRAINED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ON ROTATED WAFERS AND METHODS THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2009
|
Application #:
|
11925161
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
05/08/2008
| | | | |
Title:
|
INTERCONNECT STRUCTURE WITH A BARRIER-REDUNDANCY FEATURE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
11925164
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
ELECTRICAL FUSE HAVING A FULLY SILICIDED FUSELINK AND ENHANCED FLUX DIVERGENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2009
|
Application #:
|
11925168
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
STRUCTURE AND METHOD FOR FABRICATING SELF-ALIGNED METAL CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11925170
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
OPTOELECTRONIC DEVICE WITH GERMANIUM PHOTODETECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
11925238
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
METHOD AND SYSTEM TO REDISTRIBUTE WHITE SPACE FOR MINIMIZING WIRE LENGTH
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11925387
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
Title:
|
Integrated Fin-Local Interconnect Structure
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11925413
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
Title:
|
Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2010
|
Application #:
|
11925425
|
Filing Dt:
|
10/26/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
COLLABORATIVE TROUBLESHOOTING COMPUTER SYSTEMS USING FAULT TREE ANALYSIS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11925983
|
Filing Dt:
|
10/28/2007
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
SOI BIPOLAR TRANSISTORS WITH REDUCED SELF HEATING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
11926025
|
Filing Dt:
|
10/28/2007
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
Title:
|
ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2009
|
Application #:
|
11926031
|
Filing Dt:
|
10/28/2007
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2009
|
Application #:
|
11926289
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
IC DESIGN MODELING ALLOWING DIMENSION-DEPENDENT RULE CHECKING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
11926297
|
Filing Dt:
|
10/29/2007
|
Title:
|
DESIGN STRUCTURE FOR MEMORY ARRAY REPAIR WHERE REPAIR LOGIC CANNOT OPERATE AT SAME OPERATING CONDITION AS ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
11926399
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
ONE-TRANSISTOR STATIC RANDOM ACCESS MEMORY WITH INTEGRATED VERTICAL PNPN DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
11926556
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
SYSTEM TO IMPROVE REQUIREMENTS, DESIGN MANUFACTURING, AND TRANSPORTATION IN MASS MANUFACTURING INDUSTRIES THROUGH ANALYSIS OF DEFECT DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
11926567
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
SYSTEM AND METHOD OF AUTOMATED WIRE AND VIA LAYOUT OPTIMIZATION DESCRIPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2010
|
Application #:
|
11926613
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
METHOD FOR FABRICATING STRAINED SILICON-ON-INSULATOR STRUCTURES AND STRAINED SILICON-ON-INSULATOR STRUCTURES FORMED THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
11926627
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
METHODS OF FABRICATING VERTICAL CARBON NANOTUBE FIELD EFFECT TRANSISTORS FOR ARRANGEMENT IN ARRAYS AND FIELD EFFECT TRANSISTORS AND ARRAYS FORMED THEREBY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11926635
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
METHOD TO IMPROVE REQUIREMENTS, DESIGN MANUFACTURING, AND TRANSPORTATION IN MASS MANUFACTURING INDUSTRIES THROUGH ANALYSIS OF DEFECT DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
11926661
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
09/18/2008
| | | | |
Title:
|
VERTICAL NANOTUBE SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2009
|
Application #:
|
11926689
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
VOLTAGE CONTROLLED STATIC RANDOM ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
11926722
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
FORMING SURFACE FEATURES USING SELF-ASSEMBLING MASKS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11926781
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
Techniques Supporting Collaborative Product Development
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2009
|
Application #:
|
11927006
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
STRAINED SI MOSFET ON TENSILE-STRAINED SIGE-ON-INSULATOR (SGOI)
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2012
|
Application #:
|
11927073
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
A ROBUST SPECTRAL ANALYZER FOR ONE-DIMENSIONAL AND MULTI-DIMENSIONAL DATA ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
11927110
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES INTEGRATING DAMASCENE-BODY FINFET'S AND PLANAR DEVICES ON A COMMON SUBSTRATE AND METHODS FOR FORMING SUCH SEMICONDUCTOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2010
|
Application #:
|
11927135
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES FOR LATCH-UP SUPPRESSION AND METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
11927720
|
Filing Dt:
|
12/11/2007
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
Title:
|
TOPOLOGIES AND METHODOLOGIES FOR AMS INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11927749
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
METHOD TO FABRICATE METAL GATE HIGH-K DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11927774
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
11927780
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES INTEGRATING DAMASCENE-BODY FINFET'S AND PLANAR DEVICES ON A COMMON SUBSTRATE AND METHODS FOR FORMING SUCH SEMICONDUCTOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2010
|
Application #:
|
11927964
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
TECHNIQUES FOR ENABLING MULTIPLE VT DEVICES USING HIGH-K METAL GATE STACKS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
11928070
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS USING DIFFERENTIAL SIGNALING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11928093
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR AN AUTOMATED REAL-TIME FREQUENCY BAND SELECTION CIRCUIT FOR USE WITH A VOLTAGE CONTROLLED OSCILLATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
11928135
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES WITH BODY CONTACTS AND FABRICATION METHODS THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2008
|
Application #:
|
11928205
|
Filing Dt:
|
10/30/2007
|
Title:
|
METHOD AND APPARATUS FOR EXTENDING LIFETIME RELIABILITY OF DIGITAL LOGIC DEVICES THROUGH REVERSAL OF AGING MECHANISMS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2008
|
Application #:
|
11928232
|
Filing Dt:
|
10/30/2007
|
Title:
|
METHOD AND APPARATUS FOR EXTENDING LIFETIME RELIABILITY OF DIGITAL LOGIC DEVICES THROUGH REMOVAL OF AGING MECHANISMS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2010
|
Application #:
|
11928356
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
MOSFETS COMPRISING SOURCE/DRAIN RECESSES WITH SLANTED SIDEWALL SURFACES, AND METHODS FOR FABRICATING THE SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11928391
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
SCALABLE HIGH-K DIELECTRIC GATE STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
11928395
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
HYBRID ORIENTATION SEMICONDUCTOR STRUCTURE WITH REDUCED BOUNDARY DEFECTS AND METHOD OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
11928418
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
HIGH DENSITY SRAM CELL WITH HYBRID DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11928523
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
Techniques for Linking Non-Coding and Gene-Coding Deoxyribonucleic Acid Sequences and Applications Thereof
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11928539
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
Changing Chip Function Based on Fuse States
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2010
|
Application #:
|
11928583
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
ANTI-HALO COMPENSATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2011
|
Application #:
|
11928611
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
TECHNIQUES FOR LINKING NON-CODING AND GENE-CODING DEOXYRIBONUCLEIC ACID SEQUENCES AND APPLICATIONS THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2010
|
Application #:
|
11928615
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
METHOD OF FABRICATING HIGH-DENSITY, TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
11928787
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
METHOD FOR FORMING A MULTI-GATE DEVICE WITH HIGH K DIELECTRIC FOR CHANNEL TOP SURFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2008
|
Application #:
|
11929106
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
COPLANAR SILICON-ON-INSULATOR (SOI) REGIONS OF DIFFERENT CRYSTAL ORIENTATIONS AND METHODS OF MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2009
|
Application #:
|
11929490
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
COPLANAR SILICON-ON-INSULATOR (SOI) REGIONS OF DIFFERENT CRYSTAL ORIENTATIONS AND METHODS OF MAKING THE SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929634
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929662
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929676
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
11929694
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
HIGH-VOLTAGE SILICON-ON-INSULATOR TRANSISTORS AND METHODS OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929697
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929711
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/22/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929736
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929754
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/08/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929768
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/22/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929783
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929806
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/22/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929821
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/22/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929839
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929853
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/22/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929873
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929883
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929899
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/08/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929911
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929924
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/22/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929934
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2011
|
Application #:
|
11929943
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
EMBEDDED DRAM INTEGRATED CIRCUITS WITH EXTREMELY THIN SILICON-ON-INSULATOR PASS TRANSISTORS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929944
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/29/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929956
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929962
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|