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Patent #:
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11/09/2004
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10224102
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Filing Dt:
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08/20/2002
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Publication #:
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01/02/2003
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Title:
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05/31/2005
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10224341
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08/21/2002
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02/26/2004
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Title:
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BURIED TRANSISTORS FOR SILICON ON INSULATOR TECHNOLOGY
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08/31/2004
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10224451
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08/21/2002
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02/26/2004
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Title:
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HIGH SPEED WORDLINE DECODER FOR DRIVING A LONG WORDLINE
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12/02/2003
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10224702
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08/21/2002
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Title:
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VERTICAL FLASH MEMORY CELL WITH BURIED SOURCE RAIL
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11/30/2004
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10224771
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08/21/2002
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02/26/2004
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Title:
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NICKEL BONDING CAP OVER COPPER METALIZED BONDPADS
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07/13/2004
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10224915
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08/21/2002
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02/26/2004
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Title:
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HIGH COUPLING FLOATING GATE TRANSISTOR
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07/06/2004
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10224950
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08/20/2002
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12/19/2002
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Title:
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APPARATUS AND STRUCTURE FOR RAPID ENABLEMENT
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02/10/2004
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10224989
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08/20/2002
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02/20/2003
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Title:
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CANCELLATION OF REDUNDANT ELEMENTS WITH A CANCEL BANK
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03/28/2006
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10225190
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08/22/2002
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02/26/2004
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Title:
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METHOD OF MANUFACTURE OF A RESISTANCE VARIABLE MEMORY CELL
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08/05/2003
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10225315
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08/20/2002
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04/03/2003
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Title:
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PROCESS FOR MANUFACTURING ELECTRONIC DEVICES COMPRISING NONVOLATILE MEMORY CELLS OF REDUCED DIMENSIONS
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03/22/2005
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10225428
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08/22/2002
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02/26/2004
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Title:
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DUAL-SIDED CAPACITOR
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02/03/2004
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10225513
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08/20/2002
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04/10/2003
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Title:
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EEPROM FLASH MEMORY ERASABLE LINE BY LINE
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06/15/2004
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10225570
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08/20/2002
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09/25/2003
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Title:
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MAGNETIC TUNNELING JUNCTION ANTIFUSE DEVICE
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05/25/2004
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10225575
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08/21/2002
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Pub Dt:
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02/26/2004
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Title:
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PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR ASSEMBLING MICROELECTRONIC DEVICES
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02/24/2004
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10225584
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08/21/2002
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Pub Dt:
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02/26/2004
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Title:
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DUAL-DAMASCENE BIT LINE STRUCTURES FOR MICROELECTRONIC DEVICES AND METHODS OF FABRICATING MICROELECTRONIC DEVICES
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09/07/2004
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10225606
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08/22/2002
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Pub Dt:
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12/26/2002
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Title:
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MULTILEVEL LEADFRAME FOR A PACKAGED INTEGRATED CIRCUIT AND METHOD OF FABRICATION
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09/28/2004
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10225907
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08/21/2002
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04/10/2003
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Title:
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CIRCUIT BOARDS CONTAINING VIAS AND METHODS FOR PRODUCING SAME
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08/09/2005
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10226070
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08/22/2002
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02/26/2004
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Title:
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MULTI-DIE SEMICONDUCTOR PACKAGE
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11/29/2005
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10226283
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08/23/2002
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Pub Dt:
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02/26/2004
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Title:
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SOI DEVICE HAVING INCREASED RELIABILITY AND REDUCED FREE FLOATING BODY EFFECTS
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12/06/2005
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10226327
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08/23/2002
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02/26/2004
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Title:
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RESET VOLTAGE GENERATION CIRCUIT FOR CMOS IMAGERS
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05/10/2005
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10226472
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08/23/2002
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02/26/2004
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Title:
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SEMICONDUCTOR COMPONENT WITH ON BOARD CAPACITOR AND METHOD OF FABRICATION
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04/06/2004
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10226488
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08/22/2002
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02/26/2004
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Title:
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01/25/2005
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10226509
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08/22/2002
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02/26/2004
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Title:
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APPARATUS AND METHOD FOR DEPOSITING AND REFLOWING SOLDER PASTE ON A MICROELECTRONIC WORKPIECE
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04/26/2005
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10226573
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08/23/2002
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02/26/2004
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Title:
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REACTORS HAVING GAS DISTRIBUTORS AND METHODS FOR DEPOSITING MATERIALS ONTO MICRO-DEVICE WORKPIECES
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04/27/2004
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10226782
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08/23/2002
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02/26/2004
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Title:
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CONTROLLING A DELAY LOCK LOOP CIRCUIT
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07/08/2003
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10226849
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08/22/2002
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Title:
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DEPOSITION AND CHAMBER TREATMENT METHODS
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09/14/2004
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10227240
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08/26/2002
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02/26/2004
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Title:
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POWER REDUCTION IN CMOS IMAGERS BY TRIMMING OF MASTER CURRENT REFERENCE
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05/11/2004
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10227317
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08/23/2002
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01/02/2003
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METHOD AND APPARATUS FOR MARKING A BARE SEMICONDUCTOR DIE
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02/24/2004
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10227329
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08/23/2002
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02/26/2004
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08/05/2003
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10227369
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08/23/2002
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12/26/2002
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METHOD FOR GRAVITATION-ASSISTED CONTROL OF SPREAD OF VISCOUS MATERIAL APPLIED TO A SUBSTRATE
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05/03/2005
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10227608
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08/23/2002
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12/25/2003
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VOLTAGE LEVEL SHIFTING CIRCUIT WITH IMPROVED SWITCHING SPEED
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08/19/2003
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10227699
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08/26/2002
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01/02/2003
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FORMATION OF METAL OXIDE GATE DIELECTRIC
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02/22/2005
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10227734
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08/26/2002
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02/26/2004
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PRECONDITIONING GLOBAL BITLINES
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10/26/2004
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10227965
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08/26/2002
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02/26/2004
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HIGH SPEED LOW VOLTAGE DRIVER
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01/13/2004
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10228062
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08/27/2002
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MRAM MEMORY ELEMENT
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08/02/2005
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10228116
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08/26/2002
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02/26/2004
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SELECTIVELY CONFIGURABLE MICROELECTRONIC PROBES
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01/11/2005
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10228597
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08/27/2002
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03/04/2004
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METHOD AND APPARATUS FOR ERASING MEMORY
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03/17/2009
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10228617
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08/26/2002
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10/21/2004
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METHOD FOR PACKAGING A TAPE SUBSTRATE
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08/03/2004
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10228619
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08/27/2002
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03/04/2004
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MAGNETIC NON-VOLATILE MEMORY COIL LAYOUT ARCHITECTURE AND PROCESS INTEGRATION SCHEME
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05/17/2005
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10228695
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08/26/2002
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02/20/2003
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FIELD CORRECTION OF OVERLAY ERROR
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12/23/2003
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10228697
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08/26/2002
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12/19/2002
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METHOD AND APPARATUS FOR REDUCING FIXED CHARGE IN SEMICONDUCTOR DEVICE LAYERS
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12/06/2005
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10228703
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08/27/2002
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03/04/2004
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PSEUDO CMOS DYNAMIC LOGIC WITH DELAYED CLOCKS
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05/25/2004
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10228704
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08/27/2002
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03/04/2004
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DIFFERENTIAL AMPLIFIER COMMON MODE NOISE COMPENSATION
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02/24/2004
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10228732
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08/27/2002
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01/02/2003
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METHODS, STRUCTURES, AND CIRCUITS FOR TRANSISTORS WITH GATE-TO-BODY CAPACITIVE COUPLING
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07/05/2005
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10228771
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08/27/2002
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02/12/2004
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TEMPORARY, CONFORMABLE CONTACTS FOR MICROELECTRONIC COMPONENTS
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05/24/2005
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10228823
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08/27/2002
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03/27/2003
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METAL-POLY INTEGRATED CAPACITOR STRUCTURE
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06/15/2004
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10228824
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08/27/2002
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03/20/2003
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FLASH MEMORY ARRAY ARCHITECTURE
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01/23/2007
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08/26/2002
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02/26/2004
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CROSS DIFFUSION BARRIER LAYER IN POLYSILICON
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01/11/2005
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10228864
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08/26/2002
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02/20/2003
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FIELD CORRECTION OF OVERLAY ERROR
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09/19/2006
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10228947
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08/28/2002
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03/04/2004
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AUTOMATIC COLOR CONSTANCY FOR IMAGE SENSORS
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07/19/2005
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10229136
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08/28/2002
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03/04/2004
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04/19/2005
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10229139
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08/28/2002
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03/04/2004
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DEVICE HAVING REDUCED DIFFUSION THROUGH FERROMAGNETIC MATERIALS
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08/23/2005
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10229330
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08/27/2002
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03/04/2004
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METHOD AND APPARATUS FOR DESIGNING A PATTERN ON A SEMICONDUCTOR SURFACE
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06/29/2004
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10229336
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08/26/2002
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02/26/2004
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SEMICONDUCTOR CONSTRUCTIONS
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02/24/2004
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10229364
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08/27/2002
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03/27/2003
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TEMPERATURE AND VOLTAGE COMPENSATED REFERENCE CURRENT GENERATOR
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12/30/2003
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10229399
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08/27/2002
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03/27/2003
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HIGH VOLTAGE LOW POWER SENSING DEVICE FOR FLASH MEMORY
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01/20/2004
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10229476
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08/28/2002
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VERTICAL FLOATING GATE TRANSISTOR
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10/25/2005
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10229627
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08/28/2002
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03/04/2004
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SYSTEMS AND METHODS FOR FORMING METAL OXIDES USING METAL ORGANO-AMINES AND METAL ORGANO-OXIDES
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08/31/2004
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10229653
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08/28/2002
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03/04/2004
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SYSTEMS AND METHODS FOR FORMING REFRACTORY METAL OXIDE LAYERS
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05/30/2006
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10229702
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08/28/2002
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03/04/2004
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OUTPUT DATA COMPRESSION SCHEME USING TRI-STATE
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Issue Dt:
|
09/26/2006
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Application #:
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10229779
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
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07/28/2005
| | | | |
Title:
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SYSTEMS AND METHODS FOR FORMING ZIRCONIUM AND/OR HAFNIUM-CONTAINING LAYERS
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Patent #:
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Issue Dt:
|
09/28/2004
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Application #:
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10229824
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
Title:
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VERTICALLY INTEGRATED FLASH MEMORY CELL AND METHOD OF FABRICATING A VERTICALLY INTEGRATED FLASH MEMORY CELL
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Patent #:
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Issue Dt:
|
07/26/2005
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Application #:
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10229835
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
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01/02/2003
| | | | |
Title:
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A METHOD FOR A SEMICONDUCTOR ASSEMBLY HAVING A SEMICDUCTOR DIE WITH HEAT SPREADERS
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Patent #:
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Issue Dt:
|
06/14/2005
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Application #:
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10229837
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
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01/09/2003
| | | | |
Title:
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THIN FLIP-CHIP METHOD
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Patent #:
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Issue Dt:
|
08/08/2006
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Application #:
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10229841
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
Title:
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SYSTEMS AND METHODS FOR FORMING METAL OXIDES USING METAL COMPOUNDS CONTAINING AMINOSILANE LIGANDS
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Patent #:
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Issue Dt:
|
11/23/2004
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Application #:
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10229865
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
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01/09/2003
| | | | |
Title:
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INTEGRATED CIRCUITRY
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Patent #:
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Issue Dt:
|
12/04/2007
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Application #:
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10229866
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
|
03/04/2004
| | | | |
Title:
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METHOD AND SYSTEM FOR TRANSFERRING DATA TO AN ELECTRONIC TOY OR OTHER ELECTRONIC DEVICE
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Patent #:
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Issue Dt:
|
11/16/2004
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Application #:
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10229886
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
|
07/24/2003
| | | | |
Title:
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SEMICONDUCTOR CONSTRUCTIONS
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Patent #:
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Issue Dt:
|
01/06/2004
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Application #:
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10229887
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Filing Dt:
|
08/27/2002
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Title:
|
ATOMIC LAYER DEPOSITION METHODS
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Patent #:
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Issue Dt:
|
05/24/2005
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Application #:
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10229901
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
|
05/15/2003
| | | | |
Title:
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VOLTAGE CLAMP CIRCUIT
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Patent #:
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Issue Dt:
|
01/17/2006
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Application #:
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10229908
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
|
03/04/2004
| | | | |
Title:
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MULTIPLE CHIP SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SAME
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|
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Patent #:
|
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Issue Dt:
|
11/15/2005
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Application #:
|
10229914
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Filing Dt:
|
08/27/2002
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Publication #:
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Pub Dt:
|
03/04/2004
| | | | |
Title:
|
MULTI-CHIP WAFER LEVEL SYSTEM PACKAGES AND METHODS OF FORMING SAME
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|
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Patent #:
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Issue Dt:
|
08/02/2005
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Application #:
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10229920
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
|
03/27/2003
| | | | |
Title:
|
CONDITIONED AND ROBUST ULTRA-LOW POWER POWER-ON RESET SEQUENCER FOR INTEGRATED CIRCUITS
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|
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Patent #:
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Issue Dt:
|
04/06/2004
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Application #:
|
10229921
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Filing Dt:
|
08/28/2002
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Publication #:
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Pub Dt:
|
04/03/2003
| | | | |
Title:
|
FLASH MEMORY SECTOR TAGGING FOR CONSECUTIVE SECTOR ERASE OR BANK ERASE
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|
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Patent #:
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|
Issue Dt:
|
03/29/2005
|
Application #:
|
10229968
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Filing Dt:
|
08/28/2002
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Publication #:
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|
Pub Dt:
|
01/09/2003
| | | | |
Title:
|
DIE STACKING SCHEME
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|
|
Patent #:
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|
Issue Dt:
|
03/22/2005
|
Application #:
|
10229969
|
Filing Dt:
|
08/28/2002
|
Publication #:
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|
Pub Dt:
|
01/09/2003
| | | | |
Title:
|
SEMICONDUCTOR/PRINTED CIRCUIT BOARD ASSEMBLY, AND COMPUTER SYSTEM
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|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10230005
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Filing Dt:
|
08/28/2002
|
Publication #:
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|
Pub Dt:
|
04/10/2003
| | | | |
Title:
|
PACKAGED STACKED SEMICONDUCTOR DIE AND METHOD OF PREPARING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2004
|
Application #:
|
10230131
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Filing Dt:
|
08/28/2002
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Publication #:
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|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
SYSTEMS AND METHODS FOR FORMING STRONTIUM- AND/OR BARIUM-CONTAINING LAYERS
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|
|
Patent #:
|
|
Issue Dt:
|
01/16/2007
|
Application #:
|
10230189
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
METHOD OF FORMING A RESISTANCE VARIABLE MEMORY ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
10230191
|
Filing Dt:
|
08/29/2002
|
Publication #:
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Pub Dt:
|
03/04/2004
| | | | |
Title:
|
METHOD TO ISOLATE DEVICE LAYER EDGES THROUGH MECHANICAL SPACING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
10230193
|
Filing Dt:
|
08/28/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
SYSTEMS AND METHODS FOR FORMING METAL OXIDES USING METAL DIKETONATES AND/OR KETOIMINES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2004
|
Application #:
|
10230203
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
REVERSE METAL PROCESS FOR CREATING A METAL SILICIDE TRANSISTOR GATE STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10230211
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
MEMORY TECHNOLOGY TEST APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2004
|
Application #:
|
10230300
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
MRAM SENSE LAYER AREA CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10230327
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/18/2004
| | | | |
Title:
|
GRADED GEXSE100-X CONCENTRATION IN PCRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
10230355
|
Filing Dt:
|
08/28/2002
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
Title:
|
ULTRA LOW POWER TRACKED LOW VOLTAGE REFERENCE SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10230459
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
METHODS FOR WAFER-LEVEL PACKAGING OF MICROELECTRONIC DEVICES AND MICROELECTRONIC DEVICES FORMED BY SUCH METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
10230523
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
DOUBLE-DOPED POLYSILICON FLOATING GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10230546
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
METHOD AND APPARATUS FOR LATENCY SPECIFIC DUTY CYCLE CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10230553
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
INPUT BUFFER WITH SELECTABLE OPERATIONAL CHARACTERISTICS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
10230568
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
ANNULAR GATE AND TECHNIQUE FOR FABRICATING AN ANNULAR GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2005
|
Application #:
|
10230569
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
Title:
|
METHODS OF FABRICATING A MOLDED BALL GRID ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2005
|
Application #:
|
10230570
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
METHOD OF ETCHING MATERIALS PATTERNED WITH A SINGLE LAYER 193NM RESIST
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
10230592
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
METHOD AND SYSTEM FOR BINDING HALIDE-BASED CONTAMINANTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
10230602
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
METHOD AND APPARATUS FOR SIMULTANEOUSLY REMOVING MULTIPLE CONDUCTIVE MATERIALS FROM MICROELECTRONIC SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2004
|
Application #:
|
10230605
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
PLATINUM STUFFED WITH SILICON OXIDE AS A DIFFUSION OXYGEN BARRIER FOR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2005
|
Application #:
|
10230615
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
PLANARITY DIAGNOSTIC SYSTEM, E.G., FOR MICROELECTRONIC COMPONENT TEST SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2004
|
Application #:
|
10230616
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
02/19/2004
| | | | |
Title:
|
PACKAGED MICROELECTRONIC COMPONENT ASSEMBLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10230628
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
METHOD AND APPARATUS FOR REMOVING ADJACENT CONDUCTIVE AND NONCONDUCTIVE MATERIALS OF A MICROELECTRONIC SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
10230637
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
Title:
|
CURRENT LIMITING ANTIFUSE PROGRAMMING PATH
|
|