|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929968
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929976
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/08/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929982
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/08/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929991
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/22/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11929999
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11930005
|
Filing Dt:
|
02/01/2008
|
Publication #:
|
|
Pub Dt:
|
05/22/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11930010
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11930016
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11930019
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/08/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11930026
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11930033
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11930039
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11930045
|
Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
05/08/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11930231
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR POINT OF CARE OSMOLARITY TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2012
|
Application #:
|
11930236
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
SOLUTION FOR FORMING POLISHING SLURRY, POLISHING SLURRY AND RELATED METHODS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11930270
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR POINT OF CARE OSMOLARITY TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
11930633
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
METHOD AND SYSTEM FOR REAL-TIME ESTIMATION AND PREDICTION OF THE THERMAL STATE OF A MICROPROCESSOR UNIT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11930638
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
05/08/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11930654
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
05/29/2008
| | | | |
Title:
|
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
11930820
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
METHOD AND SYSTEM FOR LOGIC VERIFICATION USING MIRROR INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
11930924
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
11930975
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
RECEIVER TERMINATION CIRCUIT FOR A HIGH SPEED DIRECT CURRENT (DC) SERIAL LINK
|
|
|
Patent #:
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|
Issue Dt:
|
01/19/2010
|
Application #:
|
11931033
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
METAL-GATED MOSFET DEVICES HAVING SCALED GATE STACK THICKNESS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
11931096
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
FULLY AUTOMATED PASTE DISPENSE SYSTEM FOR DISPENSING SMALL DOTS AND LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
11931112
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
UNIFORM RECESS OF A MATERIAL IN A TRENCH INDEPENDENT OF INCOMING TOPOGRAPHY
|
|
|
Patent #:
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|
Issue Dt:
|
12/07/2010
|
Application #:
|
11931144
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
MECHANISM FOR DETECTION AND COMPENSATION OF NBTI INDUCED THRESHOLD DEGRADATION
|
|
|
Patent #:
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|
Issue Dt:
|
02/15/2011
|
Application #:
|
11931153
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
FULLY AUTOMATED PASTE DISPENSE SYSTEM FOR DISPENSING SMALL DOTS AND LINES
|
|
|
Patent #:
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|
Issue Dt:
|
04/21/2009
|
Application #:
|
11931194
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
CRACK STOP FOR LOW K DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2010
|
Application #:
|
11931209
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
11931217
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
FULLY AUTOMATED PASTE DISPENSE SYSTEM FOR DISPENSING SMALL DOTS AND LINES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11931230
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
10/02/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR FABRICATING OR ALTERING MICROSTRUCTURES USING LOCAL CHEMICAL ALTERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
11931238
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
VERTICAL SOI TRANSISTOR MEMORY CELL AND METHOD OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2012
|
Application #:
|
11931242
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR FABRICATING OR ALTERING MICROSTRUCTURES USING LOCAL CHEMICAL ALTERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
11931296
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
MOMENT ANALYSIS OF TERTIARY PROTEIN STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2011
|
Application #:
|
11931371
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
HIGH RESISTIVITY SOI BASE WAFER USING THERMALLY ANNEALED SUBSTRATE
|
|
|
Patent #:
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|
Issue Dt:
|
01/13/2009
|
Application #:
|
11931387
|
Filing Dt:
|
10/31/2007
|
Publication #:
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|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI CMOS DEVICES BY GATE STRESS ENGINEERING WITH SIGE AND/OR SI:C
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2010
|
Application #:
|
11931626
|
Filing Dt:
|
10/31/2007
|
Publication #:
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|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR A FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11931634
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
STRUCTURE FOR UNIFORM TRIGGERING OF MULTIFINGER SEMICONDUCTOR DEVICES WITH TUNABLE TRIGGER VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2010
|
Application #:
|
11931836
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
PATTERNED STRAINED SEMICONDUCTOR SUBSTRATE AND DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2009
|
Application #:
|
11932385
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
NEGATIVE THERMAL EXPANSION SYSTEM (NTES) DEVICE FOR TCE COMPENSATION IN ELASTOMER COMPOSITES AND CONDUCTIVE ELASTOMER INTERCONNECTS IN MICROELECTRONIC PACKAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
11932793
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
MICROELECTRONIC DEVICES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2009
|
Application #:
|
11933505
|
Filing Dt:
|
11/01/2007
|
Publication #:
|
|
Pub Dt:
|
04/10/2008
| | | | |
Title:
|
COMPUTER-READABLE MEDIUM ENCODING A MEMORY USING A BACK-GATE CONTROLLED ASYMMETRICAL MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
11933530
|
Filing Dt:
|
11/01/2007
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
PATTERNABLE LOW DIELECTRIC CONSTANT MATERIALS AND THEIR USE IN ULSI INTERCONNECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2010
|
Application #:
|
11933571
|
Filing Dt:
|
11/01/2007
|
Publication #:
|
|
Pub Dt:
|
06/04/2009
| | | | |
Title:
|
BRIDGED GATE FINFET
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11933760
|
Filing Dt:
|
11/01/2007
|
Publication #:
|
|
Pub Dt:
|
05/07/2009
| | | | |
Title:
|
SELF-ASSEMBLED MATERIAL PATTERN TRANSFER CONTRAST ENHANCEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
11934479
|
Filing Dt:
|
11/02/2007
|
Publication #:
|
|
Pub Dt:
|
05/07/2009
| | | | |
Title:
|
STRAINED SEMICONDUCTOR-ON-INSULATOR BY SI:C COMBINED WITH POROUS PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2011
|
Application #:
|
11934804
|
Filing Dt:
|
11/05/2007
|
Publication #:
|
|
Pub Dt:
|
05/07/2009
| | | | |
Title:
|
STRUCTURE FOR SYSTEM ARCHITECTURES FOR AND METHODS OF SCHEDULING ON-CHIP AND ACROSS-CHIP NOISE EVENTS IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
11934995
|
Filing Dt:
|
11/05/2007
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
CHIP HAVING TIMING ANALYSIS OF PATHS PERFORMED WITHIN THE CHIP DURING THE DESIGN PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
11935143
|
Filing Dt:
|
11/05/2007
|
Publication #:
|
|
Pub Dt:
|
05/07/2009
| | | | |
Title:
|
CMOS EPROM AND EEPROM DEVICES AND PROGRAMMABLE CMOS INVERTERS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2010
|
Application #:
|
11935566
|
Filing Dt:
|
11/06/2007
|
Publication #:
|
|
Pub Dt:
|
05/07/2009
| | | | |
Title:
|
STORAGE ARRAY INCLUDING A LOCAL CLOCK BUFFER WITH PROGRAMMABLE TIMING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
11935612
|
Filing Dt:
|
11/06/2007
|
Publication #:
|
|
Pub Dt:
|
05/07/2009
| | | | |
Title:
|
DESIGN STRUCTURE INCLUDING TRANSISTOR HAVING GATE AND BODY IN DIRECT SELF-ALIGNED CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2010
|
Application #:
|
11935698
|
Filing Dt:
|
11/06/2007
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
POST STI TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11935714
|
Filing Dt:
|
11/06/2007
|
Title:
|
POLYCONDUCTOR LINE END FORMATION AND RELATED MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
11935741
|
Filing Dt:
|
11/06/2007
|
Publication #:
|
|
Pub Dt:
|
05/07/2009
| | | | |
Title:
|
LEVEL SHIFTER FOR BOOSTING WORDLINE VOLTAGE AND MEMORY CELL PERFORMANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
11935834
|
Filing Dt:
|
11/06/2007
|
Publication #:
|
|
Pub Dt:
|
05/07/2009
| | | | |
Title:
|
PACKAGING SUBSTRATE HAVING PATTERN-MATCHED METAL LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2011
|
Application #:
|
11935865
|
Filing Dt:
|
11/06/2007
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
METHOD AND SYSTEM FOR CREATING, VIEWING, EDITING, AND SHARING OUTPUT FROM A DESIGN CHECKING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
11936139
|
Filing Dt:
|
11/07/2007
|
Publication #:
|
|
Pub Dt:
|
05/07/2009
| | | | |
Title:
|
APPARATUS FOR GUARANTEED WRITE THROUGH IN DOMINO READ SRAM'S
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
11936673
|
Filing Dt:
|
11/07/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
COMPUTER PROGRAM FOR BALANCING POWER PLANE PIN CURRENTS IN A PRINTED WIRING BOARD
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
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Application #:
|
11936775
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Filing Dt:
|
11/07/2007
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Publication #:
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Pub Dt:
|
03/13/2008
| | | | |
Title:
|
SYSTEMS, METHODS, AND MEDIA FOR BLOCK-BASED ASSERTION GENERATION, QUALIFICATION AND ANALYSIS
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|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
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Application #:
|
11936782
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Filing Dt:
|
11/07/2007
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Publication #:
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Pub Dt:
|
06/26/2008
| | | | |
Title:
|
REAL-TIME CONFIGURABLE MASKING
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11936785
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Filing Dt:
|
11/07/2007
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Publication #:
|
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Pub Dt:
|
05/08/2008
| | | | |
Title:
|
REAL-TIME CONFIGURABLE MASKING
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|
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Patent #:
|
|
Issue Dt:
|
03/15/2011
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Application #:
|
11936887
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Filing Dt:
|
11/08/2007
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Publication #:
|
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Pub Dt:
|
05/14/2009
| | | | |
Title:
|
UNIVERSAL PATTERNED METAL THERMAL INTERFACE
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|
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Patent #:
|
|
Issue Dt:
|
05/11/2010
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Application #:
|
11936971
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Filing Dt:
|
11/08/2007
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Publication #:
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Pub Dt:
|
03/13/2008
| | | | |
Title:
|
METROLOGY TOOL RECIPE VALIDATOR USING BEST KNOWN METHODS
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|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
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Application #:
|
11937088
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Filing Dt:
|
11/08/2007
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Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR A TRENCH CAPACITOR
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11937105
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Filing Dt:
|
11/08/2007
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Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR BRIDGE OF A SEMINCONDUCTOR INTERNAL NODE
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|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
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Application #:
|
11937106
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Filing Dt:
|
11/08/2007
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Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR DYNAMICALLY SELECTING COMPILED INSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
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Application #:
|
11937111
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Filing Dt:
|
11/08/2007
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Publication #:
|
|
Pub Dt:
|
02/12/2009
| | | | |
Title:
|
DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2009
|
Application #:
|
11937534
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Filing Dt:
|
11/09/2007
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Publication #:
|
|
Pub Dt:
|
05/29/2008
| | | | |
Title:
|
METHOD OF FABRICATION FOR SIGE HETEROJUNCTION BIPOLAR TRANSISTOR (HBT)
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2008
|
Application #:
|
11937559
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Filing Dt:
|
11/09/2007
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Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
NOISE REDUCTION IN DIGITAL SYSTEMS WHEN THE NOISE IS CAUSED BY SIMULTANEOUSLY CLOCKING DATA REGISTERS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2009
|
Application #:
|
11937637
|
Filing Dt:
|
11/09/2007
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
METHOD AND STRUCTURE FOR REDUCING INDUCED MECHANICAL STRESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
11937646
|
Filing Dt:
|
11/09/2007
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
HIGH TIN SOLDER ETCHING SOLUTION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
11938532
|
Filing Dt:
|
11/12/2007
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
METHOD AND SYSTEM FOR TESTING FUNCTIONALITY OF A CHIP CHECKER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
11938612
|
Filing Dt:
|
11/12/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
COMPUTER PROGRAM PRODUCT FOR VERIFICATION USING REACHABILITY OVERAPPROXIMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
11938656
|
Filing Dt:
|
11/12/2007
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
SYSTEM FOR VERIFICATION USING REACHABILITY OVERAPPROXIMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
11938899
|
Filing Dt:
|
11/13/2007
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
STRUCTURE FOR A SYSTEM AND METHOD OF PREDICTING POWER EVENTS IN AN INTERMITTENT POWER ENVIRONMENT AND DISPATCHING COMPUTATIONAL OPERATIONS OF AN INTEGRATED CIRCUIT ACCORDINGLY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
11939017
|
Filing Dt:
|
11/13/2007
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR CONTAINING A WIDE BAND GAP SEMICONDUCTOR MATERIAL IN A DRAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
11939574
|
Filing Dt:
|
11/14/2007
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
DENSE CHEVRON NON-PLANAR FIELD EFFECT TRANSISTORS AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2011
|
Application #:
|
11939578
|
Filing Dt:
|
11/14/2007
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
METHODS OF CHANGING THRESHOLD VOLTAGES OF SEMICONDUCTOR TRANSISTORS BY ION IMPLANTATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11939582
|
Filing Dt:
|
11/14/2007
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
DUAL WIRED INTEGRATED CIRCUIT CHIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
11939599
|
Filing Dt:
|
11/14/2007
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
CARBON NANOTUBE STRUCTURES FOR ENHANCEMENT OF THERMAL DISSIPATION FROM SEMICONDUCTOR MODULES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
11939612
|
Filing Dt:
|
11/14/2007
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2010
|
Application #:
|
11939671
|
Filing Dt:
|
11/14/2007
|
Publication #:
|
|
Pub Dt:
|
04/03/2008
| | | | |
Title:
|
BEOL INTERCONNECT STRUCTURES WITH SIMULTANEOUS HIGH-K AND LOW-K DIELECTRIC REGIONS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11940487
|
Filing Dt:
|
11/15/2007
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
Title:
|
INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
11940531
|
Filing Dt:
|
11/15/2007
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
Title:
|
STRESS-GENERATING SHALLOW TRENCH ISOLATION STRUCTURE HAVING DUAL COMPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11940711
|
Filing Dt:
|
11/15/2007
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
METHOD AND SYSTEM FOR PERFORMING HEURISTIC CONSTRAINT SIMPLIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
11940720
|
Filing Dt:
|
11/15/2007
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
Title:
|
METHOD AND APPARATUS FOR ELECTROPLATING ON SOI AND BULK SEMICONDUCTOR WAFERS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
11940755
|
Filing Dt:
|
11/15/2007
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
METHOD AND SYSTEM FOR PERFORMING HEURISTIC CONSTRAINT SIMPLIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
11941104
|
Filing Dt:
|
11/16/2007
|
Publication #:
|
|
Pub Dt:
|
04/17/2008
| | | | |
Title:
|
A DESIGN STRUCTURE WITH A DEEP SUB-COLLECTOR, A REACH-THROUGH STRUCTURE AND TRENCH ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2010
|
Application #:
|
11941161
|
Filing Dt:
|
11/16/2007
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
Title:
|
METHOD AND SYSTEM FOR DETERMINING ELEMENT VOLTAGE SELECTION CONTROL VALUES FOR A STORAGE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
11941165
|
Filing Dt:
|
11/16/2007
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
ELECTRICAL INTERCONNECTION STRUCTURE FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2009
|
Application #:
|
11941168
|
Filing Dt:
|
11/16/2007
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
Title:
|
ENERGY EFFICIENT STORAGE DEVICE USING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2010
|
Application #:
|
11941308
|
Filing Dt:
|
11/16/2007
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
Title:
|
STRUCTURE OF AN APPARATUS FOR PROGRAMMING AN ELECTRONICALLY PROGRAMMABLE SEMICONDUCTOR FUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2010
|
Application #:
|
11941342
|
Filing Dt:
|
11/16/2007
|
Publication #:
|
|
Pub Dt:
|
04/10/2008
| | | | |
Title:
|
METHODS AND CIRCUITS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW IN MULTI-THRESHOLD VOLTAGE APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2009
|
Application #:
|
11941994
|
Filing Dt:
|
11/19/2007
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
Title:
|
SYSTEM AND METHOD FOR IMPLEMENTING ROW REDUNDANCY WITH REDUCED ACCESS TIME AND REDUCED DEVICE AREA
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2010
|
Application #:
|
11942034
|
Filing Dt:
|
11/19/2007
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
METHOD OF ACHIEVING TIMING CLOSURE IN DIGITAL INTEGRATED CIRCUITS BY OPTIMIZING INDIVIDUAL MACROS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
11942061
|
Filing Dt:
|
11/19/2007
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
Title:
|
REDUCING IMPEDANCE DISCONTINUITY IN PACKAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
11942148
|
Filing Dt:
|
11/19/2007
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
SYSTEMS, METHODS, AND MEDIA FOR BLOCK-BASED ASSERTION GENERATION, QUALIFICATION AND ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
|
Application #:
|
11942270
|
Filing Dt:
|
11/19/2007
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT CHIP HAVING ON-CHIP SIGNAL INTEGRITY AND NOISE VERIFICATION USING FREQUENCY DEPENDENT RLC EXTRACTION AND MODELING TECHNIQUES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2010
|
Application #:
|
11942309
|
Filing Dt:
|
11/19/2007
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
METHODOLOGY FOR IMAGE FIDELITY VERIFICATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11942393
|
Filing Dt:
|
11/19/2007
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
Title:
|
DIRECT ELECTRODEPOSITION OF COPPER ONTO TA-ALLOY BARRIERS
|
|