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Reel/Frame:054633/0001   Pages: 1245
Recorded: 11/02/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 8468
Page 64 of 85
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
1
Patent #:
9570555
Issue Dt:
02/14/2017
Application #:
14926936
Filing Dt:
10/29/2015
Title:
SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES
2
Patent #:
9853110
Issue Dt:
12/26/2017
Application #:
14927765
Filing Dt:
10/30/2015
Publication #:
US20170125530
Pub Dt:
05/04/2017
Title:
METHOD OF FORMING A GATE CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE
3
Patent #:
10115719
Issue Dt:
10/30/2018
Application #:
14928272
Filing Dt:
10/30/2015
Publication #:
US20160126239
Pub Dt:
05/05/2016
Title:
INTEGRATED CIRCUITS WITH RESISTOR STRUCTURES FORMED FROM MIM CAPACITOR MATERIAL AND METHODS FOR FABRICATING SAME
4
Patent #:
9960284
Issue Dt:
05/01/2018
Application #:
14928595
Filing Dt:
10/30/2015
Publication #:
US20170125610
Pub Dt:
05/04/2017
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A VARACTOR
5
Patent #:
10199479
Issue Dt:
02/05/2019
Application #:
14928681
Filing Dt:
10/30/2015
Publication #:
US20160056263
Pub Dt:
02/25/2016
Title:
METHODS OF FORMING A GATE CAP LAYER ABOVE A REPLACEMENT GATE STRUCTURE
6
Patent #:
9923078
Issue Dt:
03/20/2018
Application #:
14928719
Filing Dt:
10/30/2015
Publication #:
US20170125543
Pub Dt:
05/04/2017
Title:
TRENCH SILICIDE CONTACTS WITH HIGH SELECTIVITY PROCESS
7
Patent #:
9536982
Issue Dt:
01/03/2017
Application #:
14930895
Filing Dt:
11/03/2015
Title:
ETCH STOP FOR AIRGAP PROTECTION
8
Patent #:
NONE
Issue Dt:
Application #:
14931277
Filing Dt:
11/03/2015
Publication #:
US20160064250
Pub Dt:
03/03/2016
Title:
METHODS OF FORMING METASTABLE REPLACEMENT FINS FOR A FINFET SEMICONDUCTOR DEVICE BY PERFORMING A REPLACEMENT GROWTH PROCESS
9
Patent #:
10161915
Issue Dt:
12/25/2018
Application #:
14932372
Filing Dt:
11/04/2015
Publication #:
US20170122913
Pub Dt:
05/04/2017
Title:
IN-SITU CONTACTLESS MONITORING OF PHOTOMASK PELLICLE DEGRADATION
10
Patent #:
9419101
Issue Dt:
08/16/2016
Application #:
14932394
Filing Dt:
11/04/2015
Title:
MULTI-LAYER SPACER USED IN FINFET
11
Patent #:
10263065
Issue Dt:
04/16/2019
Application #:
14932441
Filing Dt:
11/04/2015
Publication #:
US20170125509
Pub Dt:
05/04/2017
Title:
METAL RESISTOR FORMING METHOD USING ION IMPLANTATION
12
Patent #:
9673115
Issue Dt:
06/06/2017
Application #:
14933107
Filing Dt:
11/05/2015
Publication #:
US20170133287
Pub Dt:
05/11/2017
Title:
TEST STRUCTURES AND METHOD OF FORMING AN ACCORDING TEST STRUCTURE
13
Patent #:
9905460
Issue Dt:
02/27/2018
Application #:
14933650
Filing Dt:
11/05/2015
Publication #:
US20170133325
Pub Dt:
05/11/2017
Title:
METHODS OF SELF-FORMING BARRIER FORMATION IN METAL INTERCONNECTION APPLICATIONS
14
Patent #:
9798088
Issue Dt:
10/24/2017
Application #:
14933668
Filing Dt:
11/05/2015
Publication #:
US20170131476
Pub Dt:
05/11/2017
Title:
BARRIER STRUCTURES FOR UNDERFILL BLOCKOUT REGIONS
15
Patent #:
9368513
Issue Dt:
06/14/2016
Application #:
14934369
Filing Dt:
11/06/2015
Publication #:
US20160071886
Pub Dt:
03/10/2016
Title:
HIGHLY CONFORMAL EXTENSION DOPING IN ADVANCED MULTI-GATE DEVICES
16
Patent #:
9906213
Issue Dt:
02/27/2018
Application #:
14934793
Filing Dt:
11/06/2015
Publication #:
US20170133923
Pub Dt:
05/11/2017
Title:
REDUCING THERMAL RUNAWAY IN INVERTER DEVICES
17
Patent #:
9466505
Issue Dt:
10/11/2016
Application #:
14935767
Filing Dt:
11/09/2015
Publication #:
US20160064236
Pub Dt:
03/03/2016
Title:
METHODS OF PATTERNING FEATURES HAVING DIFFERING WIDTHS
18
Patent #:
9659862
Issue Dt:
05/23/2017
Application #:
14936582
Filing Dt:
11/09/2015
Publication #:
US20170133319
Pub Dt:
05/11/2017
Title:
METHOD, APPARATUS, AND SYSTEM FOR E-FUSE IN ADVANCED CMOS TECHNOLOGIES
19
Patent #:
9548318
Issue Dt:
01/17/2017
Application #:
14936848
Filing Dt:
11/10/2015
Title:
CONNECTING TO BACK-PLATE CONTACTS OR DIODE JUNCTIONS THROUGH A RMG ELECTRODE AND RESULTING DEVICES
20
Patent #:
9548312
Issue Dt:
01/17/2017
Application #:
14937041
Filing Dt:
11/10/2015
Title:
METHOD INCLUDING A FORMATION OF A CONTROL GATE OF A NONVOLATILE MEMORY CELL AND SEMICONDUCTOR STRUCTURE INCLUDING A NONVOLATILE MEMORY CELL
21
Patent #:
9704807
Issue Dt:
07/11/2017
Application #:
14939251
Filing Dt:
11/12/2015
Publication #:
US20170141035
Pub Dt:
05/18/2017
Title:
PATTERN PLACEMENT ERROR COMPENSATION LAYER
22
Patent #:
9748176
Issue Dt:
08/29/2017
Application #:
14939319
Filing Dt:
11/12/2015
Publication #:
US20170141036
Pub Dt:
05/18/2017
Title:
PATTERN PLACEMENT ERROR COMPENSATION LAYER IN VIA OPENING
23
Patent #:
9754829
Issue Dt:
09/05/2017
Application #:
14939464
Filing Dt:
11/12/2015
Publication #:
US20170140985
Pub Dt:
05/18/2017
Title:
SELF-ALIGNED CONDUCTIVE POLYMER PATTERN PLACEMENT ERROR COMPENSATION LAYER
24
Patent #:
9472558
Issue Dt:
10/18/2016
Application #:
14940499
Filing Dt:
11/13/2015
Title:
SEMICONDUCTOR STRUCTURES WITH STACKED NON-PLANAR FIELD EFFECT TRANSISTORS AND METHODS OF FORMING THE STRUCTURES
25
Patent #:
9799767
Issue Dt:
10/24/2017
Application #:
14940597
Filing Dt:
11/13/2015
Publication #:
US20170141226
Pub Dt:
05/18/2017
Title:
METHODS OF FORMING PMOS AND NMOS FINFET DEVICES ON CMOS BASED INTEGRATED CIRCUIT PRODUCTS
26
Patent #:
9748387
Issue Dt:
08/29/2017
Application #:
14940655
Filing Dt:
11/13/2015
Publication #:
US20170141227
Pub Dt:
05/18/2017
Title:
METHODS OF FORMING PMOS FINFET DEVICES AND MULTIPLE NMOS FINFET DEVICES WITH DIFFERENT PERFORMANCE CHARACTERISTICS
27
Patent #:
9740101
Issue Dt:
08/22/2017
Application #:
14940857
Filing Dt:
11/13/2015
Publication #:
US20170139324
Pub Dt:
05/18/2017
Title:
ADDITIONS OF ORGANIC SPECIES TO FACILITATE CROSSLINKER REMOVAL DURING PSPI CURE
28
Patent #:
9966182
Issue Dt:
05/08/2018
Application #:
14942311
Filing Dt:
11/16/2015
Publication #:
US20170140865
Pub Dt:
05/18/2017
Title:
MULTI-FREQUENCY INDUCTORS WITH LOW-K DIELECTRIC AREA
29
Patent #:
9412616
Issue Dt:
08/09/2016
Application #:
14942448
Filing Dt:
11/16/2015
Title:
METHODS OF FORMING SINGLE AND DOUBLE DIFFUSION BREAKS ON INTEGRATED CIRCUIT PRODUCTS COMPRISED OF FINFET DEVICES AND THE RESULTING PRODUCTS
30
Patent #:
9798244
Issue Dt:
10/24/2017
Application #:
14943086
Filing Dt:
11/17/2015
Publication #:
US20170139330
Pub Dt:
05/18/2017
Title:
METHODS, APPARATUS, AND SYSTEMS FOR MINIMIZING DEFECTIVITY IN TOP-COAT-FREE LITHOGRAPHY AND IMPROVING RETICLE CD UNIFORMITY
31
Patent #:
9484306
Issue Dt:
11/01/2016
Application #:
14943663
Filing Dt:
11/17/2015
Title:
MOSFET WITH ASYMMETRIC SELF-ALIGNED CONTACT
32
Patent #:
9502308
Issue Dt:
11/22/2016
Application #:
14944659
Filing Dt:
11/18/2015
Title:
METHODS FOR FORMING TRANSISTOR DEVICES WITH DIFFERENT SOURCE/DRAIN CONTACT LINERS AND THE RESULTING DEVICES
33
Patent #:
9484459
Issue Dt:
11/01/2016
Application #:
14944833
Filing Dt:
11/18/2015
Publication #:
US20160071978
Pub Dt:
03/10/2016
Title:
PERFORMANCE ENHANCEMENT IN TRANSISTORS BY PROVIDING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR MATERIAL ON THE BASIS OF A SEED LAYER
34
Patent #:
10191108
Issue Dt:
01/29/2019
Application #:
14945520
Filing Dt:
11/19/2015
Publication #:
US20170146592
Pub Dt:
05/25/2017
Title:
ON-CHIP SENSOR FOR MONITORING ACTIVE CIRCUITS ON INTEGRATED CIRCUIT (IC) CHIPS
35
Patent #:
9607973
Issue Dt:
03/28/2017
Application #:
14946162
Filing Dt:
11/19/2015
Title:
METHOD FOR ESTABLISHING INTERCONNECTS IN PACKAGES USING THIN INTERPOSERS
36
Patent #:
9590028
Issue Dt:
03/07/2017
Application #:
14948587
Filing Dt:
11/23/2015
Publication #:
US20160079342
Pub Dt:
03/17/2016
Title:
METHOD AND DEVICE FOR AN INTEGRATED TRENCH CAPACITOR
37
Patent #:
9535807
Issue Dt:
01/03/2017
Application #:
14951815
Filing Dt:
11/25/2015
Publication #:
US20160077939
Pub Dt:
03/17/2016
Title:
RECOVERING FROM UNCORRECTED MEMORY ERRORS
38
Patent #:
9767300
Issue Dt:
09/19/2017
Application #:
14953426
Filing Dt:
11/30/2015
Publication #:
US20160085983
Pub Dt:
03/24/2016
Title:
MANAGING RESTRICTED TAGGED CONTENT ELEMENTS WITHIN A PUBLISHED MESSAGE
39
Patent #:
9825094
Issue Dt:
11/21/2017
Application #:
14953702
Filing Dt:
11/30/2015
Publication #:
US20170054005
Pub Dt:
02/23/2017
Title:
FINFET PCM ACCESS TRANSISTOR HAVING GATE-WRAPPED SOURCE AND DRAIN REGIONS
40
Patent #:
9741847
Issue Dt:
08/22/2017
Application #:
14953874
Filing Dt:
11/30/2015
Publication #:
US20170154994
Pub Dt:
06/01/2017
Title:
METHODS OF FORMING A CONTACT STRUCTURE FOR A VERTICAL CHANNEL SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE
41
Patent #:
9520392
Issue Dt:
12/13/2016
Application #:
14954050
Filing Dt:
11/30/2015
Title:
SEMICONDUCTOR DEVICE INCLUDING FINFET AND FIN VARACTOR
42
Patent #:
9761720
Issue Dt:
09/12/2017
Application #:
14954166
Filing Dt:
11/30/2015
Publication #:
US20170154995
Pub Dt:
06/01/2017
Title:
REPLACEMENT BODY FINFET FOR IMPROVED JUNCTION PROFILE WITH GATE SELF-ALIGNED JUNCTIONS
43
Patent #:
9466567
Issue Dt:
10/11/2016
Application #:
14957842
Filing Dt:
12/03/2015
Publication #:
US20160086886
Pub Dt:
03/24/2016
Title:
NANOWIRE COMPATIBLE E-FUSE
44
Patent #:
9728506
Issue Dt:
08/08/2017
Application #:
14957860
Filing Dt:
12/03/2015
Publication #:
US20170162508
Pub Dt:
06/08/2017
Title:
STRAIN ENGINEERING DEVICES USING PARTIAL DEPTH FILMS IN THROUGH-SUBSTRATE VIAS
45
Patent #:
9653566
Issue Dt:
05/16/2017
Application #:
14958345
Filing Dt:
12/03/2015
Publication #:
US20160087073
Pub Dt:
03/24/2016
Title:
BIPOLAR JUNCTION TRANSISTORS WITH AN AIR GAP IN THE SHALLOW TRENCH ISOLATION
46
Patent #:
9859382
Issue Dt:
01/02/2018
Application #:
14959825
Filing Dt:
12/04/2015
Publication #:
US20170162656
Pub Dt:
06/08/2017
Title:
INTEGRATED CMOS WAFERS
47
Patent #:
9425108
Issue Dt:
08/23/2016
Application #:
14960378
Filing Dt:
12/05/2015
Title:
METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES
48
Patent #:
9773867
Issue Dt:
09/26/2017
Application #:
14962015
Filing Dt:
12/08/2015
Publication #:
US20160093692
Pub Dt:
03/31/2016
Title:
FINFET SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES
49
Patent #:
9704971
Issue Dt:
07/11/2017
Application #:
14963397
Filing Dt:
12/09/2015
Publication #:
US20170170291
Pub Dt:
06/15/2017
Title:
EPI FACET HEIGHT UNIFORMITY IMPROVEMENT FOR FDSOI TECHNOLOGIES
50
Patent #:
NONE
Issue Dt:
Application #:
14963683
Filing Dt:
12/09/2015
Publication #:
US20160093739
Pub Dt:
03/31/2016
Title:
FINFET SEMICONDUCTOR DEVICE WITH ISOLATED CHANNEL REGIONS
51
Patent #:
9461128
Issue Dt:
10/04/2016
Application #:
14963789
Filing Dt:
12/09/2015
Publication #:
US20160093704
Pub Dt:
03/31/2016
Title:
METHOD FOR CREATING SELF-ALIGNED TRANSISTOR CONTACTS
52
Patent #:
9589850
Issue Dt:
03/07/2017
Application #:
14964746
Filing Dt:
12/10/2015
Title:
METHOD FOR CONTROLLED RECESSING OF MATERIALS IN CAVITIES IN IC DEVICES
53
Patent #:
9520396
Issue Dt:
12/13/2016
Application #:
14965193
Filing Dt:
12/10/2015
Publication #:
US20160111422
Pub Dt:
04/21/2016
Title:
METHOD FOR MAKING HIGH VOLTAGE INTEGRATED CIRCUIT DEVICES IN A FIN-TYPE PROCESS AND RESULTING DEVICES
54
Patent #:
9590082
Issue Dt:
03/07/2017
Application #:
14965267
Filing Dt:
12/10/2015
Title:
INTEGRATION OF HETEROJUNCTION BIPOLAR TRANSISTORS WITH DIFFERENT BASE PROFILES
55
Patent #:
10078183
Issue Dt:
09/18/2018
Application #:
14966781
Filing Dt:
12/11/2015
Publication #:
US20170168242
Pub Dt:
06/15/2017
Title:
WAVEGUIDE STRUCTURES USED IN PHONOTICS CHIP PACKAGING
56
Patent #:
9503106
Issue Dt:
11/22/2016
Application #:
14966881
Filing Dt:
12/11/2015
Title:
FREQUENCY-LOCKED VOLTAGE REGULATED LOOP
57
Patent #:
9548381
Issue Dt:
01/17/2017
Application #:
14967946
Filing Dt:
12/14/2015
Title:
METHOD AND STRUCTURE FOR III-V NANOWIRE TUNNEL FETS
58
Patent #:
9590056
Issue Dt:
03/07/2017
Application #:
14967983
Filing Dt:
12/14/2015
Publication #:
US20160099321
Pub Dt:
04/07/2016
Title:
SEMICONDUCTOR DEVICE COMPRISING CONTACT STRUCTURES WITH PROTECTION LAYERS FORMED ON SIDEWALLS OF CONTACT ETCH STOP LAYERS
59
Patent #:
9704962
Issue Dt:
07/11/2017
Application #:
14970661
Filing Dt:
12/16/2015
Publication #:
US20170179248
Pub Dt:
06/22/2017
Title:
HORIZONTAL GATE ALL AROUND NANOWIRE TRANSISTOR BOTTOM ISOLATION
60
Patent #:
9941300
Issue Dt:
04/10/2018
Application #:
14970725
Filing Dt:
12/16/2015
Publication #:
US20170179156
Pub Dt:
06/22/2017
Title:
STRUCTURE AND METHOD FOR FULLY DEPLETED SILICON ON INSULATOR STRUCTURE FOR THRESHOLD VOLTAGE MODIFICATION
61
Patent #:
9640633
Issue Dt:
05/02/2017
Application #:
14974589
Filing Dt:
12/18/2015
Title:
SELF ALIGNED GATE SHAPE PREVENTING VOID FORMATION
62
Patent #:
10186482
Issue Dt:
01/22/2019
Application #:
14975726
Filing Dt:
12/19/2015
Publication #:
US20160104677
Pub Dt:
04/14/2016
Title:
SELF ALIGNED VIA FUSE
63
Patent #:
9712413
Issue Dt:
07/18/2017
Application #:
14976530
Filing Dt:
12/21/2015
Publication #:
US20160110244
Pub Dt:
04/21/2016
Title:
SYSTEMS AND METHODS FOR MANAGING COMPUTING SYSTEMS UTILIZING AUGMENTED REALITY
64
Patent #:
10020224
Issue Dt:
07/10/2018
Application #:
14980320
Filing Dt:
12/28/2015
Publication #:
US20170186682
Pub Dt:
06/29/2017
Title:
SELF-ALIGNED VIA FORMING TO CONDUCTIVE LINE AND RELATED WIRING STRUCTURE
65
Patent #:
9953978
Issue Dt:
04/24/2018
Application #:
14981574
Filing Dt:
12/28/2015
Publication #:
US20160118385
Pub Dt:
04/28/2016
Title:
REPLACEMENT GATE STRUCTURES FOR TRANSISTOR DEVICES
66
Patent #:
9583640
Issue Dt:
02/28/2017
Application #:
14982028
Filing Dt:
12/29/2015
Title:
METHOD INCLUDING A FORMATION OF A CONTROL GATE OF A NONVOLATILE MEMORY CELL AND SEMICONDUCTOR STRUCTURE
67
Patent #:
9806025
Issue Dt:
10/31/2017
Application #:
14982097
Filing Dt:
12/29/2015
Publication #:
US20170186693
Pub Dt:
06/29/2017
Title:
SOI WAFERS WITH BURIED DIELECTRIC LAYERS TO PREVENT CU DIFFUSION
68
Patent #:
9627409
Issue Dt:
04/18/2017
Application #:
14982112
Filing Dt:
12/29/2015
Publication #:
US20160300856
Pub Dt:
10/13/2016
Title:
Semiconductor device with thin-film resistor
69
Patent #:
9754951
Issue Dt:
09/05/2017
Application #:
14982228
Filing Dt:
12/29/2015
Publication #:
US20170125432
Pub Dt:
05/04/2017
Title:
SEMICONDUCTOR DEVICE WITH A MEMORY DEVICE AND A HIGH-K METAL GATE TRANSISTOR
70
Patent #:
9978849
Issue Dt:
05/22/2018
Application #:
14982459
Filing Dt:
12/29/2015
Publication #:
US20170186845
Pub Dt:
06/29/2017
Title:
SOI-MOSFET GATE INSULATION LAYER WITH DIFFERENT THICKNESS
71
Patent #:
9466664
Issue Dt:
10/11/2016
Application #:
14982474
Filing Dt:
12/29/2015
Publication #:
US20160133692
Pub Dt:
05/12/2016
Title:
UNIAXIALLY-STRAINED FD-SOI FINFET
72
Patent #:
9818637
Issue Dt:
11/14/2017
Application #:
14982576
Filing Dt:
12/29/2015
Publication #:
US20170186643
Pub Dt:
06/29/2017
Title:
DEVICE LAYER TRANSFER WITH A PRESERVED HANDLE WAFER SECTION
73
Patent #:
9589829
Issue Dt:
03/07/2017
Application #:
14982872
Filing Dt:
12/29/2015
Title:
FINFET DEVICE INCLUDING SILICON OXYCARBON ISOLATION STRUCTURE
74
Patent #:
9564484
Issue Dt:
02/07/2017
Application #:
14983157
Filing Dt:
12/29/2015
Publication #:
US20160118458
Pub Dt:
04/28/2016
Title:
METAL-INSULATOR-METAL BACK END OF LINE CAPACITOR STRUCTURES
75
Patent #:
9716177
Issue Dt:
07/25/2017
Application #:
14983217
Filing Dt:
12/29/2015
Publication #:
US20160133740
Pub Dt:
05/12/2016
Title:
SEMICONDUCTOR DEVICE COMPRISING A MULTI-LAYER CHANNEL REGION
76
Patent #:
9812404
Issue Dt:
11/07/2017
Application #:
14984547
Filing Dt:
12/30/2015
Publication #:
US20170194265
Pub Dt:
07/06/2017
Title:
ELECTRICAL CONNECTION AROUND A CRACKSTOP STRUCTURE
77
Patent #:
9904757
Issue Dt:
02/27/2018
Application #:
14985686
Filing Dt:
12/31/2015
Publication #:
US20170193150
Pub Dt:
07/06/2017
Title:
TEST PATTERNS FOR DETERMINING SIZING AND SPACING OF SUB-RESOLUTION ASSIST FEATURES (SRAFs)
78
Patent #:
9443931
Issue Dt:
09/13/2016
Application #:
14988050
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Assignor
1
GLOBALFOUNDRIES INC.
Exec Dt:
10/22/2020
Assignee
1
GLOBALFOUNDRIES U.S. INC.
2600 GREAT AMERICA WAY
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
60 WOODLANDS INDUSTRIAL PARK D STREET 2,
SINGAPORE, 738406 SINGAPORE

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