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Reel/Frame:036550/0001   Pages: 983
Recorded: 09/03/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 14793
Page 65 of 148
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148
1
Patent #:
7865855
Issue Dt:
01/04/2011
Application #:
11942744
Filing Dt:
11/20/2007
Publication #:
US20090064069
Pub Dt:
03/05/2009
Title:
METHOD AND SYSTEM FOR GENERATING A LAYOUT FOR AN INTEGRATED ELECTRONIC CIRCUIT
2
Patent #:
7862987
Issue Dt:
01/04/2011
Application #:
11942753
Filing Dt:
11/20/2007
Publication #:
US20090130599
Pub Dt:
05/21/2009
Title:
METHOD FOR FORMING AN ELECTRICAL STRUCTURE COMPRISING MULTIPLE PHOTOSENSITIVE MATERIALS
3
Patent #:
8017995
Issue Dt:
09/13/2011
Application #:
11942756
Filing Dt:
11/20/2007
Publication #:
US20090127619
Pub Dt:
05/21/2009
Title:
DEEP TRENCH SEMICONDUCTOR STRUCTURE AND METHOD
4
Patent #:
7923808
Issue Dt:
04/12/2011
Application #:
11942811
Filing Dt:
11/20/2007
Publication #:
US20090127652
Pub Dt:
05/21/2009
Title:
STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING
5
Patent #:
7895556
Issue Dt:
02/22/2011
Application #:
11942990
Filing Dt:
11/20/2007
Publication #:
US20090132982
Pub Dt:
05/21/2009
Title:
METHOD FOR OPTIMIZING AN UNROUTED DESIGN TO REDUCE THE PROBABILITY OF TIMING PROBLEMS DUE TO COUPLING AND LONG WIRE ROUTES
6
Patent #:
7882465
Issue Dt:
02/01/2011
Application #:
11944408
Filing Dt:
11/21/2007
Publication #:
US20080116919
Pub Dt:
05/22/2008
Title:
FPGA AND METHOD AND SYSTEM FOR CONFIGURING AND DEBUGGING A FPGA
7
Patent #:
7861209
Issue Dt:
12/28/2010
Application #:
11944769
Filing Dt:
11/26/2007
Publication #:
US20080086715
Pub Dt:
04/10/2008
Title:
METHOD FOR INTERLAYER AND YIELD BASED OPTICAL PROXIMITY CORRECTION
8
Patent #:
7752583
Issue Dt:
07/06/2010
Application #:
11944956
Filing Dt:
11/26/2007
Publication #:
US20080077381
Pub Dt:
03/27/2008
Title:
SYSTEM FOR VERIFICATION OF DIGITAL DESIGNS USING CASE-SPLITTING VIA CONSTRAINED INTERNAL SIGNALS
9
Patent #:
7458048
Issue Dt:
11/25/2008
Application #:
11945069
Filing Dt:
11/26/2007
Publication #:
US20080077379
Pub Dt:
03/27/2008
Title:
COMPUTER PROGRAM PRODUCT FOR VERIFICATION OF DIGITAL DESIGNS USING CASE-SPLITTING VIA CONSTRAINED INTERNAL SIGNALS
10
Patent #:
7913202
Issue Dt:
03/22/2011
Application #:
11945308
Filing Dt:
11/27/2007
Publication #:
US20080068039
Pub Dt:
03/20/2008
Title:
WAFER LEVEL I/O TEST, REPAIR AND/OR CUSTOMIZATION ENABLED BY I/O LAYER
11
Patent #:
7912568
Issue Dt:
03/22/2011
Application #:
11945700
Filing Dt:
11/27/2007
Publication #:
US20090138117
Pub Dt:
05/28/2009
Title:
TUNING ORDER CONFIGURATOR PERFORMANCE BY DYNAMIC INTEGRATION OF MANUFACTURING AND FIELD FEEDBACK
12
Patent #:
8037337
Issue Dt:
10/11/2011
Application #:
11946096
Filing Dt:
11/28/2007
Publication #:
US20090138676
Pub Dt:
05/28/2009
Title:
DESIGN STRUCTURES INCLUDING CIRCUITS FOR NOISE REDUCTION IN DIGITAL SYSTEMS
13
Patent #:
NONE
Issue Dt:
Application #:
11946231
Filing Dt:
11/28/2007
Publication #:
US20090134016
Pub Dt:
05/28/2009
Title:
UNDERBUMP METALLURGY EMPLOYING SPUTTER-DEPOSITED NICKEL TITANIUM COPPER ALLOY
14
Patent #:
NONE
Issue Dt:
Application #:
11946450
Filing Dt:
11/28/2007
Publication #:
US20090135640
Pub Dt:
05/28/2009
Title:
ELECTROMIGRATION-PROGRAMMABLE SEMICONDUCTOR DEVICE WITH BIDIRECTIONAL RESISTANCE CHANGE
15
Patent #:
8148953
Issue Dt:
04/03/2012
Application #:
11946550
Filing Dt:
11/28/2007
Publication #:
US20090134844
Pub Dt:
05/28/2009
Title:
APPARATUS AND METHOD FOR RECYCLING AND REUSING CHARGE IN AN ELECTRONIC CIRCUIT
16
Patent #:
7645700
Issue Dt:
01/12/2010
Application #:
11946922
Filing Dt:
11/29/2007
Publication #:
US20080088027
Pub Dt:
04/17/2008
Title:
DRY ETCHBACK OF INTERCONNECT CONTACTS
17
Patent #:
8004060
Issue Dt:
08/23/2011
Application #:
11946938
Filing Dt:
11/29/2007
Publication #:
US20090141533
Pub Dt:
06/04/2009
Title:
METAL GATE COMPATIBLE ELECTRICAL ANTIFUSE
18
Patent #:
7602635
Issue Dt:
10/13/2009
Application #:
11947092
Filing Dt:
11/29/2007
Publication #:
US20090141536
Pub Dt:
06/04/2009
Title:
STRUCTURE FOR A CONFIGURABLE SRAM SYSTEM AND METHOD
19
Patent #:
8412507
Issue Dt:
04/02/2013
Application #:
11947100
Filing Dt:
11/29/2007
Publication #:
US20080133205
Pub Dt:
06/05/2008
Title:
TESTING THE COMPLIANCE OF A DESIGN WITH THE SYNCHRONIZATION REQUIREMENTS OF A MEMORY MODEL
20
Patent #:
7883395
Issue Dt:
02/08/2011
Application #:
11947103
Filing Dt:
11/29/2007
Publication #:
US20090142994
Pub Dt:
06/04/2009
Title:
ELECTRICAL CONTACT STRUCTURES AND METHODS FOR USE
21
Patent #:
NONE
Issue Dt:
Application #:
11947156
Filing Dt:
11/29/2007
Publication #:
US20090144744
Pub Dt:
06/04/2009
Title:
PERFORMANCE EVALUATION OF ALGORITHMIC TASKS AND DYNAMIC PARAMETERIZATION ON MULTI-CORE PROCESSING SYSTEMS
22
Patent #:
NONE
Issue Dt:
Application #:
11947180
Filing Dt:
11/29/2007
Publication #:
US20090144677
Pub Dt:
06/04/2009
Title:
Design Structure for a Circuit and Method to Measure Threshold Voltage Distributions in SRAM Devices
23
Patent #:
NONE
Issue Dt:
Application #:
11947185
Filing Dt:
11/29/2007
Publication #:
US20090144745
Pub Dt:
06/04/2009
Title:
PERFORMANCE EVALUATION OF ALGORITHMIC TASKS AND DYNAMIC PARAMETERIZATION ON MULTI-CORE PROCESSING SYSTEMS
24
Patent #:
7676780
Issue Dt:
03/09/2010
Application #:
11947706
Filing Dt:
11/29/2007
Publication #:
US20080072202
Pub Dt:
03/20/2008
Title:
TECHNIQUES FOR SUPER FAST BUFFER INSERTION
25
Patent #:
8120175
Issue Dt:
02/21/2012
Application #:
11947832
Filing Dt:
11/30/2007
Publication #:
US20090140420
Pub Dt:
06/04/2009
Title:
SOFT ERROR RATE MITIGATION BY INTERCONNECT STRUCTURE
26
Patent #:
7909208
Issue Dt:
03/22/2011
Application #:
11947856
Filing Dt:
11/30/2007
Publication #:
US20090139451
Pub Dt:
06/04/2009
Title:
PROCESS OF MONITORING DISPENSING OF PROCESS FLUIDS IN PRECISION PROCESSING OPERATIONS
27
Patent #:
7863169
Issue Dt:
01/04/2011
Application #:
11947929
Filing Dt:
11/30/2007
Publication #:
US20090140350
Pub Dt:
06/04/2009
Title:
LITHOGRAPHY FOR PRINTING CONSTANT LINE WIDTH FEATURES
28
Patent #:
7873921
Issue Dt:
01/18/2011
Application #:
11948308
Filing Dt:
11/30/2007
Publication #:
US20090144689
Pub Dt:
06/04/2009
Title:
STRUCTURE FOR A VOLTAGE DETECTION CIRCUIT IN AN INTEGRATED CIRCUIT AND METHOD OF GENERATING A TRIGGER FLAG SIGNAL
29
Patent #:
NONE
Issue Dt:
Application #:
11948376
Filing Dt:
11/30/2007
Publication #:
US20090144678
Pub Dt:
06/04/2009
Title:
METHOD AND ON-CHIP CONTROL APPARATUS FOR ENHANCING PROCESS RELIABILITY AND PROCESS VARIABILITY THROUGH 3D INTEGRATION
30
Patent #:
7948535
Issue Dt:
05/24/2011
Application #:
11948463
Filing Dt:
11/30/2007
Publication #:
US20090141155
Pub Dt:
06/04/2009
Title:
HIGH DYNAMIC RANGE IMAGING CELL WITH ELECTRONIC SHUTTER EXTENSIONS
31
Patent #:
7434186
Issue Dt:
10/07/2008
Application #:
11948761
Filing Dt:
11/30/2007
Title:
METHOD AND SYSTEM FOR CALCULATING HIGH FREQUENCY LIMIT CAPACITANCE AND INDUCTANCE FOR COPLANAR ON-CHIP STRUCTURE
32
Patent #:
7848128
Issue Dt:
12/07/2010
Application #:
11949063
Filing Dt:
12/03/2007
Publication #:
US20090141527
Pub Dt:
06/04/2009
Title:
APPARATUS AND METHOD FOR IMPLEMENTING MATRIX-BASED SEARCH CAPABILITY IN CONTENT ADDRESSABLE MEMORY DEVICES
33
Patent #:
7924588
Issue Dt:
04/12/2011
Application #:
11949065
Filing Dt:
12/03/2007
Publication #:
US20090141528
Pub Dt:
06/04/2009
Title:
CONTENT ADDRESSABLE MEMORY WITH CONCURRENT TWO-DIMENSIONAL SEARCH CAPABILITY IN BOTH ROW AND COLUMN DIRECTIONS
34
Patent #:
8196088
Issue Dt:
06/05/2012
Application #:
11949066
Filing Dt:
12/03/2007
Publication #:
US20090144024
Pub Dt:
06/04/2009
Title:
METHOD AND STRUCTURE FOR SCREENING NFET-TO-PFET DEVICE PERFORMANCE OFFSETS WITHIN A CMOS PROCESS
35
Patent #:
7646648
Issue Dt:
01/12/2010
Application #:
11949068
Filing Dt:
12/03/2007
Publication #:
US20090141537
Pub Dt:
06/04/2009
Title:
APPARATUS AND METHOD FOR IMPLEMENTING MEMORY ARRAY DEVICE WITH BUILT IN COMPUTATIONAL CAPABILITY
36
Patent #:
7624289
Issue Dt:
11/24/2009
Application #:
11949129
Filing Dt:
12/03/2007
Publication #:
US20080091961
Pub Dt:
04/17/2008
Title:
POWER NETWORK RECONFIGURATION USING MEM SWITCHES
37
Patent #:
8268542
Issue Dt:
09/18/2012
Application #:
11949190
Filing Dt:
12/03/2007
Publication #:
US20090142704
Pub Dt:
06/04/2009
Title:
METHOD FOR REDUCING SIDE LOBE PRINTING USING A BARRIER LAYER
38
Patent #:
7432755
Issue Dt:
10/07/2008
Application #:
11949426
Filing Dt:
12/03/2007
Title:
PROGRAMMING CURRENT STABILIZED ELECTRICAL FUSE PROGRAMMING CIRCUIT AND METHOD
39
Patent #:
7880266
Issue Dt:
02/01/2011
Application #:
11949569
Filing Dt:
12/03/2007
Publication #:
US20080073749
Pub Dt:
03/27/2008
Title:
A FOUR-TERMINAL ANTIFUSE STRUCTURE HAVING INTEGRATED HEATING ELEMENTS FOR A PROGRAMMABLE CIRCUIT.
40
Patent #:
8024513
Issue Dt:
09/20/2011
Application #:
11949904
Filing Dt:
12/04/2007
Publication #:
US20090144506
Pub Dt:
06/04/2009
Title:
METHOD AND SYSTEM FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED CACHE
41
Patent #:
7767539
Issue Dt:
08/03/2010
Application #:
11949973
Filing Dt:
12/04/2007
Publication #:
US20090140338
Pub Dt:
06/04/2009
Title:
METHOD OF FABRICATING PATTERNED SOI DEVICES AND THE RESULTING DEVICE STRUCTURES
42
Patent #:
7956412
Issue Dt:
06/07/2011
Application #:
11950001
Filing Dt:
12/04/2007
Publication #:
US20090140343
Pub Dt:
06/04/2009
Title:
LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH A TRENCH FIELD PLATE
43
Patent #:
7479364
Issue Dt:
01/20/2009
Application #:
11950150
Filing Dt:
12/04/2007
Publication #:
US20080085473
Pub Dt:
04/10/2008
Title:
COPOLYMER FOR USE IN CHEMICAL AMPLIFICATION RESISTS
44
Patent #:
8784966
Issue Dt:
07/22/2014
Application #:
11950453
Filing Dt:
12/05/2007
Publication #:
US20080113169
Pub Dt:
05/15/2008
Title:
METHOD OF FORMING A MATERIAL HAVING A PREDEFINED MORPHOLOGY
45
Patent #:
NONE
Issue Dt:
Application #:
11950574
Filing Dt:
12/05/2007
Publication #:
US20090146223
Pub Dt:
06/11/2009
Title:
PROCESS AND METHOD TO LOWER CONTACT RESISTANCE
46
Patent #:
8457938
Issue Dt:
06/04/2013
Application #:
11950735
Filing Dt:
12/05/2007
Publication #:
US20090150133
Pub Dt:
06/11/2009
Title:
APPARATUS AND METHOD FOR SIMULATING ONE OR MORE OPERATIONAL CHARACTERISTICS OF AN ELECTRONICS RACK
47
Patent #:
7989357
Issue Dt:
08/02/2011
Application #:
11950741
Filing Dt:
12/05/2007
Publication #:
US20090146221
Pub Dt:
06/11/2009
Title:
METHOD OF PATTERNING SEMICONDUCTOR STRUCTURE AND STRUCTURE THEREOF
48
Patent #:
7979250
Issue Dt:
07/12/2011
Application #:
11950747
Filing Dt:
12/05/2007
Publication #:
US20090150123
Pub Dt:
06/11/2009
Title:
METHOD OF LAYING OUT A DATA CENTER USING A PLURALITY OF THERMAL SIMULATORS
49
Patent #:
7832925
Issue Dt:
11/16/2010
Application #:
11950758
Filing Dt:
12/05/2007
Publication #:
US20090150129
Pub Dt:
06/11/2009
Title:
APPARATUS AND METHOD FOR SIMULATING HEATED AIRFLOW EXHAUST OF AN ELECTRONICS SUBSYSTEM, ELECTRONICS RACK OR ROW OF ELECTRONICS RACKS
50
Patent #:
7912106
Issue Dt:
03/22/2011
Application #:
11950939
Filing Dt:
12/05/2007
Publication #:
US20090147818
Pub Dt:
06/11/2009
Title:
ENHANCED SURFACE-EMITTING PHOTONIC DEVICE
51
Patent #:
7473159
Issue Dt:
01/06/2009
Application #:
11951616
Filing Dt:
12/06/2007
Publication #:
US20080076331
Pub Dt:
03/27/2008
Title:
DETECTION OF DIAMOND CONTAMINATION IN POLISHING PAD AND RECONDITIONING SYSTEM THEREFOR
52
Patent #:
NONE
Issue Dt:
Application #:
11951646
Filing Dt:
12/06/2007
Publication #:
US20080087457
Pub Dt:
04/17/2008
Title:
Ceramic Package in Which Far End Noise is Reduced Using Capacitive Cancellation by Offset Wiring
53
Patent #:
7904849
Issue Dt:
03/08/2011
Application #:
11951705
Filing Dt:
12/06/2007
Publication #:
US20080092101
Pub Dt:
04/17/2008
Title:
CERAMIC PACKAGE IN WHICH FAR END NOISE IS REDUCED USING CAPACITIVE CANCELLATION BY OFFSET WIRING
54
Patent #:
8613973
Issue Dt:
12/24/2013
Application #:
11951858
Filing Dt:
12/06/2007
Publication #:
US20090145482
Pub Dt:
06/11/2009
Title:
PHOTOVOLTAIC DEVICE WITH SOLUTION-PROCESSED CHALCOGENIDE ABSORBER LAYER
55
Patent #:
7469395
Issue Dt:
12/23/2008
Application #:
11952544
Filing Dt:
12/07/2007
Publication #:
US20080074147
Pub Dt:
03/27/2008
Title:
WIRING OPTIMIZATIONS FOR POWER
56
Patent #:
NONE
Issue Dt:
Application #:
11952939
Filing Dt:
12/07/2007
Publication #:
US20090146181
Pub Dt:
06/11/2009
Title:
INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS
57
Patent #:
7727890
Issue Dt:
06/01/2010
Application #:
11953359
Filing Dt:
12/10/2007
Publication #:
US20090148677
Pub Dt:
06/11/2009
Title:
HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD
58
Patent #:
8062951
Issue Dt:
11/22/2011
Application #:
11953445
Filing Dt:
12/10/2007
Publication #:
US20090146263
Pub Dt:
06/11/2009
Title:
METHOD TO INCREASE EFFECTIVE MOSFET WIDTH
59
Patent #:
7671362
Issue Dt:
03/02/2010
Application #:
11953568
Filing Dt:
12/10/2007
Publication #:
US20090146143
Pub Dt:
06/11/2009
Title:
TEST STRUCTURE FOR DETERMINING OPTIMAL SEED AND LINER LAYER THICKNESSES FOR DUAL DAMASCENE PROCESSING
60
Patent #:
7494912
Issue Dt:
02/24/2009
Application #:
11953927
Filing Dt:
12/11/2007
Publication #:
US20080090407
Pub Dt:
04/17/2008
Title:
TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME
61
Patent #:
7596038
Issue Dt:
09/29/2009
Application #:
11954468
Filing Dt:
12/12/2007
Publication #:
US20090154258
Pub Dt:
06/18/2009
Title:
FLOATING BODY CONTROL IN SOI DRAM
62
Patent #:
8137791
Issue Dt:
03/20/2012
Application #:
11954557
Filing Dt:
12/12/2007
Publication #:
US20090155541
Pub Dt:
06/18/2009
Title:
FUSE AND PAD STRESS RELIEF
63
Patent #:
7560950
Issue Dt:
07/14/2009
Application #:
11954589
Filing Dt:
12/12/2007
Publication #:
US20080088335
Pub Dt:
04/17/2008
Title:
PACKAGING RELIABILITY SUPERCHIPS
64
Patent #:
NONE
Issue Dt:
Application #:
11954626
Filing Dt:
12/12/2007
Publication #:
US20080092096
Pub Dt:
04/17/2008
Title:
OPTIMIZED AUTOMATED CASE - SPLITTING VIA CONSTRAINTS IN A SYMBOLIC SIMULATION FRAMEWORK
65
Patent #:
7904839
Issue Dt:
03/08/2011
Application #:
11954646
Filing Dt:
12/12/2007
Publication #:
US20090158444
Pub Dt:
06/18/2009
Title:
SYSTEM AND METHOD FOR CONTROLLING ACCESS TO ADDRESSABLE INTEGRATED CIRCUITS
66
Patent #:
NONE
Issue Dt:
Application #:
11954749
Filing Dt:
12/12/2007
Publication #:
US20090152636
Pub Dt:
06/18/2009
Title:
HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS
67
Patent #:
7528048
Issue Dt:
05/05/2009
Application #:
11954782
Filing Dt:
12/12/2007
Publication #:
US20080132027
Pub Dt:
06/05/2008
Title:
PLANAR VERTICAL RESISTOR AND BOND PAD RESISTOR AND RELATED METHOD
68
Patent #:
7767579
Issue Dt:
08/03/2010
Application #:
11954802
Filing Dt:
12/12/2007
Publication #:
US20090155969
Pub Dt:
06/18/2009
Title:
PROTECTION OF SIGE DURING ETCH AND CLEAN OPERATIONS
69
Patent #:
8772933
Issue Dt:
07/08/2014
Application #:
11954812
Filing Dt:
12/12/2007
Publication #:
US20090152723
Pub Dt:
06/18/2009
Title:
INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME
70
Patent #:
8089160
Issue Dt:
01/03/2012
Application #:
11954866
Filing Dt:
12/12/2007
Publication #:
US20090152724
Pub Dt:
06/18/2009
Title:
IC INTERCONNECT FOR HIGH CURRENT
71
Patent #:
8030709
Issue Dt:
10/04/2011
Application #:
11954918
Filing Dt:
12/12/2007
Publication #:
US20090179283
Pub Dt:
07/16/2009
Title:
METAL GATE STACK AND SEMICONDUCTOR GATE STACK FOR CMOS DEVICES
72
Patent #:
7834442
Issue Dt:
11/16/2010
Application #:
11954943
Filing Dt:
12/12/2007
Publication #:
US20090179322
Pub Dt:
07/16/2009
Title:
ELECTRONIC PACKAGE METHOD AND STRUCTURE WITH CURE-MELT HIERARCHY
73
Patent #:
NONE
Issue Dt:
Application #:
11954966
Filing Dt:
12/12/2007
Publication #:
US20080079176
Pub Dt:
04/03/2008
Title:
STRUCTURE TO ENHANCE TEMPERATURE/HUMIDITY/BIAS PERFORMANCE OF SEMICONDUCTOR DEVICES BY SURFACE MODIFICATION
74
Patent #:
NONE
Issue Dt:
Application #:
11955430
Filing Dt:
12/13/2007
Publication #:
US20080098337
Pub Dt:
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Title:
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75
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7478280
Issue Dt:
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11955433
Filing Dt:
12/13/2007
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Pub Dt:
04/17/2008
Title:
TEST SYSTEM FOR INTEGRATED CIRCUITS
76
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11955451
Filing Dt:
12/13/2007
Publication #:
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Pub Dt:
06/18/2009
Title:
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77
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7566637
Issue Dt:
07/28/2009
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11955484
Filing Dt:
12/13/2007
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Pub Dt:
06/18/2009
Title:
METHOD OF INHIBITION OF METAL DIFFUSION ARISING FROM LASER DICING
78
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11/08/2011
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11955491
Filing Dt:
12/13/2007
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Pub Dt:
06/18/2009
Title:
PFET WITH TAILORED DIELECTRIC AND RELATED METHODS AND INTEGRATED CIRCUIT
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02/08/2011
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11955515
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12/13/2007
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Pub Dt:
06/18/2009
Title:
STRUCTURE AND METHOD FOR MANUFACTURING DEVICE WITH PLANAR HALO PROFILE
80
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8129773
Issue Dt:
03/06/2012
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11955579
Filing Dt:
12/13/2007
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Pub Dt:
04/17/2008
Title:
FIN-TYPE FIELD EFFECT TRANSISTOR
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Issue Dt:
07/19/2011
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11955580
Filing Dt:
12/13/2007
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Pub Dt:
08/19/2010
Title:
DESIGN STRUCTURE FOR A REDUNDANT MICRO-LOOP STRUCTURE FOR USE IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN PROCESS AND METHOD OF FORMING THE SAME
82
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12/28/2010
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Pub Dt:
04/24/2008
Title:
METAL OXIDE FIELD EFFECT TRANSISTOR WITH A SHARP HALO
83
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11955598
Filing Dt:
12/13/2007
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Title:
THERMAL PASTE CONTAINMENT FOR SEMICONDUCTOR MODULES
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Issue Dt:
05/04/2010
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11955653
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Publication #:
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Pub Dt:
06/18/2009
Title:
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85
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8001503
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11955689
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Pub Dt:
06/18/2009
Title:
METHOD AND SYSTEM FOR AUTOMATICALLY ACCESSING INTERNAL SIGNALS OR PORTS IN A DESIGN HIERARCHY
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7893485
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02/22/2011
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11955913
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12/13/2007
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Pub Dt:
06/18/2009
Title:
VERTICAL SOI TRENCH SONOS CELL
87
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8120095
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02/21/2012
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11955940
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12/13/2007
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Pub Dt:
06/18/2009
Title:
HIGH-DENSITY, TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS
88
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7863646
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01/04/2011
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11956043
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Pub Dt:
06/18/2009
Title:
DUAL OXIDE STRESS LINER
89
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Filing Dt:
12/14/2007
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Pub Dt:
06/18/2009
Title:
MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT
90
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9054074
Issue Dt:
06/09/2015
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11957576
Filing Dt:
12/17/2007
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Pub Dt:
06/18/2009
Title:
ONE-DIMENSIONAL HIERARCHICAL NESTED CHANNEL DESIGN FOR CONTINUOUS FEED MANUFACTURING PROCESSES
91
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7793237
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09/07/2010
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11957584
Filing Dt:
12/17/2007
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Pub Dt:
06/18/2009
Title:
SYSTEM, STRUCTURE AND METHOD OF PROVIDING DYNAMIC OPTIMIZATION OF INTEGRATED CIRCUITS USING A NON-CONTACT METHOD OF SELECTION, AND A DESIGN STRUCTURE
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12/17/2007
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12/18/2008
Title:
PRINTING A MASK WITH MAXIMUM POSSIBLE PROCESS WINDOW THROUGH ADJUSTMENT OF THE SOURCE DISTRIBUTION
93
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10/21/2008
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11957602
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Title:
PRINTING A MASK WITH MAXIMUM POSSIBLE PROCESS WINDOW THROUGH ADJUSTMENT OF THE SOURCE DISTRIBUTION
94
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NONE
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11957608
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12/17/2007
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04/24/2008
Title:
PRINTING A MASK WITH MAXIMUM POSSIBLE PROCESS WINDOW THROUGH ADJUSTMENT OF THE SOURCE DISTRIBUTION
95
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04/20/2010
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11957615
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06/05/2008
Title:
TRENCH WIDENING WITHOUT MERGING
96
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NONE
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11957775
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12/17/2007
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04/24/2008
Title:
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7872901
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01/18/2011
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11957797
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12/17/2007
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06/26/2008
Title:
PROGRAMMABLE-RESISTANCE MEMORY CELL
98
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11958558
Filing Dt:
12/18/2007
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Pub Dt:
06/18/2009
Title:
ELECTROSTATIC DISCHARGE PROTECTION FOR BIPOLAR SEMICONDUCTOR CIRCUITRY
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NONE
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11958595
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12/18/2007
Publication #:
US20090152651
Pub Dt:
06/18/2009
Title:
GATE STACK STRUCTURE WITH OXYGEN GETTERING LAYER
100
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NONE
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Application #:
11958598
Filing Dt:
12/18/2007
Publication #:
US20090153228
Pub Dt:
06/18/2009
Title:
STRUCTURE FOR IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS
Assignor
1
INTERNATIONAL BUSINESS MACHINES CORPORATION
Exec Dt:
06/29/2015
Assignee
1
GLOBALFOUNDRIES U.S. 2 LLC
2070 ROUTE 52
HOPEWELL JUNCTION, NEW YORK 12533
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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