|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12712371
|
Filing Dt:
|
02/25/2010
|
Publication #:
|
|
Pub Dt:
|
06/17/2010
| | | | |
Title:
|
CMOS TRANSISTORS WITH DIFFERENTIAL OXYGEN CONTENT HIGH-K DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
12712521
|
Filing Dt:
|
02/25/2010
|
Publication #:
|
|
Pub Dt:
|
08/25/2011
| | | | |
Title:
|
IMPLEMENTING EDRAM STACKED FET STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
12712836
|
Filing Dt:
|
02/25/2010
|
Publication #:
|
|
Pub Dt:
|
08/25/2011
| | | | |
Title:
|
METHOD FOR DESIGNING THE LAYOUT OF TURBINES IN A WINDFARM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12712880
|
Filing Dt:
|
02/25/2010
|
Publication #:
|
|
Pub Dt:
|
06/17/2010
| | | | |
Title:
|
METHODS TO OBTAIN A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAYOUT OPTIMIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
12713572
|
Filing Dt:
|
02/26/2010
|
Publication #:
|
|
Pub Dt:
|
12/09/2010
| | | | |
Title:
|
SINGLE-JUNCTION PHOTOVOLTAIC CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2014
|
Application #:
|
12713581
|
Filing Dt:
|
02/26/2010
|
Publication #:
|
|
Pub Dt:
|
03/03/2011
| | | | |
Title:
|
MULTIJUNCTION PHOTOVOLTAIC CELL FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
12714702
|
Filing Dt:
|
03/01/2010
|
Publication #:
|
|
Pub Dt:
|
09/01/2011
| | | | |
Title:
|
METHOD FOR SEMICONDUCTOR GATE HARDMASK REMOVAL AND DECOUPLING OF IMPLANTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12717398
|
Filing Dt:
|
03/04/2010
|
Publication #:
|
|
Pub Dt:
|
09/08/2011
| | | | |
Title:
|
STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2012
|
Application #:
|
12717439
|
Filing Dt:
|
03/04/2010
|
Publication #:
|
|
Pub Dt:
|
09/08/2011
| | | | |
Title:
|
PREVENTION OF OXYGEN ABSORPTION INTO HIGH-K GATE DIELECTRIC OF SILICON-ON-INSULATOR BASED FINFET DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2012
|
Application #:
|
12718567
|
Filing Dt:
|
03/05/2010
|
Publication #:
|
|
Pub Dt:
|
09/08/2011
| | | | |
Title:
|
SPATIAL CORRELATION-BASED ESTIMATION OF YIELD OF INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
12719058
|
Filing Dt:
|
03/08/2010
|
Publication #:
|
|
Pub Dt:
|
09/08/2011
| | | | |
Title:
|
GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
12719289
|
Filing Dt:
|
03/08/2010
|
Publication #:
|
|
Pub Dt:
|
09/08/2011
| | | | |
Title:
|
POLYSILICON RESISTOR AND E-FUSE FOR INTEGRATION WITH METAL GATE AND HIGH-K DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2011
|
Application #:
|
12719962
|
Filing Dt:
|
03/09/2010
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
FET RADIATION MONITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
12721032
|
Filing Dt:
|
03/10/2010
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
METHODS FOR FABRICATION OF AN AIR GAP-CONTAINING INTERCONNECT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
12721727
|
Filing Dt:
|
03/11/2010
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
DOPING OF SEMICONDUCTOR SUBSTRATE THROUGH CARBONLESS PHOSPHOROUS-CONTAINING LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
12721738
|
Filing Dt:
|
03/11/2010
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
METHOD OF ENHANCING PHOTORESIST ADHESION TO RARE EARTH OXIDES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
12723130
|
Filing Dt:
|
03/12/2010
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
INTEGRATED FRAMEWORK FOR FINITE-ELEMENT METHODS FOR PACKAGE, DEVICE AND CIRCUIT CO-DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12723189
|
Filing Dt:
|
03/12/2010
|
Title:
|
SOFT ERROR DETECTION FOR LATCHES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
12723743
|
Filing Dt:
|
03/15/2010
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
MANAGING MEMORY REFRESHES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
12723842
|
Filing Dt:
|
03/15/2010
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
NANOPORE BASED DEVICE FOR CUTTING LONG DNA MOLECULES INTO FRAGMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
12725287
|
Filing Dt:
|
03/16/2010
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
Title:
|
WAVEFRONT ENGINEERING OF MASK DATA FOR SEMICONDUCTOR DEVICE DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
12725688
|
Filing Dt:
|
03/17/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
METHOD AND SYSTEM FOR PARTICLES ANALYSIS IN MICROSTRUCTURE DEVICES BY ISOLATING PARTICLES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12725792
|
Filing Dt:
|
03/17/2010
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12725822
|
Filing Dt:
|
03/17/2010
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
Title:
|
VOLTAGE REGULATOR BYPASS IN MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
12726736
|
Filing Dt:
|
03/18/2010
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
Title:
|
METHOD FOR FORMING AN SOI SCHOTTKY SOURCE/DRAIN DEVICE TO CONTROL ENCROACHMENT AND DELAMINATION OF SILICIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
12726889
|
Filing Dt:
|
03/18/2010
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
Title:
|
ETSOI WITH REDUCED EXTENSION RESISTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
12726904
|
Filing Dt:
|
03/18/2010
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
Title:
|
STRAINED SILICON CARBIDE CHANNEL FOR ELECTRON MOBILITY OF NMOS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
12727024
|
Filing Dt:
|
03/18/2010
|
Title:
|
SMALL-AREA DIGITAL TO ANALOG CONVERTER BASED ON MASTER-SLAVE CONFIGURATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12727027
|
Filing Dt:
|
03/18/2010
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
SEMICONDUCTOR ON INSULATOR (SOI) DEVICE INCLUDING A DISCHARGE PATH FOR A DECOUPLING CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
12727312
|
Filing Dt:
|
03/19/2010
|
Publication #:
|
|
Pub Dt:
|
09/23/2010
| | | | |
Title:
|
High Threshold Voltage NMOS Transistors For Low Power IC Technology
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2014
|
Application #:
|
12727710
|
Filing Dt:
|
03/19/2010
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
Title:
|
GLASSY CARBON NANOSTRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2017
|
Application #:
|
12727746
|
Filing Dt:
|
03/19/2010
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
Title:
|
BACKEND OF LINE (BEOL) COMPATIBLE HIGH CURRENT DENSITY ACCESS DEVICE FOR HIGH DENSITY ARRAYS OF ELECTRONIC COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
12727753
|
Filing Dt:
|
03/19/2010
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
METHOD AND APPARATUS FOR FABRICATING A CARBON NANOTUBE TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
12729856
|
Filing Dt:
|
03/23/2010
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
HIGH DENSITY MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
12730403
|
Filing Dt:
|
03/24/2010
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
BACKSIDE DUMMY PLUGS FOR 3D INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2013
|
Application #:
|
12731241
|
Filing Dt:
|
03/25/2010
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
P-FET WITH A STRAINED NANOWIRE CHANNEL AND EMBEDDED SIGE SOURCE AND DRAIN STRESSORS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
12731369
|
Filing Dt:
|
03/25/2010
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
New Flux Composition and Process For Use Thereof
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2013
|
Application #:
|
12731469
|
Filing Dt:
|
03/25/2010
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
TEST PAD STRUCTURE FOR REUSE OF INTERCONNECT LEVEL MASKS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12731481
|
Filing Dt:
|
03/25/2010
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICES WITH VERTICAL EXTENSIONS FOR LATERAL SCALING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
12731487
|
Filing Dt:
|
03/25/2010
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
METHOD OF FORMING A MULTI-CHIP STACKED STRUCTURE INCLUDING A THIN INTERPOSER CHIP HAVING A FACE-TO-BACK BONDING WITH ANOTHER CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
12732751
|
Filing Dt:
|
03/26/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
METHOD AND SYSTEM FOR DETECTING PARTICLE CONTAMINATION IN AN IMMERSION LITHOGRAPHY TOOL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2012
|
Application #:
|
12748513
|
Filing Dt:
|
03/29/2010
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
EMF CORRECTION MODEL CALIBRATION USING ASYMMETRY FACTOR DATA OBTAINED FROM AERIAL IMAGES OR A PATTERNED LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
12749112
|
Filing Dt:
|
03/29/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
METHOD FOR FORMING CMOS TRANSISTORS HAVING METAL-CONTAINING GATE ELECTRODES FORMED ON A HIGH-K GATE DIELECTRIC MATERIAL.
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
12749220
|
Filing Dt:
|
03/29/2010
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
METHOD OF MANUFACTURING A FINNED SEMICONDUCTOR DEVICE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2012
|
Application #:
|
12749264
|
Filing Dt:
|
03/29/2010
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
METHODS AND SYSTEMS FOR TROUBLESHOOTING REMOTE SYSTEMS THROUGH RECREATION OF REMOTE SYSTEM SCENARIOS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12749303
|
Filing Dt:
|
03/29/2010
|
Publication #:
|
|
Pub Dt:
|
07/22/2010
| | | | |
Title:
|
METHOD AND APPROACH TO HOSTING VERSIONED WEB SERVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
|
Application #:
|
12749619
|
Filing Dt:
|
03/30/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
REDUCING SILICIDE RESISTANCE IN SILICON/GERMANIUM-CONTAINING DRAIN/SOURCE REGIONS OF TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
12749890
|
Filing Dt:
|
03/30/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
ENHANCING ADHESION OF INTERLAYER DIELECTRIC MATERIALS OF SEMICONDUCTOR DEVICES BY SUPPRESSING SILICIDE FORMATION AT THE SUBSTRATE EDGE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
12750342
|
Filing Dt:
|
03/30/2010
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
Title:
|
STRUCTURE FOR SELF-ALIGNED SILICIDE CONTACTS TO AN UPSIDE-DOWN FET BY EPITAXIAL SOURCE AND DRAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
12751302
|
Filing Dt:
|
03/31/2010
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH BUILT-IN SHALLOW TRENCH ISOLATION IN BACK GATE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2012
|
Application #:
|
12752369
|
Filing Dt:
|
04/01/2010
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
Title:
|
AIR GAPS IN A MULTILAYER INTEGRATED CIRCUIT AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
12752554
|
Filing Dt:
|
04/01/2010
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
Title:
|
COPLANAR WAVEGUIDE STRUCTURES WITH ALTERNATING WIDE AND NARROW PORTIONS, METHOD OF MANUFACTURE AND DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
12753270
|
Filing Dt:
|
04/02/2010
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
Title:
|
CONTROLLING FERROELECTRICITY IN DIELECTRIC FILMS BY PROCESS INDUCED UNIAXIAL STRAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2011
|
Application #:
|
12753373
|
Filing Dt:
|
04/02/2010
|
Publication #:
|
|
Pub Dt:
|
09/09/2010
| | | | |
Title:
|
MEMORY CONTROLLER INCLUDING A DUAL-MODE MEMORY INTERCONNECT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12754250
|
Filing Dt:
|
04/05/2010
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
HIGH PERFORMANCE MOSFET
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
12754359
|
Filing Dt:
|
04/05/2010
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
METHOD FOR ADJUSTING THE HEIGHT OF A GATE ELECTRODE IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
12754917
|
Filing Dt:
|
04/06/2010
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2012
|
Application #:
|
12756733
|
Filing Dt:
|
04/08/2010
|
Publication #:
|
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Pub Dt:
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10/14/2010
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Title:
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METHOD AND SYSTEM FOR REAL-TIME ESTIMATION AND PREDICTION OF THE THERMAL STATE OF A MICROPROCESSOR UNIT
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Patent #:
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Issue Dt:
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08/07/2012
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Application #:
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12756781
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Filing Dt:
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04/08/2010
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Publication #:
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Pub Dt:
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10/28/2010
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Title:
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METHOD AND SYSTEM FOR REAL-TIME ESTIMATION AND PREDICTION OF THE THERMAL STATE OF A MICROPROCESSOR UNIT
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Patent #:
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Issue Dt:
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01/08/2013
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Application #:
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12757323
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Filing Dt:
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04/09/2010
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Publication #:
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Pub Dt:
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10/13/2011
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Title:
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METHOD AND STRUCTURE FOR WORK FUNCTION ENGINEERING IN TRANSISTORS INCLUDING A HIGH DIELECTRIC CONSTANT GATE INSULATOR AND METAL GATE (HKMG)
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Patent #:
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Issue Dt:
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10/15/2013
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Application #:
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12757433
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Filing Dt:
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04/09/2010
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Publication #:
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Pub Dt:
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10/13/2011
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Title:
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NANOPORE CAPTURE SYSTEM
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Patent #:
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Issue Dt:
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08/09/2011
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Application #:
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12757567
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Filing Dt:
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04/09/2010
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Publication #:
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Pub Dt:
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08/05/2010
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Title:
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MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES
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Patent #:
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Issue Dt:
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08/02/2011
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Application #:
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12757648
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Filing Dt:
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04/09/2010
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Publication #:
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Pub Dt:
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08/05/2010
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Title:
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METHOD OF OPERATING A MEMORY CIRCUIT USING MEMORY CELLS WITH INDEPENDENT-GATE CONTROLLED ACCESS DEVICES
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Patent #:
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Issue Dt:
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12/04/2012
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Application #:
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12758939
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Filing Dt:
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04/13/2010
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Publication #:
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Pub Dt:
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10/13/2011
| | | | |
Title:
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NANOWIRE CIRCUITS IN MATCHED DEVICES
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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12759015
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Filing Dt:
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04/13/2010
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Publication #:
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Pub Dt:
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08/05/2010
| | | | |
Title:
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CIRCUIT AND DESIGN STRUCTURE FOR SYNCHRONIZING MULTIPLE DIGITAL SIGNALS
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Patent #:
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Issue Dt:
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07/12/2011
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Application #:
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12759479
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Filing Dt:
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04/13/2010
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Publication #:
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Pub Dt:
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08/05/2010
| | | | |
Title:
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PHASE CHANGE MEMORY WITH DUAL WORD LINES AND SOURCE LINES AND METHOD OF OPERATING SAME
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Patent #:
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Issue Dt:
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10/30/2012
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Application #:
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12759785
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Filing Dt:
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04/14/2010
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Publication #:
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Pub Dt:
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11/18/2010
| | | | |
Title:
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SEMICONDUCTOR DEVICE COMPRISING METAL GATES AND A SILICON CONTAINING RESISTOR FORMED ON AN ISOLATION STRUCTURE
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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12760047
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Filing Dt:
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04/14/2010
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Publication #:
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Pub Dt:
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08/05/2010
| | | | |
Title:
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OPERATING CHARACTERISTIC MEASUREMENT DEVICE AND METHODS THEREOF
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Patent #:
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Issue Dt:
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12/25/2012
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Application #:
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12760250
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Filing Dt:
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04/14/2010
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Publication #:
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Pub Dt:
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10/20/2011
| | | | |
Title:
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RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER
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Patent #:
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Issue Dt:
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08/21/2012
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Application #:
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12760368
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Filing Dt:
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04/14/2010
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Publication #:
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Pub Dt:
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12/16/2010
| | | | |
Title:
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OPTICAL WAVELENGTH SWITCH
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Patent #:
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Issue Dt:
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09/03/2013
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Application #:
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12761394
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Filing Dt:
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04/16/2010
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Publication #:
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Pub Dt:
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10/20/2011
| | | | |
Title:
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HEAD COMPRISING A CRYSTALLINE ALUMINA LAYER
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Patent #:
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Issue Dt:
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06/21/2011
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Application #:
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12762427
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Filing Dt:
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04/19/2010
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Publication #:
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Pub Dt:
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08/12/2010
| | | | |
Title:
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FINFET TRANSISTOR AND CIRCUIT
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Patent #:
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Issue Dt:
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08/14/2012
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Application #:
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12762832
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Filing Dt:
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04/19/2010
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Publication #:
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Pub Dt:
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10/20/2011
| | | | |
Title:
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SOURCE/DRAIN TECHNOLOGY FOR THE CARBON NANO-TUBE/GRAPHENE CMOS WITH A SINGLE SELF-ALIGNED METAL SILICIDE PROCESS
|
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Patent #:
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Issue Dt:
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01/31/2012
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Application #:
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12763550
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Filing Dt:
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04/20/2010
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Publication #:
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Pub Dt:
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10/20/2011
| | | | |
Title:
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CMP-FIRST DAMASCENE PROCESS SCHEME
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Patent #:
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Issue Dt:
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10/30/2012
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Application #:
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12764244
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Filing Dt:
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04/21/2010
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Publication #:
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Pub Dt:
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10/27/2011
| | | | |
Title:
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SHIELDING FOR HIGH-VOLTAGE SEMICONDUCTOR-ON-INSULATOR DEVICES
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Patent #:
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Issue Dt:
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08/07/2012
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Application #:
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12764329
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Filing Dt:
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04/21/2010
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Publication #:
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Pub Dt:
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10/27/2011
| | | | |
Title:
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MONOLAYER DOPANT EMBEDDED STRESSOR FOR ADVANCED CMOS
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
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12765275
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Filing Dt:
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04/22/2010
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Publication #:
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Pub Dt:
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11/11/2010
| | | | |
Title:
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ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS
|
|
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Patent #:
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Issue Dt:
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12/13/2011
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Application #:
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12765483
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Filing Dt:
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04/22/2010
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Publication #:
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Pub Dt:
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08/12/2010
| | | | |
Title:
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GRAPHENE-BASED TRANSISTOR
|
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Patent #:
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Issue Dt:
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05/15/2012
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Application #:
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12765950
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Filing Dt:
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04/23/2010
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Publication #:
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Pub Dt:
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08/12/2010
| | | | |
Title:
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SEMICONDUCTOR DIODE STRUCTURE OPERATION METHOD
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|
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Patent #:
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Issue Dt:
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05/10/2011
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Application #:
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12765979
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Filing Dt:
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04/23/2010
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Publication #:
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Pub Dt:
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08/12/2010
| | | | |
Title:
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GAP CAPACITORS FOR MONITORING STRESS IN SOLDER BALLS IN FLIP CHIP TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
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03/20/2012
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Application #:
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12766342
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Filing Dt:
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04/23/2010
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Publication #:
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Pub Dt:
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08/12/2010
| | | | |
Title:
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ON-CHIP HEATER AND METHODS FOR FABRICATION THEREOF AND USE THEREOF
|
|
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Patent #:
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Issue Dt:
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04/09/2013
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Application #:
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12766468
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Filing Dt:
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04/23/2010
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Publication #:
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Pub Dt:
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10/27/2011
| | | | |
Title:
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USE OF EPITAXIAL NI SILICIDE
|
|
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Patent #:
|
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Issue Dt:
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09/11/2012
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Application #:
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12766859
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Filing Dt:
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04/24/2010
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Publication #:
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Pub Dt:
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10/27/2011
| | | | |
Title:
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THIN BODY SEMICONDUCTOR DEVICES
|
|
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Patent #:
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Issue Dt:
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10/30/2012
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Application #:
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12767068
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Filing Dt:
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04/26/2010
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Publication #:
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Pub Dt:
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11/04/2010
| | | | |
Title:
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METHOD AND APPARATUS FOR DETECTING CONTRADICTORY TIMING CONSTRAINT CONFLICTS
|
|
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Patent #:
|
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Issue Dt:
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06/14/2011
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Application #:
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12767261
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Filing Dt:
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04/26/2010
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Publication #:
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Pub Dt:
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08/12/2010
| | | | |
Title:
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AMORPHIZATION/TEMPLATED RECRYSTALLIZATION METHOD FOR HYBRID ORIENTATION SUBSTRATES
|
|
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Patent #:
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|
Issue Dt:
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10/23/2012
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Application #:
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12767375
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Filing Dt:
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04/26/2010
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Publication #:
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Pub Dt:
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10/27/2011
| | | | |
Title:
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HANDLING TWO-DIMENSIONAL CONSTRAINTS IN INTEGRATED CIRCUIT LAYOUT
|
|
|
Patent #:
|
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Issue Dt:
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11/25/2014
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Application #:
|
12768267
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Filing Dt:
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04/27/2010
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Publication #:
|
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Pub Dt:
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10/27/2011
| | | | |
Title:
|
STRUCTURES AND METHODS FOR AIR GAP INTEGRATION
|
|
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Patent #:
|
|
Issue Dt:
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10/16/2012
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Application #:
|
12770254
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Filing Dt:
|
04/29/2010
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Publication #:
|
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Pub Dt:
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11/03/2011
| | | | |
Title:
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MICROELECTRONIC STRUCTURE INCLUDING AIR GAP
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2012
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Application #:
|
12770420
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Filing Dt:
|
04/29/2010
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Publication #:
|
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Pub Dt:
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11/03/2011
| | | | |
Title:
|
CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
12770791
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
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11/03/2011
| | | | |
Title:
|
DECOMPOSITION WITH MULTIPLE EXPOSURES IN A PROCESS WINDOW BASED OPC FLOW USING TOLERANCE BANDS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
12770792
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
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11/03/2011
| | | | |
Title:
|
METHOD TO OPTIMIZE WORK FUNCTION IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
12770948
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
THERMAL INTERFACE MATERIAL, TEST STRUCTURE AND METHOD OF USE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12770976
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
VDD PRE-SET OF DIRECT SENSE DRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2012
|
Application #:
|
12771293
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
NON-VOLATILE MEMORY BASED RELIABILITY AND AVAILABILITY MECHANISMS FOR A COMPUTING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
12771387
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
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11/03/2011
| | | | |
Title:
|
ON-CHIP NON-VOLATILE STORAGE OF A TEST-TIME PROFILE FOR EFFICIENCY AND PERFORMANCE CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
12771697
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
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11/03/2011
| | | | |
Title:
|
High Performance Compliant Wafer Test Probe
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2013
|
Application #:
|
12772436
|
Filing Dt:
|
05/03/2010
|
Publication #:
|
|
Pub Dt:
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12/02/2010
| | | | |
Title:
|
STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12772451
|
Filing Dt:
|
05/03/2010
|
Publication #:
|
|
Pub Dt:
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08/19/2010
| | | | |
Title:
|
SPIN-ON ANTIREFLECTIVE COATING FOR INTEGRATION OF PATTERNABLE DIELECTRIC MATERIALS AND INTERCONNECT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12773306
|
Filing Dt:
|
05/04/2010
|
Publication #:
|
|
Pub Dt:
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11/10/2011
| | | | |
Title:
|
STRUCTURE AND METHOD FOR MANUFACTURING INTERCONNECT STRUCTURES HAVING SELF-ALIGNED DIELECTRIC CAPS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
12774223
|
Filing Dt:
|
05/20/2010
|
Publication #:
|
|
Pub Dt:
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11/24/2011
| | | | |
Title:
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Enhanced Modularity in Heterogeneous 3D Stacks
|
|