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05/09/2017
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15224091
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07/29/2016
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06/26/2018
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08/01/2016
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02/01/2018
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05/16/2017
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15226165
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08/02/2016
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02/20/2018
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02/08/2018
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07/02/2019
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08/02/2016
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02/08/2018
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01/30/2018
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08/03/2016
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03/02/2017
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01/01/2019
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15227142
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08/03/2016
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02/16/2017
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05/08/2018
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15227330
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08/03/2016
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02/08/2018
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03/13/2018
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08/04/2016
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02/08/2018
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07/24/2018
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15228772
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08/04/2016
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02/09/2017
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11/21/2017
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15229292
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08/05/2016
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05/08/2018
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08/05/2016
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02/08/2018
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05/08/2018
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08/08/2016
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02/08/2018
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01/09/2018
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08/09/2016
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08/28/2018
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08/09/2016
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02/15/2018
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07/18/2017
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08/09/2016
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11/21/2017
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08/09/2016
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02/07/2017
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08/09/2016
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12/15/2016
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10/03/2017
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08/09/2016
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12/15/2016
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09/19/2017
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08/10/2016
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01/16/2018
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08/10/2016
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09/26/2017
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08/10/2016
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05/04/2017
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02/23/2021
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08/10/2016
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02/15/2018
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05/15/2018
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08/11/2016
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02/15/2018
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03/27/2018
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08/11/2016
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02/15/2018
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05/15/2018
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08/11/2016
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02/15/2018
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12/05/2017
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08/12/2016
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07/11/2017
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08/12/2016
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11/21/2017
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08/15/2016
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04/17/2018
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02/15/2018
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09/25/2018
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02/22/2018
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08/21/2018
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08/16/2016
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12/08/2016
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02/27/2018
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02/22/2018
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04/24/2018
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02/22/2018
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08/17/2016
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12/08/2016
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09/26/2017
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08/22/2016
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08/22/2017
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08/22/2016
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01/01/2019
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08/23/2016
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02/23/2017
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09/26/2017
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08/24/2016
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08/07/2018
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08/25/2016
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12/22/2016
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12/12/2017
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08/26/2016
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07/03/2018
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08/26/2016
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03/01/2018
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02/05/2019
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08/29/2016
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03/01/2018
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08/08/2017
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08/30/2016
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06/13/2017
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08/30/2016
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08/20/2019
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08/30/2016
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06/15/2017
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01/31/2017
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08/31/2016
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12/22/2016
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03/28/2017
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08/31/2016
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02/09/2017
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09/17/2019
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08/31/2016
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03/01/2018
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07/17/2018
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08/31/2016
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03/01/2018
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05/02/2017
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09/01/2016
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05/18/2017
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10/09/2018
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09/02/2016
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03/08/2018
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02/14/2017
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09/02/2016
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12/22/2016
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08/14/2018
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09/02/2016
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03/08/2018
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10/02/2018
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09/06/2016
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04/27/2017
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08/21/2018
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03/08/2018
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05/01/2018
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09/07/2016
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12/29/2016
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08/21/2018
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09/08/2016
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03/08/2018
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10/09/2018
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09/08/2016
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03/08/2018
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10/10/2017
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09/13/2016
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12/29/2016
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07/25/2017
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09/13/2016
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Title:
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MULTI-CHIP MODULES WITH VERTICALLY ALIGNED GRATING COUPLERS FOR TRANSMISSION OF LIGHT SIGNALS BETWEEN OPTICAL WAVEGUIDES
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Patent #:
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Issue Dt:
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01/29/2019
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Application #:
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15264885
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Filing Dt:
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09/14/2016
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Publication #:
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Pub Dt:
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01/05/2017
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Title:
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LATERAL BICMOS REPLACEMENT METAL GATE
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Patent #:
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Issue Dt:
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12/11/2018
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Application #:
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15264957
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Filing Dt:
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09/14/2016
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Publication #:
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Pub Dt:
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03/15/2018
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Title:
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BACKSIDE SPACER STRUCTURES FOR IMPROVED THERMAL PERFORMANCE
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Patent #:
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Issue Dt:
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11/07/2017
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Application #:
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15266092
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Filing Dt:
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09/15/2016
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Title:
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CONTACT FORMATION FOR STACKED FINFETs
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Patent #:
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Issue Dt:
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12/05/2017
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Application #:
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15266201
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Filing Dt:
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09/15/2016
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Title:
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WORD LINE VOLTAGE GENERATOR FOR PROGRAMMABLE MEMORY ARRAY
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Patent #:
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Issue Dt:
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06/20/2017
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Application #:
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15266439
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Filing Dt:
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09/15/2016
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Publication #:
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Pub Dt:
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01/05/2017
| | | | |
Title:
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EMBEDDED METAL-INSULATOR-METAL CAPACITOR
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Patent #:
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Issue Dt:
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05/15/2018
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Application #:
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15267887
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Filing Dt:
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09/16/2016
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Publication #:
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Pub Dt:
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01/05/2017
| | | | |
Title:
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METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE
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Patent #:
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Issue Dt:
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07/09/2019
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Application #:
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15268751
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Filing Dt:
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09/19/2016
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Publication #:
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Pub Dt:
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03/22/2018
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Title:
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METHODS OF FORMING BOTTOM AND TOP SOURCE/DRAIN REGIONS ON A VERTICAL TRANSISTOR DEVICE
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Patent #:
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Issue Dt:
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01/01/2019
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Application #:
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15268796
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Filing Dt:
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09/19/2016
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Publication #:
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Pub Dt:
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03/22/2018
| | | | |
Title:
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METHODS OF FORMING A VERTICAL TRANSISTOR DEVICE
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Patent #:
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Issue Dt:
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08/14/2018
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Application #:
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15269023
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Filing Dt:
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09/19/2016
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Publication #:
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Pub Dt:
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03/22/2018
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Title:
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FDSOI CHANNEL CONTROL BY IMPLANTED HIGH-K BURIED OXIDE
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Patent #:
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Issue Dt:
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07/03/2018
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Application #:
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15270598
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Filing Dt:
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09/20/2016
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Publication #:
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Pub Dt:
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03/22/2018
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Title:
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PERFORMANCE MATCHING IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) USING BACK-BIAS COMPENSATION
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Patent #:
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Issue Dt:
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11/14/2017
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Application #:
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15271475
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Filing Dt:
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09/21/2016
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Title:
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APPARATUS AND METHOD OF FORMING SELF-ALIGNED CUTS IN A NON-MANDREL LINE OF AN ARRAY OF METAL LINES
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Patent #:
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Issue Dt:
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11/14/2017
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Application #:
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15271497
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Filing Dt:
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09/21/2016
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Title:
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APPARATUS AND METHOD OF FORMING SELF-ALIGNED CUTS IN MANDREL AND A NON-MANDREL LINES OF AN ARRAY OF METAL LINES
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Patent #:
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Issue Dt:
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05/22/2018
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Application #:
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15271511
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Filing Dt:
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09/21/2016
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Publication #:
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Pub Dt:
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03/22/2018
| | | | |
Title:
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FIN PATTERNING FOR A FIN-TYPE FIELD-EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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10/10/2017
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Application #:
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15271519
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Filing Dt:
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09/21/2016
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Title:
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METHOD OF FORMING ANA REGIONS IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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03/20/2018
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Application #:
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15271730
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Filing Dt:
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09/21/2016
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Publication #:
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Pub Dt:
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03/22/2018
| | | | |
Title:
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SEMICONDUCTOR DEVICE RESISTOR STRUCTURE
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Patent #:
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Issue Dt:
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12/26/2017
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Application #:
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15272919
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Filing Dt:
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09/22/2016
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Publication #:
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Pub Dt:
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05/04/2017
| | | | |
Title:
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HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS
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Patent #:
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Issue Dt:
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08/29/2017
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Application #:
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15273777
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Filing Dt:
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09/23/2016
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Publication #:
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Pub Dt:
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01/12/2017
| | | | |
Title:
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PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A UNIFORM DEPTH TUNGSTEN RECESS TECHNIQUE
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Patent #:
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Issue Dt:
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08/18/2020
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Application #:
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15273778
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Filing Dt:
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09/23/2016
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Publication #:
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Pub Dt:
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01/12/2017
| | | | |
Title:
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LARGE AREA CONTACTS FOR SMALL TRANSISTORS
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Patent #:
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Issue Dt:
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05/01/2018
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Application #:
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15274974
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Filing Dt:
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09/23/2016
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Publication #:
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Pub Dt:
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03/29/2018
| | | | |
Title:
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METHODS, APPARATUS AND SYSTEM FOR SELF-ALIGNED RETROGRADE WELL DOPING FOR FINFET DEVICES
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Patent #:
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Issue Dt:
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09/04/2018
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Application #:
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15276372
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Filing Dt:
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09/26/2016
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Publication #:
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Pub Dt:
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03/29/2018
| | | | |
Title:
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Width Adjustment of Stacked Nanowires
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Patent #:
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Issue Dt:
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05/07/2019
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Application #:
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15277583
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Filing Dt:
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09/27/2016
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Publication #:
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Pub Dt:
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03/29/2018
| | | | |
Title:
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CAPACITIVE STRUCTURE IN A SEMICONDUCTOR DEVICE HAVING REDUCED CAPACITANCE VARIABILITY
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Patent #:
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Issue Dt:
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10/10/2017
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Application #:
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15277732
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Filing Dt:
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09/27/2016
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Publication #:
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Pub Dt:
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01/19/2017
| | | | |
Title:
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INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER
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Patent #:
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Issue Dt:
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08/21/2018
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Application #:
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15277796
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Filing Dt:
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09/27/2016
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Publication #:
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Pub Dt:
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03/29/2018
| | | | |
Title:
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METHOD, SYSTEM AND PROGRAM PRODUCT FOR IDENTIFYING ANOMALIES IN INTEGRATED CIRCUIT DESIGN LAYOUTS
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Patent #:
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Issue Dt:
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10/24/2017
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Application #:
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15278925
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Filing Dt:
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09/28/2016
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Publication #:
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Pub Dt:
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03/16/2017
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Title:
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PREVENTING LEAKAGE INSIDE AIR-GAP SPACER DURING CONTACT FORMATION
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Patent #:
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Issue Dt:
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11/27/2018
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Application #:
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15279559
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Filing Dt:
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09/29/2016
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Publication #:
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Pub Dt:
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03/29/2018
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Title:
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PROCESS FOR FORMING SEMICONDUCTOR LAYERS OF DIFFERENT THICKNESS IN FDSOI TECHNOLOGIES
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Patent #:
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Issue Dt:
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11/28/2017
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Application #:
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15279732
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Filing Dt:
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09/29/2016
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Title:
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METHOD FOR FORMING NANOWIRES INCLUDING MULTIPLE INTEGRATED DEVICES WITH ALTERNATE CHANNEL MATERIALS
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Patent #:
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Issue Dt:
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02/05/2019
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Application #:
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15280451
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Filing Dt:
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09/29/2016
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Publication #:
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Pub Dt:
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03/29/2018
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Title:
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CONTROLLING SELF-ALIGNED GATE LENGTH IN VERTICAL TRANSISTOR REPLACEMENT GATE FLOW
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Patent #:
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Issue Dt:
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08/07/2018
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Application #:
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15281183
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Filing Dt:
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09/30/2016
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Publication #:
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Pub Dt:
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04/05/2018
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Title:
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EXPANSION OF ALLOWED DESIGN RULE SPACE BY WAIVING BENIGN GEOMETRIES
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Patent #:
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Issue Dt:
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01/30/2018
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Application #:
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15281227
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Filing Dt:
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09/30/2016
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Title:
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METHODS OF SIMULTANEOUSLY FORMING BOTTOM AND TOP SPACERS ON A VERTICAL TRANSISTOR DEVICE
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Patent #:
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Issue Dt:
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06/05/2018
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Application #:
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15281418
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Filing Dt:
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09/30/2016
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Publication #:
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Pub Dt:
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04/05/2018
| | | | |
Title:
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LOCAL TRAP-RICH ISOLATION
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Patent #:
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Issue Dt:
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04/24/2018
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Application #:
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15282211
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Filing Dt:
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09/30/2016
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Publication #:
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Pub Dt:
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04/05/2018
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Title:
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METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE
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Patent #:
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Issue Dt:
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01/09/2018
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Application #:
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15282320
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Filing Dt:
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09/30/2016
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Title:
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SILICON WAVEGUIDE DEVICES IN INTEGRATED PHOTONICS
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Patent #:
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Issue Dt:
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12/05/2017
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Application #:
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15282415
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Filing Dt:
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09/30/2016
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Title:
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VERTICAL FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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03/21/2017
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Application #:
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15282836
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Filing Dt:
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09/30/2016
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Publication #:
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Pub Dt:
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02/02/2017
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Title:
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TRENCH FORMATION FOR DIELECTRIC FILLED CUT REGION
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Patent #:
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Issue Dt:
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07/04/2017
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Application #:
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15283951
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Filing Dt:
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10/03/2016
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Pub Dt:
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05/18/2017
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Title:
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MOSFET WITH ASYMMETRIC SELF-ALIGNED CONTACT
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Issue Dt:
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04/24/2018
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15284110
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Filing Dt:
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10/03/2016
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Pub Dt:
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04/05/2018
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Title:
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PREVENTING OXIDATION DEFECTS IN STRAIN-RELAXED FINS BY REDUCING LOCAL GAP FILL VOIDS
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Patent #:
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Issue Dt:
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12/11/2018
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15284773
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10/04/2016
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Publication #:
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Pub Dt:
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04/05/2018
| | | | |
Title:
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SHRINK PROCESS AWARE ASSIST FEATURES
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Patent #:
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Issue Dt:
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09/18/2018
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Application #:
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15285092
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Filing Dt:
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10/04/2016
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Publication #:
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Pub Dt:
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04/05/2018
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Title:
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METHODS OF FORMING METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS AND THE RESULTING PRODUCTS
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Patent #:
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Issue Dt:
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08/14/2018
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Application #:
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15285978
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Filing Dt:
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10/05/2016
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Publication #:
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Pub Dt:
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04/05/2018
| | | | |
Title:
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METHOD OF MANUFACTURING SELECTIVE NANOSTRUCTURES INTO FINFET PROCESS FLOW
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