USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Assignments on the Web > Patent Query

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	054633/0001			Pages:	1245
		Recorded:	11/02/2020
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 8468
Page 70 of 85
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

Patent #:	10002786	Issue Dt:	06/19/2018	Application #:	15379707	Filing Dt:	12/15/2016
Publication #:	US20180174895	Pub Dt:	06/21/2018
Title:	INTERCONNECTION CELLS HAVING VARIABLE WIDTH METAL LINES AND FULLY-SELF ALIGNED VARIABLE LENGTH CONTINUITY CUTS

Patent #:	9887127	Issue Dt:	02/06/2018	Application #:	15379740	Filing Dt:	12/15/2016
Title:	INTERCONNECTION LINES HAVING VARIABLE WIDTHS AND PARTIALLY SELF-ALIGNED CONTINUITY CUTS

Patent #:	10128151	Issue Dt:	11/13/2018	Application #:	15381826	Filing Dt:	12/16/2016
Publication #:	US20180174965	Pub Dt:	06/21/2018
Title:	DEVICES AND METHODS OF COBALT FILL METALLIZATION

Patent #:	10014397	Issue Dt:	07/03/2018	Application #:	15383171	Filing Dt:	12/19/2016
Publication #:	US20180175180	Pub Dt:	06/21/2018
Title:	BIPOLAR JUNCTION TRANSISTORS WITH A COMBINED VERTICAL-LATERAL ARCHITECTURE

Patent #:	9916982	Issue Dt:	03/13/2018	Application #:	15383461	Filing Dt:	12/19/2016
Title:	DIELECTRIC PRESERVATION IN A REPLACEMENT GATE PROCESS

Patent #:	10026883	Issue Dt:	07/17/2018	Application #:	15385068	Filing Dt:	12/20/2016
Publication #:	US20180175266	Pub Dt:	06/21/2018
Title:	WAFER BOND INTERCONNECT STRUCTURES

Patent #:	9953831	Issue Dt:	04/24/2018	Application #:	15385949	Filing Dt:	12/21/2016
Title:	DEVICE STRUCTURES WITH MULTIPLE NITRIDED LAYERS

Patent #:	10446442	Issue Dt:	10/15/2019	Application #:	15386097	Filing Dt:	12/21/2016
Publication #:	US20180174948	Pub Dt:	06/21/2018
Title:	INTEGRATED CIRCUIT CHIP WITH MOLDING COMPOUND HANDLER SUBSTRATE AND METHOD

Patent #:	10062711	Issue Dt:	08/28/2018	Application #:	15386507	Filing Dt:	12/21/2016
Publication #:	US20180175064	Pub Dt:	06/21/2018
Title:	WAFERS AND DEVICE STRUCTURES WITH BODY CONTACTS

Patent #:	10109599	Issue Dt:	10/23/2018	Application #:	15387120	Filing Dt:	12/21/2016
Publication #:	US20180174982	Pub Dt:	06/21/2018
Title:	INTEGRATED CIRCUIT STRUCTURE WITH CONTINUOUS METAL CRACK STOP

Patent #:	9929157	Issue Dt:	03/27/2018	Application #:	15387933	Filing Dt:	12/22/2016
Title:	TALL SINGLE-FIN FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURES AND METHODS

Patent #:	9972495	Issue Dt:	05/15/2018	Application #:	15387984	Filing Dt:	12/22/2016
Title:	LOW-K DIELECTRIC SPACER FOR A GATE CUT

Patent #:	10068815	Issue Dt:	09/04/2018	Application #:	15388136	Filing Dt:	12/22/2016
Publication #:	US20180182677	Pub Dt:	06/28/2018
Title:	TEST STRUCTURE FOR TESTING VIA RESISTANCE AND METHOD

Patent #:	9929048	Issue Dt:	03/27/2018	Application #:	15388400	Filing Dt:	12/22/2016
Title:	MIDDLE OF THE LINE (MOL) CONTACTS WITH TWO-DIMENSIONAL SELF-ALIGNMENT

Patent #:	10020260	Issue Dt:	07/10/2018	Application #:	15388530	Filing Dt:	12/22/2016
Publication #:	US20180182708	Pub Dt:	06/28/2018
Title:	CORROSION AND/OR ETCH PROTECTION LAYER FOR CONTACTS AND INTERCONNECT METALLIZATION INTEGRATION

Patent #:	9941301	Issue Dt:	04/10/2018	Application #:	15388772	Filing Dt:	12/22/2016
Title:	FULLY DEPLETED SILICON-ON-INSULATOR (FDSOI) TRANSISTOR DEVICE AND SELF-ALIGNED ACTIVE AREA IN FDSOI BULK EXPOSED REGIONS

Patent #:	10347546	Issue Dt:	07/09/2019	Application #:	15389632	Filing Dt:	12/23/2016
Publication #:	US20180182675	Pub Dt:	06/28/2018
Title:	INTEGRATED CIRCUIT STRUCTURE INCLUDING POWER RAIL AND TAPPING WIRE WITH METHOD OF FORMING SAME

Patent #:	10014409	Issue Dt:	07/03/2018	Application #:	15393400	Filing Dt:	12/29/2016
Publication #:	US20180190817	Pub Dt:	07/05/2018
Title:	METHOD AND STRUCTURE TO PROVIDE INTEGRATED LONG CHANNEL VERTICAL FINFET DEVICE

Patent #:	9824748	Issue Dt:	11/21/2017	Application #:	15395036	Filing Dt:	12/30/2016
Title:	SRAM BITCELL STRUCTURES FACILITATING BIASING OF PULL-UP TRANSISTORS

Patent #:	9935201	Issue Dt:	04/03/2018	Application #:	15396743	Filing Dt:	01/02/2017
Publication #:	US20170110583	Pub Dt:	04/20/2017
Title:	HIGH DOPED III-V SOURCE/DRAIN JUNCTIONS FOR FIELD EFFECT TRANSISTORS

Patent #:	9799661	Issue Dt:	10/24/2017	Application #:	15397004	Filing Dt:	01/03/2017
Title:	SRAM BITCELL STRUCTURES FACILITATING BIASING OF PULL-DOWN TRANSISTORS

Patent #:	9734897	Issue Dt:	08/15/2017	Application #:	15397021	Filing Dt:	01/03/2017
Title:	SRAM BITCELL STRUCTURES FACILITATING BIASING OF PASS GATE TRANSISTORS

Patent #:	9917103	Issue Dt:	03/13/2018	Application #:	15397978	Filing Dt:	01/04/2017
Title:	DIFFUSION BREAK FORMING AFTER SOURCE/DRAIN FORMING AND RELATED IC STRUCTURE

Patent #:	9799748	Issue Dt:	10/24/2017	Application #:	15398335	Filing Dt:	01/04/2017
Title:	METHOD OF FORMING INNER SPACERS ON A NANO-SHEET/WIRE DEVICE

Patent #:	10347622	Issue Dt:	07/09/2019	Application #:	15398946	Filing Dt:	01/05/2017
Publication #:	US20180190644	Pub Dt:	07/05/2018
Title:	SILICON-CONTROLLED RECTIFIERS HAVING A CATHODE COUPLED BY A CONTACT WITH A DIODE TRIGGER

Patent #:	10204861	Issue Dt:	02/12/2019	Application #:	15399200	Filing Dt:	01/05/2017
Publication #:	US20180190588	Pub Dt:	07/05/2018
Title:	Structure with Local Contact for Shorting a Gate Electrode to a Source/Drain Region

Patent #:	9893157	Issue Dt:	02/13/2018	Application #:	15401281	Filing Dt:	01/09/2017
Title:	STRUCTURES WITH CONTACT TRENCHES AND ISOLATION TRENCHES

Patent #:	10157927	Issue Dt:	12/18/2018	Application #:	15404754	Filing Dt:	01/12/2017
Publication #:	US20180197867	Pub Dt:	07/12/2018
Title:	SEMICONDUCTOR MEMORY DEVICES HAVING AN UNDERCUT SOURCE/DRAIN REGION

Patent #:	10146132	Issue Dt:	12/04/2018	Application #:	15405448	Filing Dt:	01/13/2017
Publication #:	US20180203359	Pub Dt:	07/19/2018
Title:	MOBILE DISPENSE DEVICE FOR CHEMICALS USED IN MICRO-PROCESSING

Patent #:	10056481	Issue Dt:	08/21/2018	Application #:	15405495	Filing Dt:	01/13/2017
Publication #:	US20180204944	Pub Dt:	07/19/2018
Title:	SEMICONDUCTOR DEVICE STRUCTURE

Patent #:	9812324	Issue Dt:	11/07/2017	Application #:	15405789	Filing Dt:	01/13/2017
Title:	METHODS TO CONTROL FIN TIP PLACEMENT

Patent #:	10224330	Issue Dt:	03/05/2019	Application #:	15407960	Filing Dt:	01/17/2017
Publication #:	US20180204840	Pub Dt:	07/19/2018
Title:	SELF-ALIGNED JUNCTION STRUCTURES

Patent #:	10026824	Issue Dt:	07/17/2018	Application #:	15408540	Filing Dt:	01/18/2017
Publication #:	US20180204927	Pub Dt:	07/19/2018
Title:	AIR-GAP GATE SIDEWALL SPACER AND METHOD

Patent #:	10290574	Issue Dt:	05/14/2019	Application #:	15408883	Filing Dt:	01/18/2017
Publication #:	US20180204796	Pub Dt:	07/19/2018
Title:	EMBEDDED METAL-INSULATOR-METAL (MIM) DECOUPLING CAPACITOR IN MONOLITIC THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) STRUCTURE

Patent #:	9870942	Issue Dt:	01/16/2018	Application #:	15410032	Filing Dt:	01/19/2017
Title:	METHOD OF FORMING MANDREL AND NON-MANDREL METAL LINES HAVING VARIABLE WIDTHS

Patent #:	10026818	Issue Dt:	07/17/2018	Application #:	15410159	Filing Dt:	01/19/2017
Publication #:	US20180204920	Pub Dt:	07/19/2018
Title:	FIELD EFFECT TRANSISTOR STRUCTURE WITH RECESSED INTERLAYER DIELECTRIC AND METHOD

Patent #:	9905476	Issue Dt:	02/27/2018	Application #:	15412598	Filing Dt:	01/23/2017
Publication #:	US20170133278	Pub Dt:	05/11/2017
Title:	ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs

Patent #:	10032668	Issue Dt:	07/24/2018	Application #:	15412784	Filing Dt:	01/23/2017
Publication #:	US20170133268	Pub Dt:	05/11/2017
Title:	CHAMFERLESS VIA STRUCTURES

Patent #:	10109524	Issue Dt:	10/23/2018	Application #:	15413710	Filing Dt:	01/24/2017
Publication #:	US20180211873	Pub Dt:	07/26/2018
Title:	RECESSING OF LINER AND CONDUCTOR FOR VIA FORMATION

Patent #:	9911604	Issue Dt:	03/06/2018	Application #:	15413823	Filing Dt:	01/24/2017
Title:	SIDEWALL SPACER PATTERN FORMATION METHOD

Patent #:	9865543	Issue Dt:	01/09/2018	Application #:	15416152	Filing Dt:	01/26/2017
Title:	STRUCTURE AND METHOD FOR INHIBITING COBALT DIFFUSION

Patent #:	10153201	Issue Dt:	12/11/2018	Application #:	15417848	Filing Dt:	01/27/2017
Publication #:	US20170133265	Pub Dt:	05/11/2017
Title:	ADVANCED MOSFET CONTACT STRUCTURE TO REDUCE METAL-SEMICONDUCTOR INTERFACE RESISTANCE

Patent #:	10242946	Issue Dt:	03/26/2019	Application #:	15418001	Filing Dt:	01/27/2017
Publication #:	US20180218981	Pub Dt:	08/02/2018
Title:	CIRCUIT DESIGN HAVING ALIGNED POWER STAPLES

Patent #:	9971859	Issue Dt:	05/15/2018	Application #:	15418015	Filing Dt:	01/27/2017
Publication #:	US20170147726	Pub Dt:	05/25/2017
Title:	MODELING LOCALIZED TEMPERATURE CHANGES ON AN INTEGRATED CIRCUIT CHIP USING THERMAL POTENTIAL THEORY

Patent #:	10283505	Issue Dt:	05/07/2019	Application #:	15418996	Filing Dt:	01/30/2017
Publication #:	US20170141110	Pub Dt:	05/18/2017
Title:	DUMMY GATE USED AS INTERCONNECTION AND METHOD OF MAKING THE SAME

Patent #:	10008415	Issue Dt:	06/26/2018	Application #:	15419346	Filing Dt:	01/30/2017
Publication #:	US20170140994	Pub Dt:	05/18/2017
Title:	GATE STRUCTURE CUT AFTER FORMATION OF EPITAXIAL ACTIVE REGIONS

Patent #:	10103119	Issue Dt:	10/16/2018	Application #:	15420362	Filing Dt:	01/31/2017
Publication #:	US20180218991	Pub Dt:	08/02/2018
Title:	METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE FOR JOINING WAFERS AND RESULTING STRUCTURE

Patent #:	9728456	Issue Dt:	08/08/2017	Application #:	15420467	Filing Dt:	01/31/2017
Publication #:	US20170140984	Pub Dt:	05/18/2017
Title:	INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER

Patent #:	10185312	Issue Dt:	01/22/2019	Application #:	15420749	Filing Dt:	01/31/2017
Publication #:	US20180217584	Pub Dt:	08/02/2018
Title:	INSITU TOOL HEALTH AND RECIPE QUALITY MONITORING ON A CDSEM

Patent #:	10002797	Issue Dt:	06/19/2018	Application #:	15420794	Filing Dt:	01/31/2017
Title:	CHIP INTEGRATION INCLUDING VERTICAL FIELD-EFFECT TRANSISTORS AND BIPOLAR JUNCTION TRANSISTORS

Patent #:	9893063	Issue Dt:	02/13/2018	Application #:	15420967	Filing Dt:	01/31/2017
Publication #:	US20170141109	Pub Dt:	05/18/2017
Title:	SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET STANDARD CELLS

Patent #:	10332834	Issue Dt:	06/25/2019	Application #:	15421698	Filing Dt:	02/01/2017
Publication #:	US20170141031	Pub Dt:	05/18/2017
Title:	SEMICONDUCTOR FUSES WITH NANOWIRE FUSE LINKS AND FABRICATION METHODS THEREOF

Patent #:	10170309	Issue Dt:	01/01/2019	Application #:	15422689	Filing Dt:	02/15/2017
Publication #:	US20180233361	Pub Dt:	08/16/2018
Title:	DUMMY PATTERN ADDITION TO IMPROVE CD UNIFORMITY

Patent #:	9997403	Issue Dt:	06/12/2018	Application #:	15422923	Filing Dt:	02/02/2017
Publication #:	US20170243784	Pub Dt:	08/24/2017
Title:	METAL LAYER TIP TO TIP SHORT

Patent #:	10083952	Issue Dt:	09/25/2018	Application #:	15423006	Filing Dt:	02/02/2017
Publication #:	US20180219006	Pub Dt:	08/02/2018
Title:	DIODE-TRIGGERED SCHOTTKY SILICON-CONTROLLED RECTIFIER FOR FIN-FET ELECTROSTATIC DISCHARGE CONTROL

Patent #:	10068804	Issue Dt:	09/04/2018	Application #:	15423326	Filing Dt:	02/02/2017
Publication #:	US20180218947	Pub Dt:	08/02/2018
Title:	METHODS, APPARATUS AND SYSTEM FOR PROVIDING ADJUSTABLE FIN HEIGHT FOR A FINFET DEVICE

Patent #:	9761662	Issue Dt:	09/12/2017	Application #:	15423647	Filing Dt:	02/03/2017
Title:	ACTIVE AREA SHAPES REDUCING DEVICE SIZE

Patent #:	9911823	Issue Dt:	03/06/2018	Application #:	15423945	Filing Dt:	02/03/2017
Publication #:	US20170148895	Pub Dt:	05/25/2017
Title:	POC PROCESS FLOW FOR CONFORMAL RECESS FILL

Patent #:	10468149	Issue Dt:	11/05/2019	Application #:	15424200	Filing Dt:	02/03/2017
Publication #:	US20180226166	Pub Dt:	08/09/2018
Title:	EXTREME ULTRAVIOLET MIRRORS AND MASKS WITH IMPROVED REFLECTIVITY

Patent #:	10170617	Issue Dt:	01/01/2019	Application #:	15424379	Filing Dt:	02/03/2017
Publication #:	US20180226505	Pub Dt:	08/09/2018
Title:	VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS

Patent #:	9831248	Issue Dt:	11/28/2017	Application #:	15425366	Filing Dt:	02/06/2017
Title:	EMBEDDED DRAM CELLS HAVING CAPACITORS WITHIN TRENCH SILICIDE TRENCHES OF A SEMICONDUCTOR STRUCTURE

Patent #:	10181420	Issue Dt:	01/15/2019	Application #:	15425478	Filing Dt:	02/06/2017
Publication #:	US20180226294	Pub Dt:	08/09/2018
Title:	DEVICES WITH CHAMFER-LESS VIAS MULTI-PATTERNING AND METHODS FOR FORMING CHAMFER-LESS VIAS

Patent #:	9935003	Issue Dt:	04/03/2018	Application #:	15426573	Filing Dt:	02/07/2017
Publication #:	US20170148668	Pub Dt:	05/25/2017
Title:	HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE

Patent #:	10079300	Issue Dt:	09/18/2018	Application #:	15426728	Filing Dt:	02/07/2017
Publication #:	US20170148919	Pub Dt:	05/25/2017
Title:	SEMICONDUCTOR CIRCUIT ELEMENT

Patent #:	10964687	Issue Dt:	03/30/2021	Application #:	15427128	Filing Dt:	02/08/2017
Publication #:	US20180226394	Pub Dt:	08/09/2018
Title:	FINFET ESD DEVICE WITH SCHOTTKY DIODE

Patent #:	10002835	Issue Dt:	06/19/2018	Application #:	15427156	Filing Dt:	02/08/2017
Publication #:	US20170148737	Pub Dt:	05/25/2017
Title:	STRUCTURE FOR ESTABLISHING INTERCONNECTS IN PACKAGES USING THIN INTERPOSERS

Patent #:	10964796	Issue Dt:	03/30/2021	Application #:	15427182	Filing Dt:	02/08/2017
Publication #:	US20180226347	Pub Dt:	08/09/2018
Title:	Heterojunction Bipolar Transistors With Stress Material For Improved Mobility

Patent #:	10163900	Issue Dt:	12/25/2018	Application #:	15427403	Filing Dt:	02/08/2017
Publication #:	US20180226402	Pub Dt:	08/09/2018
Title:	INTEGRATION OF VERTICAL FIELD-EFFECT TRANSISTORS AND SADDLE FIN-TYPE FIELD EFFECT TRANSISTORS

Patent #:	9947793	Issue Dt:	04/17/2018	Application #:	15427594	Filing Dt:	02/08/2017
Title:	VERTICAL PILLAR-TYPE FIELD EFFECT TRANSISTOR AND METHOD

Patent #:	10424657	Issue Dt:	09/24/2019	Application #:	15428312	Filing Dt:	02/09/2017
Publication #:	US20170154977	Pub Dt:	06/01/2017
Title:	TRI-GATE FINFET DEVICE

Patent #:	10360334	Issue Dt:	07/23/2019	Application #:	15428449	Filing Dt:	02/09/2017
Publication #:	US20180225406	Pub Dt:	08/09/2018
Title:	CONTEXT AWARE PROCESSING TO RESOLVE STRONG SPACING EFFECTS DUE TO STRAIN RELAXATION IN STANDARD CELL LIBRARY

Patent #:	9899319	Issue Dt:	02/20/2018	Application #:	15428604	Filing Dt:	02/09/2017
Publication #:	US20170154846	Pub Dt:	06/01/2017
Title:	RAISED E-FUSE

Patent #:	10020307	Issue Dt:	07/10/2018	Application #:	15429502	Filing Dt:	02/10/2017
Title:	INTEGRATED CIRCUIT STRUCTURE INCLUDING LATERALLY RECESSED SOURCE/DRAIN EPITAXIAL REGION AND METHOD OF FORMING SAME

Patent #:	10199265	Issue Dt:	02/05/2019	Application #:	15430039	Filing Dt:	02/10/2017
Publication #:	US20180233404	Pub Dt:	08/16/2018
Title:	VARIABLE SPACE MANDREL CUT FOR SELF ALIGNED DOUBLE PATTERNING

Patent #:	9953727	Issue Dt:	04/24/2018	Application #:	15430170	Filing Dt:	02/10/2017
Title:	CIRCUIT AND METHOD FOR DETECTING TIME DEPENDENT DIELECTRIC BREAKDOWN (TDDB) SHORTS AND SIGNAL-MARGIN TESTING

Patent #:	11557420	Issue Dt:	01/17/2023	Application #:	15430596	Filing Dt:	02/13/2017
Publication #:	US20170154722	Pub Dt:	06/01/2017
Title:	COUPLING INDUCTORS IN AN IC DEVICE USING INTERCONNECTING ELEMENTS WITH SOLDER CAPS AND RESULTING DEVICES

Patent #:	10056469	Issue Dt:	08/21/2018	Application #:	15430647	Filing Dt:	02/13/2017
Publication #:	US20180233579	Pub Dt:	08/16/2018
Title:	GATE CUT INTEGRATION AND RELATED DEVICE

Patent #:	9812453	Issue Dt:	11/07/2017	Application #:	15431334	Filing Dt:	02/13/2017
Title:	SELF-ALIGNED SACRIFICIAL EPITAXIAL CAPPING FOR TRENCH SILICIDE

Patent #:	9865570	Issue Dt:	01/09/2018	Application #:	15431915	Filing Dt:	02/14/2017
Title:	INTEGRATED CIRCUIT PACKAGE WITH THERMALLY CONDUCTIVE PILLAR

Patent #:	10453751	Issue Dt:	10/22/2019	Application #:	15432016	Filing Dt:	02/14/2017
Publication #:	US20180261510	Pub Dt:	09/13/2018
Title:	TONE INVERSION METHOD AND STRUCTURE FOR SELECTIVE CONTACT VIA PATTERNING

Patent #:	10128352	Issue Dt:	11/13/2018	Application #:	15432372	Filing Dt:	02/14/2017
Publication #:	US20170162438	Pub Dt:	06/08/2017
Title:	GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

Patent #:	10573534	Issue Dt:	02/25/2020	Application #:	15433099	Filing Dt:	02/15/2017
Publication #:	US20170236721	Pub Dt:	08/17/2017
Title:	RAPID HEATING PROCESS IN THE PRODUCTION OF SEMICONDUCTOR COMPONENTS

Patent #:	10658494	Issue Dt:	05/19/2020	Application #:	15433141	Filing Dt:	02/15/2017
Publication #:	US20180233583	Pub Dt:	08/16/2018
Title:	TRANSISTORS AND METHODS OF FORMING TRANSISTORS USING VERTICAL NANOWIRES

Patent #:	10249535	Issue Dt:	04/02/2019	Application #:	15433188	Filing Dt:	02/15/2017
Publication #:	US20180233412	Pub Dt:	08/16/2018
Title:	FORMING TS CUT FOR ZERO OR NEGATIVE TS EXTENSION AND RESULTING DEVICE

Patent #:	9847390	Issue Dt:	12/19/2017	Application #:	15434205	Filing Dt:	02/16/2017
Title:	SELF-ALIGNED WRAP-AROUND CONTACTS FOR NANOSHEET DEVICES

Patent #:	9935018	Issue Dt:	04/03/2018	Application #:	15436281	Filing Dt:	02/17/2017
Title:	METHODS OF FORMING VERTICAL TRANSISTOR DEVICES WITH DIFFERENT EFFECTIVE GATE LENGTHS

Patent #:	10290698	Issue Dt:	05/14/2019	Application #:	15437057	Filing Dt:	02/20/2017
Publication #:	US20170162647	Pub Dt:	06/08/2017
Title:	SUBSTRATE RESISTOR WITH OVERLYING GATE STRUCTURE

Patent #:	9805972	Issue Dt:	10/31/2017	Application #:	15437065	Filing Dt:	02/20/2017
Title:	SKIP VIA STRUCTURES

Patent #:	10026687	Issue Dt:	07/17/2018	Application #:	15437100	Filing Dt:	02/20/2017
Title:	METAL INTERCONNECTS FOR SUPER (SKIP) VIA INTEGRATION

Patent #:	10115810	Issue Dt:	10/30/2018	Application #:	15437168	Filing Dt:	02/20/2017
Publication #:	US20180240897	Pub Dt:	08/23/2018
Title:	HETEROJUNCTION BIPOLAR TRANSISTOR WITH A THICKENED EXTRINSIC BASE

Patent #:	9947545	Issue Dt:	04/17/2018	Application #:	15437837	Filing Dt:	02/21/2017
Publication #:	US20170243748	Pub Dt:	08/24/2017
Title:	METHODS FOR GATE FORMATION IN CIRCUIT STRUCTURES

Patent #:	10170585	Issue Dt:	01/01/2019	Application #:	15437840	Filing Dt:	02/21/2017
Publication #:	US20180240889	Pub Dt:	08/23/2018
Title:	SEMICONDUCTOR DEVICES HAVING EQUAL THICKNESS GATE SPACERS

Patent #:	10181522	Issue Dt:	01/15/2019	Application #:	15437846	Filing Dt:	02/21/2017
Publication #:	US20180240885	Pub Dt:	08/23/2018
Title:	SIMPLIFIED GATE TO SOURCE/DRAIN REGION CONNECTIONS

Patent #:	10347531	Issue Dt:	07/09/2019	Application #:	15438828	Filing Dt:	02/22/2017
Publication #:	US20180240703	Pub Dt:	08/23/2018
Title:	MIDDLE OF THE LINE (MOL) CONTACT FORMATION METHOD AND STRUCTURE

Patent #:	9929148	Issue Dt:	03/27/2018	Application #:	15439444	Filing Dt:	02/22/2017
Title:	SEMICONDUCTOR DEVICE INCLUDING BURIED CAPACITIVE STRUCTURES AND A METHOD OF FORMING THE SAME

Patent #:	9905472	Issue Dt:	02/27/2018	Application #:	15440072	Filing Dt:	02/23/2017
Title:	SILICON NITRIDE CESL REMOVAL WITHOUT GATE CAP HEIGHT LOSS AND RESULTING DEVICE

Patent #:	10191107	Issue Dt:	01/29/2019	Application #:	15440791	Filing Dt:	02/23/2017
Publication #:	US20180238958	Pub Dt:	08/23/2018
Title:	RANKING DEFECTS WITH YIELD IMPACTS

Patent #:	9806221	Issue Dt:	10/31/2017	Application #:	15441345	Filing Dt:	02/24/2017
Publication #:	US20170162743	Pub Dt:	06/08/2017
Title:	Germanium Photodetector with SOI Doping Source

Patent #:	10263013	Issue Dt:	04/16/2019	Application #:	15441711	Filing Dt:	02/24/2017
Publication #:	US20180247956	Pub Dt:	08/30/2018
Title:	METHOD OF FORMING AN INTEGRATED CIRCUIT (IC) WITH SHALLOW TRENCH ISOLATION (STI) REGIONS AND THE RESULTING IC STRUCTURE

100

Patent #:	10062748	Issue Dt:	08/28/2018	Application #:	15443276	Filing Dt:	02/27/2017
Publication #:	US20180248001	Pub Dt:	08/30/2018
Title:	SEGMENTED GUARD-RING AND CHIP EDGE SEALS

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

10/22/2020

Assignee

GLOBALFOUNDRIES U.S. INC.

2600 GREAT AMERICA WAY

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	GLOBALFOUNDRIES SINGAPORE PTE. LTD.
	60 WOODLANDS INDUSTRIAL PARK D STREET 2,
	SINGAPORE, 738406 SINGAPORE

Search Results as of: 05/24/2024 08:15 PM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6