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11/19/2019
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15795431
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10/27/2017
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05/02/2019
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07/16/2019
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15795833
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10/27/2017
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05/02/2019
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SINGLE-CURVATURE CAVITY FOR SEMICONDUCTOR EPITAXY
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05/07/2019
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15795849
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10/27/2017
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05/02/2019
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METHOD OF FORMING A PASSIVATION LAYER
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05/21/2019
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15795879
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10/27/2017
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05/02/2019
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DUAL-CURVATURE CAVITY FOR EPITAXIAL SEMICONDUCTOR GROWTH
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12/31/2019
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15797380
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10/30/2017
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05/02/2019
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SELECTIVE SHALLOW TRENCH ISOLATION (STI) FILL FOR STRESS ENGINEERING IN SEMICONDUCTOR STRUCTURES
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07/17/2018
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15797533
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10/30/2017
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05/14/2019
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15797606
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10/30/2017
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05/02/2019
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LDMOS FINFET STRUCTURES WITH SHALLOW TRENCH ISOLATION INSIDE THE FIN
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02/12/2019
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15797633
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10/30/2017
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11/06/2018
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15797634
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10/30/2017
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03/01/2018
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INTEGRATED CIRCUIT STRUCTURE WITHOUT GATE CONTACT AND METHOD OF FORMING SAME
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12/25/2018
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15797701
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10/30/2017
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11/19/2019
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15797723
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10/30/2017
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05/02/2019
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12/25/2018
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15797794
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10/30/2017
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10/22/2019
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10/30/2017
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05/02/2019
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METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON TRANSISTOR DEVICES
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12/25/2018
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10/31/2017
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07/17/2018
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15799243
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10/31/2017
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02/22/2018
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10/29/2019
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15799600
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10/31/2017
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03/08/2018
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THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES
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09/25/2018
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15800551
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11/01/2017
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06/21/2018
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INTERCONNECTION LINES HAVING VARIABLE WIDTHS AND PARTIALLY SELF-ALIGNED CONTINUITY CUTS
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05/07/2019
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15800563
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11/01/2017
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05/02/2019
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HYBRID SPACER INTEGRATION FOR FIELD-EFFECT TRANSISTORS
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02/19/2019
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15800905
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11/01/2017
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03/19/2019
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15801023
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11/01/2017
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03/01/2018
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METHODS, APPARATUS AND SYSTEM FOR STI RECESS CONTROL FOR HIGHLY SCALED FINFET DEVICES
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03/05/2019
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15801458
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11/02/2017
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03/08/2018
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FORMING A CONTACT FOR A TALL FIN TRANSISTOR
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10/15/2019
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15801501
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11/02/2017
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06/14/2018
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THROUGH-SILICON VIA WITH IMPROVED SUBSTRATE CONTACT FOR REDUCED THROUGH-SILICON VIA (TSV) CAPACITANCE VARIABILITY
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06/30/2020
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15804165
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11/06/2017
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05/09/2019
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SEMICONDUCTOR TEST STRUCTURE AND METHOD FOR FORMING THE SAME
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09/03/2019
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15804556
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11/06/2017
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05/09/2019
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NOVEL SIX-TRANSISTOR (6T) SRAM CELL STRUCTURE
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12/17/2019
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15805282
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11/07/2017
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05/09/2019
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VERTICALLY ORIENTED METAL SILICIDE CONTAINING E-FUSE DEVICE AND METHODS OF MAKING SAME
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11/06/2018
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15806532
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11/08/2017
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03/08/2018
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FABRICATION OF INTEGRATED CIRCUIT STRUCTURES FOR BIPOLOR TRANSISTORS
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02/05/2019
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15806931
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11/08/2017
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07/09/2019
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15810557
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11/13/2017
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05/16/2019
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FDSOI SEMICONDUCTOR DEVICE WITH CONTACT ENHANCEMENT LAYER AND METHOD OF MANUFACTURING
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05/07/2019
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15810638
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11/13/2017
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05/16/2019
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TECHNIQUE AND RELATED SEMICONDUCTOR DEVICES BASED ON CRYSTALLINE SEMICONDUCTOR MATERIAL FORMED ON THE BASIS OF DEPOSITED AMORPHOUS SEMICONDUCTOR MATERIAL
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01/01/2019
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15811745
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11/14/2017
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FORMING LONG CHANNEL FinFET WITH SHORT CHANNEL VERTICAL FinFET AND RELATED INTEGRATED CIRCUIT
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12/18/2018
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15811953
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11/14/2017
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FORMING OF MARKING TRENCHES IN STRUCTURE FOR MULTIPLE PATTERNING LITHOGRAPHY
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10/02/2018
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15811957
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11/14/2017
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08/20/2019
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11/14/2017
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05/16/2019
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09/03/2019
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15811965
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11/14/2017
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05/16/2019
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10/29/2019
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15811990
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11/14/2017
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05/16/2019
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03/05/2019
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15813399
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11/15/2017
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03/15/2018
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FORMING AIR GAP
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10/09/2018
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15813471
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11/15/2017
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01/29/2019
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15814435
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11/16/2017
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05/28/2019
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15814440
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11/16/2017
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05/16/2019
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10/02/2018
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15814445
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11/16/2017
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INTEGRATED CIRCUIT STRUCTURE INCORPORATING A STACKED PAIR OF FIELD EFFECT TRANSISTORS AND A BURIED INTERCONNECT AND METHOD
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04/23/2019
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15814724
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11/16/2017
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05/16/2019
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FORMING CONTACTS FOR VFETS
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03/03/2020
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15815308
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11/16/2017
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05/16/2019
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HIGH-DENSITY METAL-INSULATOR-METAL CAPACITORS
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03/12/2019
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15815857
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11/17/2017
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03/15/2018
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EPITAXIAL AND SILICIDE LAYER FORMATION AT TOP AND BOTTOM SURFACES OF SEMICONDUCTOR FINS
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01/29/2019
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15817362
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11/20/2017
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03/29/2018
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METHOD TO IMPROVE CRYSTALLINE REGROWTH
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03/05/2019
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15817629
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11/20/2017
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DEEP TRENCH ISOLATION STRUCTURES
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03/10/2020
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15819213
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11/21/2017
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03/07/2019
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SEMICONDUCTOR FABRICATION DESIGN RULE LOOPHOLE CHECKING FOR DESIGN FOR MANUFACTURABILITY OPTIMIZATION
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02/23/2021
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15819825
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11/21/2017
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05/23/2019
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LATERALLY DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) DEVICE ON FULLY DEPLETED SILICON ON INSULATOR (FDSOI) ENABLING HIGH INPUT VOLTAGE
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04/09/2019
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15820477
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11/22/2017
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INSULATED EPITAXIAL STRUCTURES IN NANOSHEET COMPLEMENTARY FIELD EFFECT TRANSISTORS
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09/03/2019
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15820602
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11/22/2017
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04/05/2018
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METHOD TO REDUCE RESISTANCE FOR A COPPER (CU) INTERCONNECT LANDING ON MULTILAYERED METAL CONTACTS, AND SEMICONDUCTOR STRUCTURES FORMED THEREFROM
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11/19/2019
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15821091
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11/22/2017
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04/05/2018
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DEVICES AND METHODS OF FORMING UNMERGED EPITAXY FOR FINFET DEVICE
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10/08/2019
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15821684
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11/22/2017
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05/23/2019
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METHODS, APPARATUS AND SYSTEM FOR FORMING A FINFET DEVICE COMPRISING A FIRST PORTION CAPABLE OF OPERATING AT A FIRST VOLTAGE AND A SECOND PORTION CAPABLE OF OPERATING AT A SECOND VOLTAGE
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03/29/2022
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15822661
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11/27/2017
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05/30/2019
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PRODUCING MODELS FOR DYNAMICALLY DEPLETED TRANSISTORS USING SYSTEMS HAVING SIMULATION CIRCUITS
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12/29/2020
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15823899
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11/28/2017
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05/30/2019
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FINFET WITH ETCH-SELECTIVE SPACER AND SELF-ALIGNED CONTACT CAPPING LAYER
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07/16/2019
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15824293
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11/28/2017
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05/30/2019
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LITHO-LITHO-ETCH DOUBLE PATTERNING METHOD
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07/23/2019
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15825409
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11/29/2017
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03/29/2018
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SEMICONDUCTOR STRUCTURE INCLUDING LOW-K SPACER MATERIAL
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05/07/2019
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15826799
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11/30/2017
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08/16/2018
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Methods of Forming Integrated Circuit Package with Thermally Conductive Pillar
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07/07/2020
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15826939
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11/30/2017
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03/29/2018
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CONTACTS TO SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING SAME
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04/16/2019
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15828386
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11/30/2017
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METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR SELF-ALIGNED PATTERNING OF CONTACTS IN A VERTICAL FIELD EFFECT TRANSISTOR
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08/14/2018
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15828624
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12/01/2017
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03/29/2018
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DIRECTED SURFACE FUNCTIONALIZATION ON SELECTED SURFACE AREAS OF TOPOGRAPHICAL FEATURES WITH NANOMETER RESOLUTION
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12/04/2018
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15830217
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12/04/2017
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Title:
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VERTICAL FIN GATE STRUCTURE FOR RF DEVICE
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Patent #:
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Issue Dt:
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12/10/2019
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Application #:
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15830671
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Filing Dt:
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12/04/2017
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Title:
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FINFET SRAM LAYOUT AND METHOD OF MAKING THE SAME
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Patent #:
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Issue Dt:
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04/02/2019
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Application #:
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15831833
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Filing Dt:
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12/05/2017
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Publication #:
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Pub Dt:
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04/19/2018
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Title:
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FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/01/2019
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Application #:
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15833285
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Filing Dt:
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12/06/2017
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Publication #:
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Pub Dt:
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04/12/2018
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Title:
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INTEGRATED CIRCUIT PRODUCTS THAT INCLUDE FINFET DEVICES AND A PROTECTION LAYER FORMED ON AN ISOLATION REGION
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Patent #:
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Issue Dt:
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06/11/2019
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Application #:
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15834151
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Filing Dt:
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12/07/2017
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Publication #:
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Pub Dt:
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06/13/2019
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Title:
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INTERCONNECTS WITH CUTS FORMED BY BLOCK PATTERNING
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Patent #:
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Issue Dt:
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02/18/2020
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Application #:
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15834443
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Filing Dt:
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12/07/2017
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Publication #:
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Pub Dt:
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06/13/2019
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Title:
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ON-CHIP RESISTORS WITH DIRECT WIRING CONNECTIONS
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Patent #:
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Issue Dt:
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05/08/2018
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Application #:
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15837279
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Filing Dt:
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12/11/2017
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Publication #:
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Pub Dt:
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04/19/2018
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Title:
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INTEGRATED CIRCUIT STRUCTURE HAVING DEEP TRENCH CAPACITOR AND THROUGH-SILICON VIA AND METHOD OF FORMING SAME
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Patent #:
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Issue Dt:
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12/03/2019
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Application #:
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15837671
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Filing Dt:
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12/11/2017
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Publication #:
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Pub Dt:
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06/13/2019
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Title:
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METHODS OF FORMING CONTACT STRUCTURES ON INTEGRATED CIRCUIT PRODUCTS
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Patent #:
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Issue Dt:
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05/12/2020
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Application #:
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15840835
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Filing Dt:
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12/13/2017
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Publication #:
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Pub Dt:
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04/26/2018
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Title:
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METHODS OF SIMULTANEOUSLY FORMING BOTTOM AND TOP SPACERS ON A VERTICAL TRANSISTOR DEVICE
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Patent #:
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Issue Dt:
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02/19/2019
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Application #:
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15841372
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Filing Dt:
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12/14/2017
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Title:
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DISSIPATION OF STATIC CHARGE FROM WIRING LAYERS DURING MANUFACTURING
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Patent #:
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Issue Dt:
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07/03/2018
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Application #:
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15844840
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Filing Dt:
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12/18/2017
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Title:
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METHOD OF FORMING FIELD EFFECT TRANSISTORS WITH REPLACEMENT METAL GATES AND CONTACTS AND RESULTING STRUCTURE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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15845313
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Filing Dt:
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12/18/2017
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Publication #:
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Pub Dt:
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06/21/2018
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Title:
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METHOD AND SYSTEM FOR NON-DESTRUCTIVE METROLOGY OF THIN LAYERS
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Patent #:
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Issue Dt:
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05/28/2019
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Application #:
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15845340
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Filing Dt:
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12/18/2017
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Publication #:
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Pub Dt:
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05/02/2019
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Title:
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EARLY GATE SILICIDATION IN TRANSISTOR ELEMENTS
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Patent #:
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Issue Dt:
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03/12/2019
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Application #:
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15846365
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Filing Dt:
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12/19/2017
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Publication #:
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Pub Dt:
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05/03/2018
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Title:
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METHODS OF FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING DEVICES
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Patent #:
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Issue Dt:
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08/06/2019
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Application #:
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15848324
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Filing Dt:
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12/20/2017
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Publication #:
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Pub Dt:
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05/03/2018
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Title:
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SEMICONDUCTOR DEVICE RESISTOR STRUCTURE
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Patent #:
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Issue Dt:
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12/25/2018
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Application #:
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15848371
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Filing Dt:
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12/20/2017
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Publication #:
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Pub Dt:
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05/17/2018
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Title:
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ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MATERIALS AND FABRICATION METHODS
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Patent #:
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Issue Dt:
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03/19/2019
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Application #:
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15848591
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Filing Dt:
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12/20/2017
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Publication #:
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Pub Dt:
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07/05/2018
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Title:
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STRAIN RETENTION SEMICONDUCTOR MEMBER FOR CHANNEL SIGE LAYER OF PFET
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Patent #:
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Issue Dt:
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05/07/2019
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Application #:
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15851774
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Filing Dt:
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12/22/2017
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Publication #:
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Pub Dt:
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06/28/2018
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Title:
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MIDDLE OF THE LINE (MOL) CONTACTS WITH TWO-DIMENSIONAL SELF-ALIGNMENT
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Patent #:
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Issue Dt:
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10/23/2018
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Application #:
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15856205
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Filing Dt:
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12/28/2017
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Title:
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CROSS COUPLE STRUCTURE FOR VERTICAL TRANSISTORS
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Patent #:
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Issue Dt:
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03/03/2020
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Application #:
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15856525
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Filing Dt:
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12/28/2017
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Publication #:
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Pub Dt:
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05/03/2018
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Title:
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CONTACT MODULE FOR OPTIMIZING EMITTER AND CONTACT RESISTANCE
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Patent #:
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Issue Dt:
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02/05/2019
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Application #:
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15857202
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Filing Dt:
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12/28/2017
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Publication #:
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Pub Dt:
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05/03/2018
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Title:
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SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET STANDARD CELLS
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Patent #:
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Issue Dt:
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12/04/2018
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Application #:
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15858594
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Filing Dt:
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12/29/2017
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Publication #:
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Pub Dt:
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09/20/2018
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Title:
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METHOD AND DEVICE FOR MEASURING PLATING RING ASSEMBLY DIMENSIONS
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Patent #:
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Issue Dt:
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05/28/2019
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Application #:
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15858673
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Filing Dt:
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12/29/2017
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Publication #:
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Pub Dt:
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05/03/2018
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Title:
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PRODUCING WAFER LEVEL PACKAGING USING LEADFRAME STRIP AND RELATED DEVICE
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Patent #:
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Issue Dt:
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05/05/2020
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Application #:
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15860161
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Filing Dt:
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01/02/2018
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Publication #:
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Pub Dt:
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07/04/2019
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Title:
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REPAIRED MASK STRUCTURES AND RESULTANT UNDERLYING PATTERNED STRUCTURES
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Patent #:
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Issue Dt:
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03/10/2020
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Application #:
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15860171
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Filing Dt:
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01/02/2018
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Publication #:
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Pub Dt:
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07/04/2019
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Title:
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INTERRUPTED SMALL BLOCK SHAPE
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Patent #:
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Issue Dt:
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07/09/2019
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Application #:
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15860193
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Filing Dt:
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01/02/2018
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Publication #:
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Pub Dt:
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07/04/2019
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Title:
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METHODS OF PATTERNING DIELECTRIC LAYERS FOR METALLIZATION AND RELATED STRUCTURES
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Patent #:
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Issue Dt:
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07/02/2019
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Application #:
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15860318
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Filing Dt:
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01/02/2018
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Publication #:
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Pub Dt:
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07/04/2019
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Title:
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COBALT PLATED VIA INTEGRATION SCHEME
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Patent #:
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Issue Dt:
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11/19/2019
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Application #:
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15860775
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Filing Dt:
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01/03/2018
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Publication #:
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Pub Dt:
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07/04/2019
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Title:
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OVERLAY STRUCTURES
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Patent #:
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Issue Dt:
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09/10/2019
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Application #:
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15860840
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Filing Dt:
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01/03/2018
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Publication #:
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Pub Dt:
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07/04/2019
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Title:
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MULTIPLE GATE LENGTH DEVICE WITH SELF-ALIGNED TOP JUNCTION
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Patent #:
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Issue Dt:
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03/19/2019
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Application #:
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15861097
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Filing Dt:
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01/03/2018
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Title:
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CROSS-COUPLED CONTACT STRUCTURE ON IC PRODUCTS AND METHODS OF MAKING SUCH CONTACT STRUCTURES
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Patent #:
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Issue Dt:
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08/13/2019
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Application #:
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15861161
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Filing Dt:
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01/03/2018
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Publication #:
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Pub Dt:
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07/04/2019
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Title:
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CONTACT STRUCTURES AND METHODS OF MAKING THE CONTACT STRUCTURES
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Patent #:
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Issue Dt:
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07/30/2019
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Application #:
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15861799
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Filing Dt:
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01/04/2018
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Publication #:
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Pub Dt:
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07/04/2019
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Title:
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METHODS OF PATTERNING VARIABLE WIDTH METALLIZATION LINES
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Patent #:
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Issue Dt:
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09/10/2019
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Application #:
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15862064
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Filing Dt:
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01/04/2018
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Publication #:
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Pub Dt:
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06/28/2018
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Title:
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TALL SINGLE-FIN FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURES AND METHODS
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Patent #:
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Issue Dt:
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03/05/2019
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Application #:
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15863113
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Filing Dt:
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01/05/2018
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Title:
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SOLUBLE SELF ALIGNED BARRIER LAYER FOR INTERCONNECT STRUCTURE
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Patent #:
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Issue Dt:
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08/13/2019
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Application #:
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15865973
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Filing Dt:
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01/09/2018
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Publication #:
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Pub Dt:
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07/11/2019
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Title:
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TRANSISTORS WITH H-SHAPED OR U-SHAPED CHANNELS AND METHOD FOR FORMING THE SAME
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Patent #:
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Issue Dt:
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09/17/2019
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Application #:
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15866855
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Filing Dt:
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01/10/2018
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Publication #:
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Pub Dt:
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07/11/2019
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Title:
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CIRCUITS BASED ON COMPLEMENTARY FIELD-EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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10/01/2019
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Application #:
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15867036
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Filing Dt:
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01/10/2018
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Publication #:
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Pub Dt:
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07/11/2019
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Title:
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METHOD OF FORMING INTEGRATED CIRCUIT WITH GATE-ALL-AROUND FIELD EFFECT TRANSISTOR AND THE RESULTING STRUCTURE
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Patent #:
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Issue Dt:
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06/30/2020
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Application #:
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15867118
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Filing Dt:
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01/10/2018
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Publication #:
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Pub Dt:
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07/11/2019
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Title:
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IC WAFER FOR IDENTIFICATION OF CIRCUIT DIES AFTER DICING
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Patent #:
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Issue Dt:
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05/04/2021
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Application #:
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15867854
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Filing Dt:
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01/11/2018
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Publication #:
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Pub Dt:
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07/11/2019
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Title:
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UNIFORMITY CONTROL OF METAL-BASED PHOTORESISTS
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Patent #:
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Issue Dt:
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06/04/2019
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Application #:
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15867894
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Filing Dt:
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01/11/2018
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Title:
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INTERCONNECT STRUCTURE WITH METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
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11/12/2019
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Application #:
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15868004
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Filing Dt:
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01/11/2018
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Publication #:
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Pub Dt:
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07/11/2019
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Title:
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METHODS OF FORMING MERGED SOURCE/DRAIN REGIONS ON INTEGRATED CIRCUIT PRODUCTS
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