|
|
Patent #:
|
|
Issue Dt:
|
08/02/2005
|
Application #:
|
10724377
|
Filing Dt:
|
11/28/2003
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10724470
|
Filing Dt:
|
11/26/2003
|
Publication #:
|
|
Pub Dt:
|
06/10/2004
| | | | |
Title:
|
SYSTEM AND METHOD FOR MANAGING A CACHE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10724472
|
Filing Dt:
|
11/26/2003
|
Publication #:
|
|
Pub Dt:
|
06/10/2004
| | | | |
Title:
|
SYSTEM AND METHOD FOR MANAGING A CACHE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
10724534
|
Filing Dt:
|
11/26/2003
|
Publication #:
|
|
Pub Dt:
|
06/10/2004
| | | | |
Title:
|
SYSTEM AND METHOD FOR MANAGING A CACHE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2005
|
Application #:
|
10724648
|
Filing Dt:
|
12/01/2003
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10725481
|
Filing Dt:
|
12/03/2003
|
Publication #:
|
|
Pub Dt:
|
06/10/2004
| | | | |
Title:
|
INTERCONNECT LINE SELECTIVELY ISOLATED FROM AN UNDERLYING CONTACT PLUG
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2006
|
Application #:
|
10725557
|
Filing Dt:
|
12/03/2003
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
Title:
|
MEMORY ARCHITECTURE AND METHOD OF MANUFACTURE AND OPERATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
10725981
|
Filing Dt:
|
12/02/2003
|
Publication #:
|
|
Pub Dt:
|
06/10/2004
| | | | |
Title:
|
CIRCUIT BOARD SINGULATION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10726265
|
Filing Dt:
|
12/02/2003
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
Title:
|
HIGH VOLTAGE GENERATION AND REGULATION CIRCUIT IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
10726328
|
Filing Dt:
|
12/01/2003
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
Title:
|
METHODS OF FORMING PARTICLE-CONTAINING MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
10726439
|
Filing Dt:
|
12/03/2003
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
Title:
|
COMPENSATED REFRESH OSCILLATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2005
|
Application #:
|
10727087
|
Filing Dt:
|
12/02/2003
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
Title:
|
NO-PRECHARGE FAMOS CELL AND LATCH CIRCUIT IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10727150
|
Filing Dt:
|
12/03/2003
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
Title:
|
MEMORY DEVICE COMPOSED OF A PLURALITY OF MEMORY CHIPS IN A SINGLE PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2006
|
Application #:
|
10727341
|
Filing Dt:
|
11/26/2003
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
Title:
|
NON-VOLATILE MEMORY DEVICE ARCHITECTURE, FOR INSTANCE A FLASH KIND, HAVING A SERIAL COMMUNICATION INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10727478
|
Filing Dt:
|
12/04/2003
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2005
|
Application #:
|
10727742
|
Filing Dt:
|
12/04/2003
|
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2005
|
Application #:
|
10727887
|
Filing Dt:
|
12/04/2003
|
Publication #:
|
|
Pub Dt:
|
06/10/2004
| | | | |
Title:
|
HIGH COUPLING FLOATING GATE TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
10727889
|
Filing Dt:
|
12/04/2003
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
Title:
|
METHOD AND APPARATUS FOR REDUCING FIXED CHARGE IN SEMICONDUCTOR DEVICE LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10728372
|
Filing Dt:
|
12/04/2003
|
Publication #:
|
|
Pub Dt:
|
08/19/2004
| | | | |
Title:
|
NON-VOLATILE MEMORY CELL SENSING CIRCUIT, PARTICULARLY FOR LOW POWER SUPPLY VOLTAGES AND HIGH CAPACITIVE LOAD VALUES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
10728395
|
Filing Dt:
|
12/05/2003
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
Title:
|
SMALLER AND LOWER POWER STATIC MUX CIRCUITRY IN GENERATING MULTIPLIER PARTIAL PRODUCT SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
10728413
|
Filing Dt:
|
12/05/2003
|
Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
Title:
|
QUAD FLAT NO LEAD (QFN) GRID ARRAY PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
10728526
|
Filing Dt:
|
12/05/2003
|
Publication #:
|
|
Pub Dt:
|
06/17/2004
| | | | |
Title:
|
METHOD AND APPARATUS FOR CONDITIONING A CHEMICAL-MECHANICAL POLISHING PAD
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10728977
|
Filing Dt:
|
12/08/2003
|
Publication #:
|
|
Pub Dt:
|
06/17/2004
| | | | |
Title:
|
MEMORY CIRCUITRY AND METHOD OF FORMING MEMORY CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10729180
|
Filing Dt:
|
12/05/2003
|
Publication #:
|
|
Pub Dt:
|
06/17/2004
| | | | |
Title:
|
QUAD FLAT NO-LEAD (QFN) GRID ARRAY PACKAGE, METHOD OF MAKING AND MEMORY MODULE AND COMPUTER SYSTEM INCLUDING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10729829
|
Filing Dt:
|
12/05/2003
|
Publication #:
|
|
Pub Dt:
|
09/02/2004
| | | | |
Title:
|
METHOD AND DEVICE FOR PROGRAMMING AN ELECTRICALLY PROGRAMMABLE NON-VOLATILE SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10729875
|
Filing Dt:
|
12/05/2003
|
Publication #:
|
|
Pub Dt:
|
09/02/2004
| | | | |
Title:
|
METHOD AND DEVICE FOR PROGRAMMING AN ELECTRICALLY PROGRAMMABLE NON-VOLATILE SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2005
|
Application #:
|
10730548
|
Filing Dt:
|
12/08/2003
|
Publication #:
|
|
Pub Dt:
|
06/17/2004
| | | | |
Title:
|
PROBE CARD FOR TESTING MICROELECTRONIC COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2005
|
Application #:
|
10730641
|
Filing Dt:
|
12/08/2003
|
Publication #:
|
|
Pub Dt:
|
08/05/2004
| | | | |
Title:
|
A SEMICONDUCTOR DEVICE COMPRISING LOW DIELECTRIC CONSTANT STI WITH SOI DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10731177
|
Filing Dt:
|
12/09/2003
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
WIRE-BONDED PACKAGE WITH ELECTRICALLY INSULATING WIRE ENCAPSULANT AND THERMALLY CONDUCTIVE OVERMOLD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10731480
|
Filing Dt:
|
12/10/2003
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
Title:
|
METHOD OF FORMING METAL LINE IN SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
10731567
|
Filing Dt:
|
12/08/2003
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR PREDICTION FOR FORK AND JOIN INSTRUCTIONS IN SPECULATIVE EXECUTION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2005
|
Application #:
|
10732962
|
Filing Dt:
|
12/11/2003
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
Title:
|
EVEN NUCLEATION BETWEEN SILICON AND OXIDE SURFACES FOR THIN SILICON NITRIDE FILM GROWTH
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
10733201
|
Filing Dt:
|
12/09/2003
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
Title:
|
ATOMIC LAYER DEPOSITION METHOD OF DEPOSITING AN OXIDE ON A SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
|
Application #:
|
10733226
|
Filing Dt:
|
12/10/2003
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
Title:
|
MICROELECTRONIC DEVICES AND METHODS FOR FILLING VIAS IN MICROELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10733474
|
Filing Dt:
|
12/12/2003
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
Title:
|
CURRENT MODE LOGIC SCHEME AND CIRCUIT FOR MATCHLINE SENSE AMPLIFIER DESIGN USING CONSTANT CURRENT BIAS CASCODE CURRENT MIRRORS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
10733523
|
Filing Dt:
|
12/10/2003
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
Title:
|
METHODS AND SYSTEMS FOR CONTROLLING TEMPERATURE DURING MICROFEATURE WORKPIECE PROCESSING, E.G., CVD DEPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
10733605
|
Filing Dt:
|
12/11/2003
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
Title:
|
SWITCHED CAPACITOR FOR A TUNABLE DELAY CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2007
|
Application #:
|
10733896
|
Filing Dt:
|
11/26/2003
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
Title:
|
SYSTEM AND METHOD FOR MANIPULATING CACHE DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2008
|
Application #:
|
10734201
|
Filing Dt:
|
12/15/2003
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
Title:
|
DEVICE HAVING IMPROVED SURFACE PLANARITY PRIOR TO MRAM BIT MATERIAL DEPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2005
|
Application #:
|
10734202
|
Filing Dt:
|
12/15/2003
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
Title:
|
DEVICE WITH LAYER EDGES SEPARATED THROUGH MECHANICAL SPACING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
10734260
|
Filing Dt:
|
12/15/2003
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
Title:
|
METAL TO POLYSILICON CONTACT IN OXYGEN ENVIRONMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2006
|
Application #:
|
10734339
|
Filing Dt:
|
12/11/2003
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
Title:
|
DIGITAL FREQUENCY-MULTIPLYING DLLS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10734438
|
Filing Dt:
|
12/11/2003
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
Title:
|
BIT LINE CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
10734525
|
Filing Dt:
|
12/11/2003
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
Title:
|
METHOD OF REMOVING RESIDUAL CONTAMINANTS FROM AN ENVIRONMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10734533
|
Filing Dt:
|
12/12/2003
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
METHOD FOR MANUFACTURING FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10734663
|
Filing Dt:
|
12/11/2003
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
Title:
|
METHOD FOR MANUFACTURE OF MAGNETO-RESISTIVE BIT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
10734999
|
Filing Dt:
|
12/12/2003
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
Title:
|
DEPOSITION METHODS WITH TIME SPACED AND TIME ABUTTING PRECURSOR PULSES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
10735250
|
Filing Dt:
|
12/12/2003
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
Title:
|
MEMORY SYSTEM COMPRISING A SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2006
|
Application #:
|
10735355
|
Filing Dt:
|
12/12/2003
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
Title:
|
WAFER BONDING METHOD OF FORMING SILICON-ON-INSULATOR COMPRISING INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10736244
|
Filing Dt:
|
12/15/2003
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
Title:
|
SEMICONDUCTOR DEVICES INCLUDING PERIPHERALLY LOCATED BOND PADS, INTERMEDIATES THEREOF, ASSEMBLIES, AND PACKAGES INCLUDING THE SEMICONDUCTOR DEVICES, AND SUPPORT ELEMENTS FOR THE SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2006
|
Application #:
|
10736617
|
Filing Dt:
|
12/17/2003
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
Title:
|
NON-VOLATILE RESISTANCE VARIABLE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10736719
|
Filing Dt:
|
12/16/2003
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
Title:
|
HIGH VOLTAGE TRANSFER CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
|
Application #:
|
10736805
|
Filing Dt:
|
12/15/2003
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
Title:
|
METHODS OF FORMING ELECTRONIC COMPONENTS, AND A CONDUCTIVE LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
10738408
|
Filing Dt:
|
12/16/2003
|
Publication #:
|
|
Pub Dt:
|
07/08/2004
| | | | |
Title:
|
NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10738556
|
Filing Dt:
|
12/17/2003
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
Title:
|
VERTICAL NAND FLASH MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2007
|
Application #:
|
10738783
|
Filing Dt:
|
12/17/2003
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
Title:
|
VERTICAL NROM NAND FLASH MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10738827
|
Filing Dt:
|
12/16/2003
|
Publication #:
|
|
Pub Dt:
|
07/08/2004
| | | | |
Title:
|
SMALL SCALE ACTUATORS AND METHODS FOR THEIR FORMATION AND USE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10739253
|
Filing Dt:
|
12/18/2003
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
Title:
|
FLASH MEMORY HAVING A HIGH-PERMITTIVITY TUNNEL DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2006
|
Application #:
|
10739767
|
Filing Dt:
|
12/18/2003
|
Publication #:
|
|
Pub Dt:
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07/08/2004
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Title:
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WRITE ONCE READ ONLY MEMORY EMPLOYING CHARGE TRAPPING IN INSULATORS
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Patent #:
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Issue Dt:
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09/06/2005
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Application #:
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10739928
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Filing Dt:
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12/18/2003
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Publication #:
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Pub Dt:
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08/26/2004
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Title:
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NON-VOLATILE MEMORY DEVICE WITH IMPROVED SEQUENTIAL PROGRAMMING SPEED
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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10740100
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Filing Dt:
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12/18/2003
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Publication #:
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Pub Dt:
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12/30/2004
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Title:
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METHOD FOR READING FLASH MEMORY CELL, NAND-TYPE FLASH MEMORY APPARATUS, AND NOR-TYPE FLASH MEMORY APPARATUS
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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10741100
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Filing Dt:
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12/19/2003
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Publication #:
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Pub Dt:
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07/08/2004
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Title:
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AIR SOCKET FOR TESTING INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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05/01/2012
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Application #:
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10741129
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Filing Dt:
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12/19/2003
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Publication #:
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Pub Dt:
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03/10/2005
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Title:
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FASTER WRITE OPERATIONS TO NONVOLATILE MEMORY USING FSINFO SECTOR MANIPULATION
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Patent #:
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Issue Dt:
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10/17/2006
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Application #:
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10741774
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Filing Dt:
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12/18/2003
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Publication #:
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Pub Dt:
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06/23/2005
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Title:
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COLOR IMAGE SENSOR WITH IMAGING ELEMENTS IMAGING ON RESPECTIVE REGIONS OF SENSOR ELEMENTS
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10741804
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Filing Dt:
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12/19/2003
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Publication #:
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Pub Dt:
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08/19/2004
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Title:
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SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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01/13/2009
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Application #:
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10741815
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Filing Dt:
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12/18/2003
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Publication #:
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Pub Dt:
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09/09/2004
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Title:
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STRUCTURE AND METHOD FOR DETECTING ERRORS IN A MULTILEVEL MEMORY DEVICE WITH IMPROVED PROGRAMMING GRANULARITY
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Patent #:
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Issue Dt:
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10/11/2005
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Application #:
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10742181
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Filing Dt:
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12/19/2003
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Publication #:
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Pub Dt:
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07/08/2004
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Title:
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STRING PROGRAMMABLE NONVOLATILE MEMORY WITH NOR ARCHITECTURE
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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10742429
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Filing Dt:
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12/19/2003
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Publication #:
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Pub Dt:
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07/08/2004
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Title:
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STRING PROGRAMMABLE NONVOLATILE MEMORY WITH NOR ARCHITECTURE
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Patent #:
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Issue Dt:
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05/05/2009
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Application #:
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10744206
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Filing Dt:
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12/22/2003
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Publication #:
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Pub Dt:
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06/23/2005
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Title:
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CLOCK SIGNAL DISTRIBUTION WITH REDUCED PARASITIC LOADING EFFECTS
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10744495
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Filing Dt:
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12/23/2003
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Title:
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METHOD OF FORMING GATE ELECTRODE IN FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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05/11/2010
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Application #:
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10744632
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Filing Dt:
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12/23/2003
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Publication #:
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Pub Dt:
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11/11/2004
| | | | |
Title:
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METHOD FOR PACKAGING CIRCUITS AND PACKAGED CIRCUITS
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Patent #:
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Issue Dt:
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10/30/2007
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Application #:
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10744664
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Filing Dt:
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12/23/2003
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Publication #:
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Pub Dt:
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06/23/2005
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Title:
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REWRITABLE FUSE MEMORY
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Patent #:
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Issue Dt:
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08/22/2006
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Application #:
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10744778
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Filing Dt:
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12/23/2003
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Publication #:
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Pub Dt:
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07/15/2004
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Title:
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SENDING SIGNAL THROUGH INTEGRATED CIRCUIT DURING SETUP TIME
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Patent #:
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Issue Dt:
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06/21/2005
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Application #:
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10744931
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Filing Dt:
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12/22/2003
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Publication #:
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Pub Dt:
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09/16/2004
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Title:
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METHODS FOR FORMING WORDLINES, TRANSISTOR GATES, AND CONDUCTIVE INTERCONNECTS, AND WORDLINE, TRANSISTOR GATE, AND CONDUCTIVE INTERCONNECT STRUCTURES
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Patent #:
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Issue Dt:
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05/01/2007
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Application #:
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10745008
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Filing Dt:
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12/23/2003
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Publication #:
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Pub Dt:
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05/19/2005
| | | | |
Title:
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METHOD OF MANUFACTURING FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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07/05/2005
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Application #:
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10745040
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Filing Dt:
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12/22/2003
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Publication #:
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Pub Dt:
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07/15/2004
| | | | |
Title:
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SEMICONDUCTOR COMPONENT WITH ELECTRICAL CHARACTERISTIC ADJUSTMENT CIRCUITRY
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Patent #:
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Issue Dt:
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04/04/2006
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Application #:
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10745295
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Filing Dt:
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12/23/2003
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Publication #:
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Pub Dt:
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09/30/2004
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Title:
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MOS DEVICE AND PROCESS FOR MANUFACTURING MOS DEVICES USING DUAL-POLYSILICON LAYER TECHNOLOGY
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Patent #:
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Issue Dt:
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08/15/2006
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Application #:
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10745297
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Filing Dt:
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12/23/2003
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Publication #:
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Pub Dt:
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06/02/2005
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Title:
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MOS DEVICE AND A PROCESS FOR MANUFACTURING MOS DEVICES USING A DUAL-POLYSILICON LAYER TECHNOLOGY WITH SIDE CONTACT
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Patent #:
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Issue Dt:
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03/27/2007
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Application #:
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10745311
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Filing Dt:
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12/22/2003
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Publication #:
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Pub Dt:
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07/15/2004
| | | | |
Title:
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METHOD AND APPARATUS FOR A DEPOSITED FILL LAYER
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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10745531
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Filing Dt:
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12/29/2003
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Publication #:
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Pub Dt:
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07/07/2005
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Title:
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MAGNETIC MEMORY HAVING SYNTHETIC ANTIFERROMAGNETIC PINNED LAYER
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Patent #:
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Issue Dt:
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11/17/2009
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Application #:
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10745611
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Filing Dt:
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12/29/2003
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Publication #:
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Pub Dt:
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07/07/2005
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Title:
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POWER SAVINGS WITH MULTIPLE READOUT CIRCUITS
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Patent #:
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Issue Dt:
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04/17/2007
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Application #:
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10745903
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Filing Dt:
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12/23/2003
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Publication #:
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Pub Dt:
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07/15/2004
| | | | |
Title:
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BUNDLE SKEW MANAGEMENT AND CELL SYNCHRONIZATION
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10746095
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Filing Dt:
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12/26/2003
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Title:
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COMPACT DECODE AND MULTIPLEXING CIRCUITRY FOR A MULTI-PORT MEMORY HAVING A COMMON MEMORY INTERFACE
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Patent #:
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Issue Dt:
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04/04/2006
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Application #:
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10746555
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Filing Dt:
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12/24/2003
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Publication #:
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Pub Dt:
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09/30/2004
| | | | |
Title:
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SEMICONDUCTOR MEMORY SYSTEM INCLUDING SELECTION TRANSISTORS
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Patent #:
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Issue Dt:
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10/24/2006
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Application #:
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10746878
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Filing Dt:
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12/23/2003
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Publication #:
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Pub Dt:
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10/14/2004
| | | | |
Title:
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METHOD FOR MANUFACTURING NON-VOLATILE MEMORY CELLS ON A SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
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04/17/2007
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Application #:
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10746975
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Filing Dt:
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12/24/2003
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Publication #:
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Pub Dt:
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07/07/2005
| | | | |
Title:
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SECURE BOOTING AND PROVISIONING
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Patent #:
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Issue Dt:
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06/14/2005
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Application #:
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10747586
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Filing Dt:
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12/29/2003
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Publication #:
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Pub Dt:
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07/22/2004
| | | | |
Title:
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SOI DEVICE WITH REDUCED DRAIN INDUCED BARRIER LOWERING
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Patent #:
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Issue Dt:
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01/30/2007
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Application #:
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10747625
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Filing Dt:
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12/30/2003
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Publication #:
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Pub Dt:
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07/07/2005
| | | | |
Title:
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PREDICTIVE FILTERING OF REGISTER CACHE ENTRY
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Patent #:
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Issue Dt:
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02/12/2008
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Application #:
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10747917
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Filing Dt:
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12/29/2003
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Publication #:
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Pub Dt:
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07/07/2005
| | | | |
Title:
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SYSTEM AND METHOD FOR READ SYNCHRONIZATION OF MEMORY MODULES
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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10748447
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Filing Dt:
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12/30/2003
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Publication #:
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Pub Dt:
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02/24/2005
| | | | |
Title:
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FAST PAGE PROGRAMMING ARCHITECTURE AND METHOD IN A NON-VOLATILE MEMORY DEVICE WITH AN SPI INTERFACE
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10748696
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Filing Dt:
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12/30/2003
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Publication #:
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Pub Dt:
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09/02/2004
| | | | |
Title:
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NON VOLATILE MEMORY DEVICE INCLUDING A PREDETERMINED NUMBER OF SECTORS
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Patent #:
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Issue Dt:
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05/24/2005
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Application #:
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10748697
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Filing Dt:
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12/30/2003
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Publication #:
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Pub Dt:
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10/14/2004
| | | | |
Title:
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VOLTAGE SUPPLY DISTRIBUTION ARCHITECTURE FOR A PLURALITY OF MEMORY MODULES
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10748701
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Filing Dt:
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12/30/2003
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Publication #:
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Pub Dt:
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10/28/2004
| | | | |
Title:
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STABILIZATION METHOD FOR DRAIN VOLTAGE IN NON-VOLATILE MULTI-LEVEL MEMORY CELLS AND RELATED MEMORY DEVICE
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Patent #:
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Issue Dt:
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04/11/2006
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Application #:
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10748732
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Filing Dt:
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12/29/2003
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Publication #:
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Pub Dt:
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07/07/2005
| | | | |
Title:
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ACCESS CIRCUIT AND METHOD FOR ALLOWING EXTERNAL TEST VOLTAGE TO BE APPLIED TO ISOLATED WELLS
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Patent #:
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Issue Dt:
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10/24/2006
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Application #:
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10749020
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Filing Dt:
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12/29/2003
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Publication #:
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Pub Dt:
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10/21/2004
| | | | |
Title:
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METHOD FOR MANUFACTURING NON-VOLATILE MEMORY CELLS ON A SEMICONDUCTIVE SUBSTRATE
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|
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Patent #:
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Issue Dt:
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06/07/2005
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Application #:
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10749659
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Filing Dt:
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12/30/2003
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Publication #:
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Pub Dt:
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08/05/2004
| | | | |
Title:
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SILICON-ON-INSULATOR COMPRISING INTEGRATED CIRCUITRY
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10750736
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Filing Dt:
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12/31/2003
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Publication #:
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Pub Dt:
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06/30/2005
| | | | |
Title:
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DIGITAL SWITCHING TECHNIQUE FOR DETECTING DATA
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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10750737
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Filing Dt:
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12/31/2003
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Publication #:
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Pub Dt:
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06/30/2005
| | | | |
Title:
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MEMORY CELL HAVING IMPROVED INTERCONNECT
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|
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Patent #:
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Issue Dt:
|
06/12/2007
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Application #:
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10751141
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Filing Dt:
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12/31/2003
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Publication #:
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Pub Dt:
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07/07/2005
| | | | |
Title:
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TRANSISTOR HAVING VERTICAL JUNCTION EDGE AND METHOD OF MANUFACTURING THE SAME
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|
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Patent #:
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Issue Dt:
|
01/13/2009
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Application #:
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10751441
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Filing Dt:
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01/06/2004
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Publication #:
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Pub Dt:
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07/14/2005
| | | | |
Title:
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DIE PACKAGE HAVING AN ADHESIVE FLOW RESTRICTION AREA
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|