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Issue Dt:
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10/22/2013
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Application #:
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13151898
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Filing Dt:
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06/02/2011
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Publication #:
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Pub Dt:
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12/06/2012
| | | | |
Title:
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INTEGRATED CIRCUIT HAVING ELECTROSTATIC DISCHARGE PROTECTION
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Patent #:
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08/13/2013
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13152350
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Filing Dt:
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06/03/2011
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Publication #:
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Pub Dt:
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09/22/2011
| | | | |
Title:
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DOPANT PROFILE TUNING FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION
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Patent #:
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Issue Dt:
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02/21/2012
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13153051
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Filing Dt:
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06/03/2011
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Publication #:
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Pub Dt:
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10/20/2011
| | | | |
Title:
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SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETS
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Patent #:
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Issue Dt:
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12/31/2013
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13153381
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Filing Dt:
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06/03/2011
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Publication #:
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Pub Dt:
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03/22/2012
| | | | |
Title:
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ANNEALING THIN FILMS
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Patent #:
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Issue Dt:
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07/01/2014
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Application #:
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13153806
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Filing Dt:
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06/06/2011
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Publication #:
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Pub Dt:
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09/29/2011
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Title:
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EMBEDDED DRAM INTEGRATED CIRCUITS WITH EXTREMELY THIN SILICON-ON-INSULATOR PASS TRANSISTORS
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Issue Dt:
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04/15/2014
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13154521
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Filing Dt:
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06/07/2011
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Pub Dt:
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12/13/2012
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Title:
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Method of Removing Gate Cap Materials While Protecting Active Area
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Patent #:
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Issue Dt:
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01/27/2015
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13154548
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Filing Dt:
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06/07/2011
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Publication #:
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Pub Dt:
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12/13/2012
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Title:
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BURIED SUBLEVEL METALLIZATIONS FOR IMPROVED TRANSISTOR DENSITY
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Patent #:
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Issue Dt:
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03/04/2014
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Application #:
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13154578
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Filing Dt:
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06/07/2011
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Pub Dt:
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12/13/2012
| | | | |
Title:
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Metal Gate Stack Formation for Replacement Gate Technology
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Patent #:
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Issue Dt:
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09/16/2014
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13154677
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Filing Dt:
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06/07/2011
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Publication #:
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Pub Dt:
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12/13/2012
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Title:
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HIGHLY SCALED ETSOI FLOATING BODY MEMORY AND MEMORY CIRCUIT
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Patent #:
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Issue Dt:
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05/13/2014
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Application #:
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13154754
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Filing Dt:
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06/07/2011
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Publication #:
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Pub Dt:
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02/02/2012
| | | | |
Title:
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REDUCED TOPOGRAPHY IN ISOLATION REGIONS OF A SEMICONDUCTOR DEVICE BY APPLYING A DEPOSITION/ETCH SEQUENCE PRIOR TO FORMING THE INTERLAYER DIELECTRIC
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Patent #:
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Issue Dt:
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07/29/2014
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13154905
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Filing Dt:
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06/07/2011
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Publication #:
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Pub Dt:
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12/13/2012
| | | | |
Title:
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METHOD OF FORMING A THROUGH-SILICON VIA UTILIZING A METAL CONTACT PAD IN A BACK-END-OF-LINE WIRING LEVEL TO FILL THE THROUGH-SILICON VIA
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09/17/2013
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13155878
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Filing Dt:
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06/08/2011
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Pub Dt:
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12/13/2012
| | | | |
Title:
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FORMATION OF EMBEDDED STRESSOR THROUGH ION IMPLANTATION
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Patent #:
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10/09/2012
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13156170
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Filing Dt:
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06/08/2011
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Publication #:
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Pub Dt:
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09/29/2011
| | | | |
Title:
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MOS STRUCTURES THAT EXHIBIT LOWER CONTACT RESISTANCE AND METHODS FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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04/24/2012
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13156736
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Filing Dt:
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06/09/2011
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Publication #:
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Pub Dt:
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09/29/2011
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Title:
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MICRO-FLUIDIC INJECTION MOLDED SOLDER (IMS)
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Patent #:
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Issue Dt:
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02/24/2015
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13156935
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Filing Dt:
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06/09/2011
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Publication #:
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Pub Dt:
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12/13/2012
| | | | |
Title:
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ON-CHIP SLOW-WAVE THROUGH-SILICON VIA COPLANAR WAVEGUIDE STRUCTURES, METHOD OF MANUFACTURE AND DESIGN STRUCTURE
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Patent #:
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03/19/2013
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13157909
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06/10/2011
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Publication #:
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Pub Dt:
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12/13/2012
| | | | |
Title:
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REDUCING THROUGH PROCESS DELAY VARIATION IN METAL WIRES
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Patent #:
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Issue Dt:
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07/08/2014
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13157968
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Filing Dt:
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06/10/2011
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Publication #:
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Pub Dt:
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12/13/2012
| | | | |
Title:
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TIMING RECOVERY METHOD AND APPARATUS FOR AN INPUT/OUTPUT BUS WITH LINK REDUNDANCY
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Issue Dt:
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01/28/2014
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13157980
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Filing Dt:
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06/10/2011
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Pub Dt:
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12/13/2012
| | | | |
Title:
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Rapid Estimation of Temperature Rise in Wires Due to Joule Heating
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Issue Dt:
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03/26/2013
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13158048
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Filing Dt:
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06/10/2011
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Publication #:
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Pub Dt:
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10/06/2011
| | | | |
Title:
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CHIP PACKAGE WITH CHANNEL STIFFENER FRAME
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Patent #:
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Issue Dt:
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10/08/2013
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13158079
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Filing Dt:
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06/10/2011
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Publication #:
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Pub Dt:
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12/13/2012
| | | | |
Title:
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PROGRAMMABLE DELAY GENERATOR AND CASCADED INTERPOLATOR
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Patent #:
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Issue Dt:
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03/04/2014
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13158114
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Filing Dt:
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06/10/2011
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Publication #:
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Pub Dt:
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12/13/2012
| | | | |
Title:
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COPPER INTERCONNECT WITH METAL HARDMASK REMOVAL
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Patent #:
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Issue Dt:
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09/10/2013
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Application #:
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13158419
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Filing Dt:
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06/12/2011
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Publication #:
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Pub Dt:
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12/13/2012
| | | | |
Title:
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COMPLEMENTARY BIPOLAR INVERTER
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Patent #:
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Issue Dt:
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09/03/2013
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Application #:
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13158420
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Filing Dt:
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06/12/2011
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Publication #:
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Pub Dt:
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12/13/2012
| | | | |
Title:
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COMPLEMENTARY SOI LATERAL BIPOLAR FOR SRAM IN A LOW-VOLTAGE CMOS PLATFORM
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Issue Dt:
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01/29/2013
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13158562
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Filing Dt:
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06/13/2011
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Pub Dt:
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12/13/2012
| | | | |
Title:
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SOLUTIONS FOR ON-CHIP MODELING OF OPEN TERMINATION OF FRINGE CAPACITANCE
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Patent #:
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Issue Dt:
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07/24/2012
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13158901
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Filing Dt:
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06/13/2011
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Publication #:
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Pub Dt:
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10/20/2011
| | | | |
Title:
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PHOTOLITHOGRAPHY FOCUS IMPROVEMENT BY REDUCTION OF AUTOFOCUS RADIATION TRANSMISSION INTO SUBSTRATE
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Patent #:
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Issue Dt:
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07/01/2014
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13159580
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Filing Dt:
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06/14/2011
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Pub Dt:
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06/14/2012
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Title:
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DYNAMIC FAULT DETECTION AND REPAIR IN A DATA COMMUNICATIONS MECHANISM
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Patent #:
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Issue Dt:
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01/01/2013
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Application #:
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13159594
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Filing Dt:
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06/14/2011
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Publication #:
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Pub Dt:
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10/06/2011
| | | | |
Title:
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PHASE CHANGE MEMORY DEVICE WITH PLATED PHASE CHANGE MATERIAL
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Patent #:
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Issue Dt:
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09/23/2014
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13159877
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Filing Dt:
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06/14/2011
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Publication #:
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Pub Dt:
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12/20/2012
| | | | |
Title:
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METHOD FOR FORMING TWO DEVICE WAFERS FROM A SINGLE BASE SUBSTRATE UTILIZING A CONTROLLED SPALLING PROCESS
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Issue Dt:
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04/29/2014
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13159893
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Filing Dt:
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06/14/2011
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Pub Dt:
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12/20/2012
| | | | |
Title:
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METHOD FOR CONTROLLED LAYER TRANSFER
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Issue Dt:
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01/06/2015
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13160067
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Filing Dt:
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06/14/2011
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Publication #:
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Pub Dt:
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12/20/2012
| | | | |
Title:
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SPALLING METHODS TO FORM MULTI-JUNCTION PHOTOVOLTAIC STRUCTURE
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Issue Dt:
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02/25/2014
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13160734
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Filing Dt:
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06/15/2011
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Pub Dt:
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12/20/2012
| | | | |
Title:
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MODEL-DRIVEN ASSIGNMENT OF WORK TO A SOFTWARE FACTORY
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Issue Dt:
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10/08/2013
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13161013
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Filing Dt:
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06/15/2011
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Pub Dt:
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12/20/2012
| | | | |
Title:
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DOUBLE GATE PLANAR FIELD EFFECT TRANSISTORS
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Issue Dt:
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01/14/2014
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13161163
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Filing Dt:
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06/15/2011
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Pub Dt:
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12/20/2012
| | | | |
Title:
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UNIFORMLY DISTRIBUTED SELF-ASSEMBLED CONE-SHAPED PILLARS FOR HIGH EFFICIENCY SOLAR CELLS
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Patent #:
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Issue Dt:
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05/26/2015
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13161260
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Filing Dt:
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06/15/2011
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Pub Dt:
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12/20/2012
| | | | |
Title:
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METHOD FOR CONTROLLED REMOVAL OF A SEMICONDUCTOR DEVICE LAYER FROM A BASE SUBSTRATE
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Issue Dt:
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05/21/2013
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13162712
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06/17/2011
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Pub Dt:
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12/20/2012
| | | | |
Title:
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NON-LITHOGRAPHIC METHOD OF PATTERNING CONTACTS FOR A PHOTOVOLTAIC DEVICE
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Issue Dt:
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07/08/2014
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13163495
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06/17/2011
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Pub Dt:
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12/20/2012
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Title:
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INTEGRATED CIRCUITS INCLUDING BARRIER POLISH STOP LAYERS AND METHODS FOR THE MANUFACTURE THEREOF
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Issue Dt:
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11/26/2013
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13163700
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06/19/2011
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Pub Dt:
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12/20/2012
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Title:
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BDD-BASED FUNCTIONAL MODELING
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Issue Dt:
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06/25/2013
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13164126
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Filing Dt:
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06/20/2011
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Pub Dt:
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12/20/2012
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Title:
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Methods to Fabricate Silicide Micromechanical Device
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Issue Dt:
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04/16/2013
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Application #:
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13164173
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Filing Dt:
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06/20/2011
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Pub Dt:
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10/06/2011
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Title:
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DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS
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Issue Dt:
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05/19/2015
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13164272
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Filing Dt:
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06/20/2011
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Pub Dt:
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12/20/2012
| | | | |
Title:
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Method of Forming Conductive Contacts on a Semiconductor Device with Embedded Memory and the Resulting Device
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Issue Dt:
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07/23/2013
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Application #:
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13164891
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Filing Dt:
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06/21/2011
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Pub Dt:
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12/27/2012
| | | | |
Title:
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FABRICATION OF SILICON OXIDE AND OXYNITRIDE HAVING SUB-NANOMETER THICKNESS
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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13164899
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Filing Dt:
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06/21/2011
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Pub Dt:
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02/02/2012
| | | | |
Title:
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METHOD OF CONTROLLING CRITICAL DIMENSIONS OF VIAS IN A METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE DURING SILICON-ARC ETCH
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Patent #:
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Issue Dt:
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03/04/2014
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13166842
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Filing Dt:
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06/23/2011
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Pub Dt:
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12/29/2011
| | | | |
Title:
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SOLAR MODULE WITH OVERHEAT PROTECTION
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Patent #:
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Issue Dt:
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12/23/2014
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13167076
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Filing Dt:
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06/23/2011
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Pub Dt:
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12/27/2012
| | | | |
Title:
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INTERDIGITATED VERTICAL NATIVE CAPACITOR
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