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Reel/Frame:	036550/0001			Pages:	983
		Recorded:	09/03/2015
Attorney Dkt #:	3718.266
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14793
Page 79 of 148
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Patent #:	8138102	Issue Dt:	03/20/2012	Application #:	12195524	Filing Dt:	08/21/2008
Publication #:	US20100044678	Pub Dt:	02/25/2010
Title:	METHOD OF PLACING A SEMICONDUCTING NANOSTRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTING NANOSTRUCTURE

Patent #:	8682128	Issue Dt:	03/25/2014	Application #:	12195565	Filing Dt:	08/21/2008
Publication #:	US20100046901	Pub Dt:	02/25/2010
Title:	OPTICAL WAVEGUIDE WITH PERIODIC SUB-WAVELENGTH SIZED REGIONS

Patent #:	8268729	Issue Dt:	09/18/2012	Application #:	12195691	Filing Dt:	08/21/2008
Publication #:	US20100048027	Pub Dt:	02/25/2010
Title:	SMOOTH AND VERTICAL SEMICONDUCTOR FIN STRUCTURE

Patent #:	8024699	Issue Dt:	09/20/2011	Application #:	12195716	Filing Dt:	08/21/2008
Publication #:	US20080313583	Pub Dt:	12/18/2008
Title:	TESTING SUB-SYSTEMS OF A SYSTEM-ON-A-CHIP USING A CONFIGURABLE EXTERNAL SYSTEM-ON-A-CHIP

Patent #:	7755420	Issue Dt:	07/13/2010	Application #:	12196718	Filing Dt:	08/22/2008
Publication #:	US20090051420	Pub Dt:	02/26/2009
Title:	INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES

Patent #:	NONE	Issue Dt:		Application #:	12196754	Filing Dt:	08/22/2008
Publication #:	US20080307379	Pub Dt:	12/11/2008
Title:	SYSTEM AND METHOD FOR INCREMENTAL STATISTICAL TIMING ANALYSIS OF DIGITAL CIRCUITS

Patent #:	8132133	Issue Dt:	03/06/2012	Application #:	12196840	Filing Dt:	08/22/2008
Publication #:	US20100050137	Pub Dt:	02/25/2010
Title:	AUTOMATED ISOLATION OF LOGIC AND MACRO BLOCKS IN CHIP DESIGN TESTING

Patent #:	7648864	Issue Dt:	01/19/2010	Application #:	12197079	Filing Dt:	08/22/2008
Publication #:	US20080308831	Pub Dt:	12/18/2008
Title:	SEMICONDUCTOR STRUCTURE INCLUDING MIXED RARE EARTH OXIDE FORMED ON SILICON

Patent #:	8337646	Issue Dt:	12/25/2012	Application #:	12197366	Filing Dt:	08/25/2008
Publication #:	US20090008020	Pub Dt:	01/08/2009
Title:	GREENSHEET VIA REPAIR/FILL TOOL

Patent #:	8241970	Issue Dt:	08/14/2012	Application #:	12197459	Filing Dt:	08/25/2008
Publication #:	US20100044758	Pub Dt:	02/25/2010
Title:	CMOS WITH CHANNEL P-FINFET AND CHANNEL N-FINFET HAVING DIFFERENT CRYSTALLINE ORIENTATIONS AND PARALLEL FINS

Patent #:	7724527	Issue Dt:	05/25/2010	Application #:	12197481	Filing Dt:	08/25/2008
Publication #:	US20080310117	Pub Dt:	12/18/2008
Title:	METHOD AND STRUCTURE TO IMPROVE THERMAL DISSIPATION FROM SEMICONDUCTOR DEVICES

Patent #:	7968270	Issue Dt:	06/28/2011	Application #:	12197571	Filing Dt:	08/25/2008
Publication #:	US20080311508	Pub Dt:	12/18/2008
Title:	PROCESS OF MAKING A SEMICONDUCTOR DEVICE USING MULTIPLE ANTIREFLECTIVE MATERIALS

Patent #:	7682591	Issue Dt:	03/23/2010	Application #:	12197688	Filing Dt:	08/25/2008
Publication #:	US20090053129	Pub Dt:	02/26/2009
Title:	EMBEDDED NANOPARTICLE FILMS AND METHOD FOR THEIR FORMATION IN SELECTIVE AREAS ON A SURFACE

Patent #:	7863083	Issue Dt:	01/04/2011	Application #:	12197845	Filing Dt:	08/25/2008
Publication #:	US20080311745	Pub Dt:	12/18/2008
Title:	HIGH TEMPERATURE PROCESSING COMPATIBLE METAL GATE ELECTRODE FOR PFETS AND METHODS FOR FABRICATION

Patent #:	8799837	Issue Dt:	08/05/2014	Application #:	12197980	Filing Dt:	08/25/2008
Publication #:	US20100050145	Pub Dt:	02/25/2010
Title:	OPTIMIZING A NETLIST CIRCUIT REPRESENTATION BY LEVERAGING BINARY DECISION DIAGRAMS TO PERFORM REWRITING

Patent #:	NONE	Issue Dt:		Application #:	12198196	Filing Dt:	08/26/2008
Publication #:	US20080308940	Pub Dt:	12/18/2008
Title:	STRUCTURE COUPLING AN ELECTRICALLY CONDUCTIVE LINE TO A SEMICONDUCTOR DEVICE THROUGH VIAS AND LINES

Patent #:	8303791	Issue Dt:	11/06/2012	Application #:	12198274	Filing Dt:	08/26/2008
Publication #:	US20090057154	Pub Dt:	03/05/2009
Title:	APPARATUS AND METHOD FOR ELECTROCHEMICAL PROCESSING OF THIN FILMS ON RESISTIVE SUBSTRATES

Patent #:	8169031	Issue Dt:	05/01/2012	Application #:	12198592	Filing Dt:	08/26/2008
Publication #:	US20100052018	Pub Dt:	03/04/2010
Title:	CONTINUOUS METAL SEMICONDUCTOR ALLOY VIA FOR INTERCONNECTS

Patent #:	7811926	Issue Dt:	10/12/2010	Application #:	12198602	Filing Dt:	08/26/2008
Publication #:	US20080311744	Pub Dt:	12/18/2008
Title:	MULTILAYER HARDMASK SCHEME FOR DAMAGE-FREE DUAL DAMASCENE PROCESSING OF SICOH DIELECTRICS

Patent #:	7678638	Issue Dt:	03/16/2010	Application #:	12198857	Filing Dt:	08/26/2008
Publication #:	US20080318374	Pub Dt:	12/25/2008
Title:	METAL GATED ULTRA SHORT MOSFET DEVICES

Patent #:	7709299	Issue Dt:	05/04/2010	Application #:	12198969	Filing Dt:	08/27/2008
Publication #:	US20080308941	Pub Dt:	12/18/2008
Title:	HIERARCHICAL 2T-DRAM WITH SELF-TIMED SENSING

Patent #:	7736949	Issue Dt:	06/15/2010	Application #:	12199063	Filing Dt:	08/27/2008
Publication #:	US20080318360	Pub Dt:	12/25/2008
Title:	DEVICE AND METHOD FOR FABRICATING DOUBLE-SIDED SOI WAFER SCALE PACKAGE WITH OPTICAL THROUGH VIA CONNECTIONS

Patent #:	8001493	Issue Dt:	08/16/2011	Application #:	12199161	Filing Dt:	08/27/2008
Publication #:	US20080319717	Pub Dt:	12/25/2008
Title:	EFFICIENT METHOD AND COMPUTER PROGRAM FOR MODELING AND IMPROVING STATIC MEMORY PERFORMANCE ACROSS PROCESS VARIATIONS AND ENVIRONMENTAL CONDITIONS

Patent #:	8293454	Issue Dt:	10/23/2012	Application #:	12199253	Filing Dt:	11/18/2008
Publication #:	US20090061355	Pub Dt:	03/05/2009
Title:	PROCESS OF MAKING A LITHOGRAPHIC STRUCTURE USING ANTIREFLECTIVE MATERIALS

Patent #:	7902061	Issue Dt:	03/08/2011	Application #:	12199407	Filing Dt:	08/27/2008
Publication #:	US20080318415	Pub Dt:	12/25/2008
Title:	INTERCONNECT STRUCTURES WITH ENCASING CAP AND METHODS OF MAKING THEREOF

Patent #:	7920434	Issue Dt:	04/05/2011	Application #:	12199438	Filing Dt:	08/27/2008
Publication #:	US20100054057	Pub Dt:	03/04/2010
Title:	MEMORY SENSING METHOD AND APPARATUS

Patent #:	7855133	Issue Dt:	12/21/2010	Application #:	12199516	Filing Dt:	08/27/2008
Publication #:	US20090087972	Pub Dt:	04/02/2009
Title:	FORMATION OF CARBON AND SEMICONDUCTOR NANOMATERIALS USING MOLECULAR ASSEMBLIES

Patent #:	8273886	Issue Dt:	09/25/2012	Application #:	12199607	Filing Dt:	08/27/2008
Publication #:	US20080318157	Pub Dt:	12/25/2008
Title:	RADIATION SENSITIVE SELF-ASSEMBLED MONOLAYERS AND USES THEREOF

Patent #:	8108193	Issue Dt:	01/31/2012	Application #:	12199920	Filing Dt:	08/28/2008
Publication #:	US20100057415	Pub Dt:	03/04/2010
Title:	COLLABORATION FRAMEWORK FOR MODELING

Patent #:	7764080	Issue Dt:	07/27/2010	Application #:	12200334	Filing Dt:	08/28/2008
Publication #:	US20080315907	Pub Dt:	12/25/2008
Title:	METHODS OF OPERATING AN ELECTRONIC CIRCUIT FOR MEASUREMENT OF TRANSISTOR VARIABILITY AND THE LIKE

Patent #:	8247271	Issue Dt:	08/21/2012	Application #:	12200352	Filing Dt:	08/28/2008
Publication #:	US20080318365	Pub Dt:	12/25/2008
Title:	FORMATION OF ALPHA PARTICLE SHIELDS IN CHIP PACKAGING

Patent #:	7989893	Issue Dt:	08/02/2011	Application #:	12200482	Filing Dt:	08/28/2008
Publication #:	US20100052053	Pub Dt:	03/04/2010
Title:	SOI BODY CONTACT USING E-DRAM TECHNOLOGY

Patent #:	7989865	Issue Dt:	08/02/2011	Application #:	12200538	Filing Dt:	08/28/2008
Publication #:	US20100052026	Pub Dt:	03/04/2010
Title:	DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY

Patent #:	7674705	Issue Dt:	03/09/2010	Application #:	12201266	Filing Dt:	08/29/2008
Publication #:	US20090008788	Pub Dt:	01/08/2009
Title:	METHOD OF FORMING A SEMICONDUCTOR DEVICE

Patent #:	8126045	Issue Dt:	02/28/2012	Application #:	12201487	Filing Dt:	08/29/2008
Publication #:	US20100054324	Pub Dt:	03/04/2010
Title:	SYSTEM AND METHOD FOR LATENCY REDUCTION IN SPECULATIVE DECISION FEEDBACK EQUALIZERS

Patent #:	8156458	Issue Dt:	04/10/2012	Application #:	12201685	Filing Dt:	08/29/2008
Publication #:	US20100058269	Pub Dt:	03/04/2010
Title:	UNIQUIFICATION AND PARENT-CHILD CONSTRUCTS FOR 1XN VLSI DESIGN

Patent #:	8001405	Issue Dt:	08/16/2011	Application #:	12201821	Filing Dt:	08/29/2008
Publication #:	US20100058084	Pub Dt:	03/04/2010
Title:	SELF-TUNING POWER MANAGEMENT TECHNIQUES

Patent #:	NONE	Issue Dt:		Application #:	12201828	Filing Dt:	08/29/2008
Publication #:	US20090077511	Pub Dt:	03/19/2009
Title:	Generating Constraints in a Class Model

Patent #:	NONE	Issue Dt:		Application #:	12202487	Filing Dt:	09/02/2008
Publication #:	US20080314754	Pub Dt:	12/25/2008
Title:	INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY NITRIDIZATION

Patent #:	8234604	Issue Dt:	07/31/2012	Application #:	12202500	Filing Dt:	09/02/2008
Publication #:	US20100058256	Pub Dt:	03/04/2010
Title:	CO-OPTIMIZATION OF EMBEDDED SYSTEMS UTILIZING SYMBOLIC EXECUTION

Patent #:	NONE	Issue Dt:		Application #:	12202511	Filing Dt:	09/02/2008
Publication #:	US20090011526	Pub Dt:	01/08/2009
Title:	INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY NITRIDIZATION

Patent #:	9059658	Issue Dt:	06/16/2015	Application #:	12202854	Filing Dt:	09/02/2008
Publication #:	US20100052584	Pub Dt:	03/04/2010
Title:	INCREASING TAPE VELOCITY BY DYNAMIC SWITCHING

Patent #:	NONE	Issue Dt:		Application #:	12203338	Filing Dt:	09/03/2008
Publication #:	US20100055442	Pub Dt:	03/04/2010
Title:	METHOD OF PE-ALD OF SiNxCy AND INTEGRATION OF LINER MATERIALS ON POROUS LOW K SUBSTRATES

Patent #:	8108811	Issue Dt:	01/31/2012	Application #:	12203955	Filing Dt:	09/04/2008
Publication #:	US20080320424	Pub Dt:	12/25/2008
Title:	VALIDATION OF ELECTRICAL PERFORMANCE OF AN ELECTRONIC PACKAGE PRIOR TO FABRICATION

Patent #:	8426316	Issue Dt:	04/23/2013	Application #:	12204412	Filing Dt:	09/04/2008
Publication #:	US20090001587	Pub Dt:	01/01/2009
Title:	Ta-TaN SELECTIVE REMOVAL PROCESS FOR INTEGRATED DEVICE FABRICATION

Patent #:	8392153	Issue Dt:	03/05/2013	Application #:	12204670	Filing Dt:	09/04/2008
Publication #:	US20090030864	Pub Dt:	01/29/2009
Title:	METHOD FOR CONSTRUCTING SEGMENTATION-BASED PREDICTIVE MODELS

Patent #:	9405870	Issue Dt:	08/02/2016	Application #:	12205476	Filing Dt:	09/05/2008
Publication #:	US20090070717	Pub Dt:	03/12/2009
Title:	GENERATING COVERAGE DATA FOR A SWITCH FREQUENCY OF HDL OR VHDL SIGNALS

Patent #:	7951525	Issue Dt:	05/31/2011	Application #:	12206065	Filing Dt:	09/08/2008
Publication #:	US20100062368	Pub Dt:	03/11/2010
Title:	LOW OUTGASSING PHOTORESIST COMPOSITIONS

Patent #:	7791403	Issue Dt:	09/07/2010	Application #:	12206124	Filing Dt:	09/08/2008
Publication #:	US20100060344	Pub Dt:	03/11/2010
Title:	TRANSITIONING DIGITAL INTEGRATED CIRCUIT FROM STANDBY MODE TO ACTIVE MODE VIA BACKGATE CHARGE TRANSFER

Patent #:	NONE	Issue Dt:		Application #:	12207498	Filing Dt:	09/10/2008
Publication #:	US20090013299	Pub Dt:	01/08/2009
Title:	BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS

Patent #:	8479388	Issue Dt:	07/09/2013	Application #:	12207713	Filing Dt:	09/10/2008
Publication #:	US20090007427	Pub Dt:	01/08/2009
Title:	METHOD OF PRODUCING A LAND GRID ARRAY INTERPOSER

Patent #:	8125618	Issue Dt:	02/28/2012	Application #:	12208358	Filing Dt:	09/11/2008
Publication #:	US20090040486	Pub Dt:	02/12/2009
Title:	REFLECTIVE FILM INTERFACE TO RESTORE TRANSVERSE MAGNETIC WAVE CONTRAST IN LITHOGRAPHIC PROCESSING

Patent #:	7979824	Issue Dt:	07/12/2011	Application #:	12208469	Filing Dt:	09/11/2008
Publication #:	US20100064270	Pub Dt:	03/11/2010
Title:	COST-BENEFIT OPTIMIZATION FOR AN AIRGAPPED INTEGRATED CIRCUIT

Patent #:	8176446	Issue Dt:	05/08/2012	Application #:	12208521	Filing Dt:	09/11/2008
Publication #:	US20100064273	Pub Dt:	03/11/2010
Title:	METHOD FOR COMPENSATING FOR VARIATIONS IN STRUCTURES OF AN INTEGRATED CIRCUIT

Patent #:	8108820	Issue Dt:	01/31/2012	Application #:	12208548	Filing Dt:	09/11/2008
Publication #:	US20100063781	Pub Dt:	03/11/2010
Title:	ENHANCED CONDUCTIVITY IN AN AIRGAPPED INTEGRATED CIRCUIT

Patent #:	8505200	Issue Dt:	08/13/2013	Application #:	12208581	Filing Dt:	09/11/2008
Publication #:	US20090119916	Pub Dt:	05/14/2009
Title:	LAND GRID ARRAY INTERPOSER PRODUCING METHOD

Patent #:	7912798	Issue Dt:	03/22/2011	Application #:	12209071	Filing Dt:	09/11/2008
Publication #:	US20090006049	Pub Dt:	01/01/2009
Title:	SYSTEM FOR ESTIMATING STORAGE REQUIREMENTS FOR A MULTI-DIMENSIONAL CLUSTERING DATA CONFIGURATION

Patent #:	8010921	Issue Dt:	08/30/2011	Application #:	12209461	Filing Dt:	09/12/2008
Publication #:	US20090013294	Pub Dt:	01/08/2009
Title:	SYSTEM AND METHOD FOR STATISTICAL TIMING ANALYSIS OF DIGITAL CIRCUITS

Patent #:	8417658	Issue Dt:	04/09/2013	Application #:	12210139	Filing Dt:	09/12/2008
Publication #:	US20100070449	Pub Dt:	03/18/2010
Title:	DEPLOYMENT PATTERN REALIZATION WITH MODELS OF COMPUTING ENVIRONMENTS

Patent #:	NONE	Issue Dt:		Application #:	12210683	Filing Dt:	09/15/2008
Publication #:	US20090011346	Pub Dt:	01/08/2009
Title:	FOCUS BLUR MEASUREMENT AND CONTROL METHOD

Patent #:	7585601	Issue Dt:	09/08/2009	Application #:	12210699	Filing Dt:	09/15/2008
Publication #:	US20090011342	Pub Dt:	01/08/2009
Title:	METHOD TO OPTIMIZE GRATING TEST PATTERN FOR LITHOGRAPHY MONITORING AND CONTROL

Patent #:	7666732	Issue Dt:	02/23/2010	Application #:	12210703	Filing Dt:	09/15/2008
Publication #:	US20090011552	Pub Dt:	01/08/2009
Title:	METHOD OF FABRICATING A METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS

Patent #:	7715222	Issue Dt:	05/11/2010	Application #:	12210712	Filing Dt:	09/15/2008
Publication #:	US20090010043	Pub Dt:	01/08/2009
Title:	CONFIGURABLE SRAM SYSTEM AND METHOD

Patent #:	8315409	Issue Dt:	11/20/2012	Application #:	12211435	Filing Dt:	09/16/2008
Publication #:	US20100067718	Pub Dt:	03/18/2010
Title:	MODIFICATIONS OF AUDIO COMMUNICATIONS IN AN ONLINE ENVIRONMENT

Patent #:	7745278	Issue Dt:	06/29/2010	Application #:	12211530	Filing Dt:	09/16/2008
Publication #:	US20090011610	Pub Dt:	01/08/2009
Title:	SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE TRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH K DIELECTRICS

Patent #:	7709902	Issue Dt:	05/04/2010	Application #:	12211647	Filing Dt:	09/16/2008
Publication #:	US20090008719	Pub Dt:	01/08/2009
Title:	METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS

Patent #:	8569844	Issue Dt:	10/29/2013	Application #:	12211649	Filing Dt:	09/16/2008
Publication #:	US20090008720	Pub Dt:	01/08/2009
Title:	METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS

Patent #:	7710059	Issue Dt:	05/04/2010	Application #:	12211840	Filing Dt:	09/17/2008
Publication #:	US20090015187	Pub Dt:	01/15/2009
Title:	METHOD OF OPTIMIZING SERVO CONTROLLER POWER IN TWO-DIMENSIONAL FLEXUTRE MEMS STORAGE DEVICES

Patent #:	7688058	Issue Dt:	03/30/2010	Application #:	12212247	Filing Dt:	09/17/2008
Publication #:	US20090015238	Pub Dt:	01/15/2009
Title:	INTEGRATED SPECTRUM ANALYZER CIRCUITS AND METHODS FOR PROVIDING ON-CHIP DIAGNOSTICS

Patent #:	7673173	Issue Dt:	03/02/2010	Application #:	12212577	Filing Dt:	09/17/2008
Publication #:	US20090013099	Pub Dt:	01/08/2009
Title:	SYSTEM AND PROGRAM FOR TRANSMITTING INPUT/OUTPUT REQUESTS FROM A FIRST CONTROLLER TO A SECOND CONTROLLER

Patent #:	7888603	Issue Dt:	02/15/2011	Application #:	12212925	Filing Dt:	09/18/2008
Publication #:	US20090008129	Pub Dt:	01/08/2009
Title:	COOLING OF SUBSTRATE USING INTERPOSER CHANNELS

Patent #:	8316540	Issue Dt:	11/27/2012	Application #:	12212927	Filing Dt:	09/18/2008
Publication #:	US20090013528	Pub Dt:	01/15/2009
Title:	METHOD OF PRODUCING A LAND GRID ARRAY (LGA) INTERPOSER STRUCTURE

Patent #:	7856711	Issue Dt:	12/28/2010	Application #:	12212998	Filing Dt:	09/18/2008
Publication #:	US20090011546	Pub Dt:	01/08/2009
Title:	METHOD OF FORMING A SUBSTRATE WITH INTERPOSER CHANNELS FOR COOLING THE SUBSTRATE

Patent #:	7660350	Issue Dt:	02/09/2010	Application #:	12218272	Filing Dt:	07/14/2008
Publication #:	US20080298520	Pub Dt:	12/04/2008
Title:	HIGH-SPEED MULTI-MODE RECEIVER

Patent #:	7761825	Issue Dt:	07/20/2010	Application #:	12220497	Filing Dt:	07/24/2008
Publication #:	US20080288903	Pub Dt:	11/20/2008
Title:	GENERATING TESTCASES BASED ON NUMBERS OF TESTCASES PREVIOUSLY GENERATED

Patent #:	7615457	Issue Dt:	11/10/2009	Application #:	12220521	Filing Dt:	07/25/2008
Publication #:	US20080318373	Pub Dt:	12/25/2008
Title:	METHOD OF FABRICATING SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPERED COLLECTOR

Patent #:	7837459	Issue Dt:	11/23/2010	Application #:	12221966	Filing Dt:	08/07/2008
Publication #:	US20080305197	Pub Dt:	12/11/2008
Title:	METHOD FOR FABRICATING DUAL DAMASCENE STRUCTURES USING PHOTO-IMPRINT LITHOGRAPHY, METHODS FOR FABRICATING IMPRINT LITHOGRAPHY MOLDS FOR DUAL DAMASCENE STRUCTURES, MATERIALS FOR IMPRINTABLE DIELECTRICS AND EQUIPMENT FOR PHOTO-IMPRINT LITHOGRAPHY USED IN DUAL DAMASCE

Patent #:	7982312	Issue Dt:	07/19/2011	Application #:	12222000	Filing Dt:	08/07/2008
Publication #:	US20080303160	Pub Dt:	12/11/2008
Title:	METHOD FOR FABRICATING DUAL DAMASCENE STRUCTURES USING PHOTO-IMPRINT LITHOGRAPHY, METHODS FOR FABRICATING IMPRINT LITHOGRAPHY MOLDS FOR DUAL DAMASCENE STRUCTURES, MATERIALS FOR IMPRINTABLE DIELECTRICS AND EQUIPMENT FOR PHOTO-IMPRINT LITHOGRAPHY USED IN DUAL DAMASCE

Patent #:	7862989	Issue Dt:	01/04/2011	Application #:	12228010	Filing Dt:	08/07/2008
Publication #:	US20090023083	Pub Dt:	01/22/2009
Title:	METHOD FOR FABRICATING DUAL DAMASCENE STRUCTURES USING PHOTO-IMPRINT LITHOGRAPHY, METHODS FOR FABRICATING IMPRINT LITHOGRAPHY MOLDS FOR DUAL DAMASCENE STRUCTURES, MATERIALS FOR IMPRINTABLE DIELECTRICS AND EQUIPMENT FOR PHOTO-IMPRINT LITHOGRAPHY USED IN DUAL DAMASCE

Patent #:	8140314	Issue Dt:	03/20/2012	Application #:	12228587	Filing Dt:	08/14/2008
Publication #:	US20080312896	Pub Dt:	12/18/2008
Title:	OPTIMAL BUS OPERATION PERFORMANCE IN A LOGIC SIMULATION ENVIRONMENT

Patent #:	8110746	Issue Dt:	02/07/2012	Application #:	12233061	Filing Dt:	09/18/2008
Publication #:	US20090008130	Pub Dt:	01/08/2009
Title:	COOLING OF SUBSTRATE USING INTERPOSER CHANNELS

Patent #:	8059400	Issue Dt:	11/15/2011	Application #:	12233104	Filing Dt:	09/18/2008
Publication #:	US20090011547	Pub Dt:	01/08/2009
Title:	COOLING OF SUBSTRATE USING INTERPOSER CHANNELS

Patent #:	8056037	Issue Dt:	11/08/2011	Application #:	12233169	Filing Dt:	09/18/2008
Publication #:	US20090083684	Pub Dt:	03/26/2009
Title:	METHOD FOR VIOLATING THE LOGICAL FUNCTION AND TIMING BEHAVIOR OF A DIGITAL CIRCUIT DECISION

Patent #:	7736841	Issue Dt:	06/15/2010	Application #:	12233245	Filing Dt:	09/18/2008
Publication #:	US20090011371	Pub Dt:	01/08/2009
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100

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Title:	DISLOCATION ENGINEERING USING A SCANNED LASER

Assignor

INTERNATIONAL BUSINESS MACHINES CORPORATION

Exec Dt:

06/29/2015

Assignee

GLOBALFOUNDRIES U.S. 2 LLC

2070 ROUTE 52

HOPEWELL JUNCTION, NEW YORK 12533

Correspondence name and address
	HESLIN ROTHENBERG FARLEY & MESITI P.C.
	5 COLUMBIA CIRCLE
	ALBANY, NY 12203

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