|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
10875453
|
Filing Dt:
|
06/24/2004
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
Title:
|
FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
10875534
|
Filing Dt:
|
06/24/2004
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
Title:
|
PERMEABLE CAPACITOR ELECTRODE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10876184
|
Filing Dt:
|
06/24/2004
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
Title:
|
METHODS FOR ERASING FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10876333
|
Filing Dt:
|
06/24/2004
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
Title:
|
METHOD OF FORMING ISOLATION FILM IN SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2005
|
Application #:
|
10876664
|
Filing Dt:
|
06/28/2004
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
Title:
|
CHALCOGENIDE GLASS CONSTANT CURRENT DEVICE, AND ITS METHOD OF FABRICATION AND OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10876703
|
Filing Dt:
|
06/28/2004
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
Title:
|
CHEMICAL VAPOR DEPOSITION METHODS OF FORMING BARIUM STRONTIUM TITANATE COMPRISING DIELECTRIC LAYERS, INCLUDING SUCH LAYERS HAVING A VARIED CONCENTRATION OF BARIUM AND STRONTIUM WITHIN THE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
10876878
|
Filing Dt:
|
06/25/2004
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
HANDLING DEFECTIVE MEMORY BLOCKS OF NAND MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
10877394
|
Filing Dt:
|
06/25/2004
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
CHARGE PUMP CIRCUITRY HAVING ADJUSTABLE CURRENT OUTPUTS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10877576
|
Filing Dt:
|
06/25/2004
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
Title:
|
SYNCHRONOUS FLASH MEMORY COMMAND SEQUENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10877634
|
Filing Dt:
|
06/25/2004
|
Publication #:
|
|
Pub Dt:
|
11/18/2004
| | | | |
Title:
|
METHOD, APPARATUS, AND SYSTEM TO ENHANCE NEGATIVE VOLTAGE SWITCHING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2008
|
Application #:
|
10877720
|
Filing Dt:
|
06/25/2004
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
LOW POWER COST-EFFECTIVE ECC MEMORY SYSTEM AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10878056
|
Filing Dt:
|
06/29/2004
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
Title:
|
CURRENT SWITCHING SENSOR DETECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10878273
|
Filing Dt:
|
06/28/2004
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
HIGH VOLTAGE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
10878569
|
Filing Dt:
|
06/29/2004
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
Title:
|
FORMING OXIDE BUFFER LAYER FOR IMPROVED MAGNETIC TUNNEL JUNCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
10878799
|
Filing Dt:
|
06/28/2004
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
FORMATION OF MEMORY CELLS AND SELECT GATES OF NAND MEMORY ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
10878805
|
Filing Dt:
|
06/28/2004
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
ISOLATION TRENCHES FOR MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2011
|
Application #:
|
10879170
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
01/19/2006
| | | | |
Title:
|
SHIELDING BLACK REFERENCE PIXELS IN IMAGE SENSORS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10879366
|
Filing Dt:
|
06/28/2004
|
Title:
|
METHODS OF FORMING CONDUCTIVE INERCONNECTS, AND METHODS OF DEPOSITING NICKEL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10879367
|
Filing Dt:
|
06/28/2004
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
METHODS OF FORMING PATTERNED PHOTORESIST LAYERS OVER SEMICONDUCTOR SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10879372
|
Filing Dt:
|
06/28/2004
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10879434
|
Filing Dt:
|
06/29/2004
|
Publication #:
|
|
Pub Dt:
|
04/07/2005
| | | | |
Title:
|
CIRCUIT OF REDUNDANCY IO FUSE IN SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
10879848
|
Filing Dt:
|
06/29/2004
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
Title:
|
HIGH VOLTAGE SWITCH CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
10880646
|
Filing Dt:
|
07/01/2004
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
TRANSPARENT CONDUCTOR BASED PINNED PHOTODIODE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
10880692
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
PROVIDING CURRENT FOR PHASE CHANGE MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10880886
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
ION-ASSISTED OXIDATION METHODS AND THE RESULTING STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
10880988
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
INTERCONNECT STRUCTURE IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10881002
|
Filing Dt:
|
07/01/2004
|
Publication #:
|
|
Pub Dt:
|
01/06/2005
| | | | |
Title:
|
CAPACITOR LAYOUT TECHNIQUE FOR REDUCTION OF FIXED PATTERN NOISE IN A CMOS SENSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10881042
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
FLASH MEMORY CELLS WITH REDUCED DISTANCES BETWEEN CELL ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
10881630
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
Title:
|
CONDUCTOR LAYER NITRIDATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
10881636
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
REDUCTION OF ADJACENT FLOATING GATE DATA PATTERN SENSITIVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
10881662
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
FLASH MEMORY WITH METAL-INSULATOR-METAL TUNNELING PROGRAM AND ERASE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
10881664
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
INITIALIZING PHASE CHANGE MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
10881874
|
Filing Dt:
|
06/29/2004
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
SEMICONDUCTOR CONSTRUCTIONS COMPRISING CERIUM OXIDE AND TITANIUM OXIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2006
|
Application #:
|
10882563
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
Transistor structures and transistors with a germanium-containing channel
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10882969
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
Title:
|
EDGE INTENSIVE ANTIFUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2007
|
Application #:
|
10882987
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
Title:
|
EDGE INTENSIVE ANTIFUSE AND METHOD FOR MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2009
|
Application #:
|
10883191
|
Filing Dt:
|
07/01/2004
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
LOW TEMPERATURE PROCESS FOR POLYSILAZANE OXIDATION/DENSIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
10883215
|
Filing Dt:
|
07/01/2004
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
METHOD FOR FORMING CONTROLLED GEOMETRY HARDMASKS INCLUDING SUBRESOLUTION ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10883279
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
Title:
|
METHOD FOR MANUFACTURING FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
10883522
|
Filing Dt:
|
07/01/2004
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
Title:
|
SEMICONDUCTOR DAMASCENE TRENCH AND METHODS THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
10883601
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
01/06/2005
| | | | |
Title:
|
EDGE INTENSIVE ANTIFUSE AND METHOD FOR MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10884044
|
Filing Dt:
|
07/02/2004
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
METHODS OF FORMING LAYERS OVER SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
10884481
|
Filing Dt:
|
07/02/2004
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
Title:
|
INTEGRATED CIRCUIT DEVICE, AND METHOD OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
10885650
|
Filing Dt:
|
07/08/2004
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
DEUTERATED STRUCTURES FOR IMAGE SENSORS AND METHODS FOR FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2010
|
Application #:
|
10885821
|
Filing Dt:
|
07/07/2004
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
PRIORITIZATION OF NETWORK TRAFFIC
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10885933
|
Filing Dt:
|
07/06/2004
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
SEMICONDUCTOR CONSTRUCTIONS AND ELECTRONIC SYSTEMS COMPRISING METAL SILICIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
10886003
|
Filing Dt:
|
07/07/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
METHOD OF GENERATING AN ENABLE SIGNAL OF A STANDARD MEMORY CORE AND RELATIVE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
10886063
|
Filing Dt:
|
07/06/2004
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
Title:
|
METHOD AND SYSTEM FOR DYNAMICALLY OPERATING MEMORY IN A POWER-SAVING ERROR CORRECTING MODE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
10886078
|
Filing Dt:
|
07/07/2004
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
USE OF SELECTIVE EPITAXIAL SILICON GROWTH IN FORMATION OF FLOATING GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
10886676
|
Filing Dt:
|
07/09/2004
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
Title:
|
METHOD OF MANUFACTURE OF A PCRAM MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10886771
|
Filing Dt:
|
07/07/2004
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
POWER SUPPLY VOLTAGE DETECTION CIRCUITRY AND METHODS FOR USE OF THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
10886958
|
Filing Dt:
|
07/07/2004
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
Title:
|
MAGNETIC MEMORY CELL WITH SHAPE ANISOTROPY AND MEMORY DEVICE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
10887049
|
Filing Dt:
|
07/08/2004
|
Publication #:
|
|
Pub Dt:
|
12/09/2004
| | | | |
Title:
|
MODIFIED FACET ETCH TO PREVENT BLOWN GATE OXIDE AND INCREASE ETCH CHAMBER LIFE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10887255
|
Filing Dt:
|
07/07/2004
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
Title:
|
SEMICONDUCTOR COMPONENTS HAVING MULTIPLE ON BOARD CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10887616
|
Filing Dt:
|
07/09/2004
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
MEMORY ARRAY DECODER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2010
|
Application #:
|
10887880
|
Filing Dt:
|
07/12/2004
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
DUAL PANEL PIXEL READOUT IN AN IMAGER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10887962
|
Filing Dt:
|
07/08/2004
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
METHODS OF FORMING METAL NITRIDE, AND METHODS OF FORMING CAPACITOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10888255
|
Filing Dt:
|
07/09/2004
|
Publication #:
|
|
Pub Dt:
|
12/09/2004
| | | | |
Title:
|
ETCHANT AND METHOD OF USE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2009
|
Application #:
|
10889084
|
Filing Dt:
|
07/12/2004
|
Publication #:
|
|
Pub Dt:
|
12/16/2004
| | | | |
Title:
|
COMPOSITIONS FOR DISSOLUTION OF LOW-K DIELECTRIC FILMS, AND METHODS OF USE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
10889201
|
Filing Dt:
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07/12/2004
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Publication #:
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Pub Dt:
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12/02/2004
| | | | |
Title:
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COMPOSITIONS FOR DISSOLUTION OF LOW-K DIELECTRIC FILMS, AND METHODS OF USE
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Patent #:
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Issue Dt:
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10/07/2008
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Application #:
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10889280
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Filing Dt:
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07/12/2004
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Publication #:
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Pub Dt:
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12/09/2004
| | | | |
Title:
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COMPOSITIONS FOR DISSOLUTION OF LOW-K DIELECTRIC FILM, AND METHODS OF USE
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Patent #:
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Issue Dt:
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03/27/2012
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Application #:
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10889597
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Filing Dt:
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07/12/2004
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Publication #:
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Pub Dt:
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12/16/2004
| | | | |
Title:
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COMPOSITIONS FOR DISSOLUTION OF LOW-K DIELECTRIC FILMS, AND METHODS OF USE
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10889803
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Filing Dt:
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07/13/2004
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Publication #:
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Pub Dt:
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12/02/2004
| | | | |
Title:
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ABERRATION MARK AND METHOD FOR ESTIMATING OVERLAY ERROR AND OPTICAL ABERRATIONS
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Patent #:
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Issue Dt:
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10/26/2010
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Application #:
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10890529
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Filing Dt:
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07/12/2004
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Publication #:
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Pub Dt:
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02/24/2005
| | | | |
Title:
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METHOD FOR MANUFACTURING DIFFERENTIAL ISOLATION STRUCTURES IN A SEMICONDUCTOR ELECTRONIC DEVICE AND CORRESPONDING STRUCTURE
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|
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Patent #:
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Issue Dt:
|
09/18/2007
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Application #:
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10891535
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Filing Dt:
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07/15/2004
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Publication #:
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Pub Dt:
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01/19/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR REDUCING DUTY CYCLE DISTORTION OF AN OUTPUT SIGNAL
|
|
|
Patent #:
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|
Issue Dt:
|
09/26/2006
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Application #:
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10891792
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Filing Dt:
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07/15/2004
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Publication #:
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Pub Dt:
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12/09/2004
| | | | |
Title:
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DIE STACKING SCHEME
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Patent #:
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Issue Dt:
|
08/02/2005
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Application #:
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10892048
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Filing Dt:
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07/15/2004
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Publication #:
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Pub Dt:
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12/16/2004
| | | | |
Title:
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METHOD AND APPARATUS FOR DETECTING TOPOGRAPHICAL FEATURES OF MICROELECTRONIC SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
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Application #:
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10892318
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Filing Dt:
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07/16/2004
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Publication #:
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Pub Dt:
|
01/19/2006
| | | | |
Title:
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EXPOSURE CONTROL FOR IMAGE SENSORS
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|
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Patent #:
|
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Issue Dt:
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02/13/2007
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Application #:
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10892340
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Filing Dt:
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07/14/2004
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Publication #:
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Pub Dt:
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12/30/2004
| | | | |
Title:
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METHODS OF FORMING MEMORY CELLS HAVING DIODES AND ELECTRODE PLATES CONNECTED TO SOURCE/DRAIN REGIONS
|
|
|
Patent #:
|
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Issue Dt:
|
10/03/2006
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Application #:
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10892651
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Filing Dt:
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07/16/2004
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Publication #:
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Pub Dt:
|
01/19/2006
| | | | |
Title:
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METHODS OF GROWING EPITAXIAL SILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
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Application #:
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10892773
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Filing Dt:
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07/15/2004
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Publication #:
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Pub Dt:
|
01/19/2006
| | | | |
Title:
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METHOD AND SYSTEM FOR CONTROLLING REFRESH TO AVOID MEMORY CELL DATA LOSSES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
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Application #:
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10892805
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Filing Dt:
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07/16/2004
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Publication #:
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Pub Dt:
|
01/19/2006
| | | | |
Title:
|
MEASURE-CONTROLLED DELAY CIRCUITS WITH REDUCED PHASE ERROR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2009
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Application #:
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10892875
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Filing Dt:
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07/16/2004
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Publication #:
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Pub Dt:
|
01/19/2006
| | | | |
Title:
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METHOD AND SYSTEM FOR REDUCING MISMATCH BETWEEN REFERENCE AND INTENSITY PATHS IN ANALOG TO DIGITAL CONVERTERS IN CMOS ACTIVE PIXEL SENSORS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
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Application #:
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10893015
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Filing Dt:
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07/16/2004
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Publication #:
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Pub Dt:
|
01/19/2006
| | | | |
Title:
|
METHOD, SYSTEM, AND APPARATUS FOR TRACKING DEFECTIVE CACHE LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
10893276
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Filing Dt:
|
07/19/2004
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Publication #:
|
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Pub Dt:
|
01/19/2006
| | | | |
Title:
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PIXEL CELL HAVING A GRATED INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
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Application #:
|
10893293
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Filing Dt:
|
07/19/2004
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Publication #:
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Pub Dt:
|
01/19/2006
| | | | |
Title:
|
CMOS FRONT END PROCESS COMPATIBLE LOW STRESS LIGHT SHIELD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2007
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Application #:
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10893299
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Filing Dt:
|
07/19/2004
|
Publication #:
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|
Pub Dt:
|
01/19/2006
| | | | |
Title:
|
RESISTANCE VARIABLE MEMORY DEVICE AND METHOD OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
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Application #:
|
10893685
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Filing Dt:
|
07/16/2004
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Publication #:
|
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Pub Dt:
|
12/30/2004
| | | | |
Title:
|
APPARATUS FOR DEFORMING RESILIENT CONTACT STRUCTURES ON SEMICONDUCTOR COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
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Application #:
|
10893709
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Filing Dt:
|
07/15/2004
|
Publication #:
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Pub Dt:
|
12/23/2004
| | | | |
Title:
|
WAVELENGTH DIVISION MULTIPLEXED MEMORY MODULE, MEMORY SYSTEM AND METHOD
|
|
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Patent #:
|
|
Issue Dt:
|
12/26/2006
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Application #:
|
10893760
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Filing Dt:
|
07/16/2004
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Publication #:
|
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Pub Dt:
|
03/03/2005
| | | | |
Title:
|
REDUNDANCY SCHEME FOR A MEMORY INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10893804
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Filing Dt:
|
07/19/2004
|
Publication #:
|
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Pub Dt:
|
02/02/2006
| | | | |
Title:
|
DELAY STAGE-INTERWEAVED ANALOG DLL/PLL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2007
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Application #:
|
10894101
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Filing Dt:
|
07/19/2004
|
Publication #:
|
|
Pub Dt:
|
01/19/2006
| | | | |
Title:
|
IN-SERVICE RECONFIGURABLE DRAM AND FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
10894125
|
Filing Dt:
|
07/20/2004
|
Publication #:
|
|
Pub Dt:
|
01/26/2006
| | | | |
Title:
|
DRAM LAYOUT WITH VERTICAL FETS AND METHOD OF FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
10894242
|
Filing Dt:
|
07/19/2004
|
Publication #:
|
|
Pub Dt:
|
01/19/2006
| | | | |
Title:
|
MEMORY DEVICE TRIMS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10894292
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Filing Dt:
|
07/19/2004
|
Publication #:
|
|
Pub Dt:
|
12/23/2004
| | | | |
Title:
|
ETCH STOP LAYER IN POLY-METAL STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10894782
|
Filing Dt:
|
07/19/2004
|
Publication #:
|
|
Pub Dt:
|
01/19/2006
| | | | |
Title:
|
METHODS OF ETCHING AN ALUMINUM OXIDE COMPRISING SUBSTRATE, AND METHODS OF FORMING A CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10895130
|
Filing Dt:
|
07/21/2004
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
METHOD OF FORMING A DUAL-SIDED CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10895502
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Filing Dt:
|
07/20/2004
|
Publication #:
|
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Pub Dt:
|
12/30/2004
| | | | |
Title:
|
ETCHING METHODS AND APPARATUS AND SUBSTRATE ASSEMBLIES PRODUCED THEREWITH
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10895649
|
Filing Dt:
|
07/20/2004
|
Publication #:
|
|
Pub Dt:
|
01/26/2006
| | | | |
Title:
|
DELAY-LOCKED LOOP WITH FEEDBACK COMPENSATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10896139
|
Filing Dt:
|
07/20/2004
|
Publication #:
|
|
Pub Dt:
|
01/26/2006
| | | | |
Title:
|
TEMPERATURE-COMPENSATED OUTPUT BUFFER METHOD AND CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
10896711
|
Filing Dt:
|
07/22/2004
|
Publication #:
|
|
Pub Dt:
|
01/06/2005
| | | | |
Title:
|
LOW DOSE SUPER DEEP SOURCE/DRAIN IMPLANT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
10897165
|
Filing Dt:
|
07/22/2004
|
Publication #:
|
|
Pub Dt:
|
12/23/2004
| | | | |
Title:
|
USE OF A DUAL-TONE RESIST TO FORM PHOTOMASKS INCLUDING ALIGNMENT MARK PROTECTION, INTERMEDIATE SEMICONDUCTOR DEVICE STRUCTURES AND BULK SEMICONDUCTOR DEVICE SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2006
|
Application #:
|
10897166
|
Filing Dt:
|
07/22/2004
|
Publication #:
|
|
Pub Dt:
|
01/26/2006
| | | | |
Title:
|
METHOD AND APPARATUS TO SET A TUNING RANGE FOR AN ANALOG DELAY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
10898762
|
Filing Dt:
|
07/26/2004
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
APPARATUS FOR LATENCY SPECIFIC DUTY CYCLE CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
10898765
|
Filing Dt:
|
07/26/2004
|
Publication #:
|
|
Pub Dt:
|
12/23/2004
| | | | |
Title:
|
METHODS OF WRITING JUNCTION-ISOLATED DEPLETION MODE FERROELECTRIC MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
10898867
|
Filing Dt:
|
07/26/2004
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
Title:
|
METHODS OF READING JUNCTION-ISOLATED DEPLETION MODE FERROELECTRIC MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
10899010
|
Filing Dt:
|
07/27/2004
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
Title:
|
AMORPHOUS CARBON-BASED NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2009
|
Application #:
|
10899011
|
Filing Dt:
|
07/27/2004
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
Title:
|
SYSTEM INCLUDING INTEGRATED CIRCUIT STRUCTURES FORMED IN A SILICONE LADDER POLYMER LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
10899736
|
Filing Dt:
|
07/27/2004
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
Title:
|
SMALL GRAIN SIZE, CONFORMAL ALUMINUM INTERCONNECTS AND METHOD FOR THEIR FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10899892
|
Filing Dt:
|
07/27/2004
|
Publication #:
|
|
Pub Dt:
|
01/06/2005
| | | | |
Title:
|
MEMORY DEVICE WITH NON-VOLATILE REFERENCE MEMORY CELL TRIMMING CAPABILITIES
|
|