|
|
Patent #:
|
|
Issue Dt:
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10/17/2006
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Application #:
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10929823
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Filing Dt:
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08/30/2004
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Publication #:
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Pub Dt:
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02/10/2005
| | | | |
Title:
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SYSTEMS AND METHODS OF FORMING REFRACTORY METAL NITRIDE LAYERS USING DISILAZANES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
10929827
|
Filing Dt:
|
08/30/2004
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Publication #:
|
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Pub Dt:
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02/10/2005
| | | | |
Title:
|
SYSTEMS AND METHODS OF FORMING REFRACTORY METAL NITRIDE LAYERS USING DISILAZANES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
10929853
|
Filing Dt:
|
08/30/2004
|
Publication #:
|
|
Pub Dt:
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02/03/2005
| | | | |
Title:
|
ACTIVATION OF OXIDES FOR ELECTROLESS PLATING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
10929898
|
Filing Dt:
|
08/30/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
ISOLATION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
10929904
|
Filing Dt:
|
08/30/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
RESISTIVE HEATER FOR THERMO OPTIC DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10929916
|
Filing Dt:
|
08/30/2004
|
Publication #:
|
|
Pub Dt:
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02/03/2005
| | | | |
Title:
|
PROGRAMMABLE ARRAY LOGIC OR MEMORY WITH P-CHANNEL DEVICES AND ASYMMETRICAL TUNNEL BARRIERS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
10929986
|
Filing Dt:
|
08/30/2004
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Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
ATOMIC LAYER DEPOSITION OF METAL OXIDE AND/OR LOW ASYMMETRICAL TUNNEL BARRIER INTERPOLY INSULATORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
10930001
|
Filing Dt:
|
08/30/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
LOCALIZED BIASING FOR SILICON ON INSULATOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
10930087
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
Title:
|
DEFECTIVE MEMORY BLOCK IDENTIFICATION IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2005
|
Application #:
|
10930138
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
EVAPORATION OF Y-SI-O FILMS FOR MEDIUM-K DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2012
|
Application #:
|
10930149
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
METHOD OF INCREASING DEPOSITION RATE OF SILICON DIOXIDE ON A CATALYST
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2007
|
Application #:
|
10930153
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
ACCESSING TEST MODES USING COMMAND SEQUENCES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2009
|
Application #:
|
10930158
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
CAPACITIVE TECHNIQUES TO REDUCE NOISE IN HIGH SPEED INTERCONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2009
|
Application #:
|
10930167
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
METHODS FOR FORMING A LANTHANUM-METAL OXIDE DIELECTRIC LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10930184
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
CRYSTALLINE OR AMORPHOUS MEDIUM-K GATE OXIDES, Y2O3 AND GD2O3
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10930211
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
SEMICONDUCTOR SUBSTRATE CLEANING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
10930213
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
METHOD AND APPARATUS ON (110) SURFACES OF SILICON STRUCTURES WITH CONDUCTION IN THE <110> DIRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
10930251
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
PRINT STRIPPER FOR ESD CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
10930252
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
INTEGRATED CIRCUIT COOLING AND INSULATING DEVICE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
10930288
|
Filing Dt:
|
08/30/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
SYSTEM AND METHOD FOR A SINGLE-PASS MULTIPLE TAP FILTER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
10930422
|
Filing Dt:
|
08/30/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
STRUCTURE AND METHOD FOR TRANSVERSE FIELD ENHANCEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2009
|
Application #:
|
10930431
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
HfAlO3 FILMS FOR GATE DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10930440
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
ONE TRANSISTOR SOI NON-VOLATILE RANDOM ACCESS MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10930442
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
NICKEL BONDING CAP OVER COPPER METALIZED BONDPADS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
10930444
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
LATENCY REDUCTION USING NEGATIVE CLOCK EDGE AND READ FLAGS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
10930510
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
ASYMMETRIC PLATING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
10930511
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
CURRENT LIMITING ANTIFUSE PROGRAMMING PATH
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
10930512
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
BULK-ISOLATED PN DIODE AND METHOD OF FORMING A BULK-ISOLATED PN DIODE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10930513
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
Title:
|
DELAY LOCKED LOOP "ACTIVE COMMAND" REACTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
10930514
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
WRITE ONCE READ ONLY MEMORY EMPLOYING CHARGE TRAPPING IN INSULATORS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
10930517
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
CURRENT LIMITING ANTIFUSE PROGRAMMING PATH
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
10930518
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
METHOD OF ETCHING MATERIALS PATTERNED WITH A SINGLE LAYER 193NM RESIST
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
10930526
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
Title:
|
CURRENT LIMITING ANTIFUSE PROGRAMMING PATH
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2009
|
Application #:
|
10930543
|
Filing Dt:
|
08/30/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
METHOD AND SYSTEM FOR GENERATING REFERENCE VOLTAGES FOR SIGNAL RECEIVERS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2008
|
Application #:
|
10930657
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
HIGH PERMEABILITY LAYERED FILMS TO REDUCE NOISE IN HIGH SPEED INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
10930774
|
Filing Dt:
|
09/01/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
DIELECTRIC RELAXATION MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2009
|
Application #:
|
10930789
|
Filing Dt:
|
09/01/2004
|
Publication #:
|
|
Pub Dt:
|
07/21/2005
| | | | |
Title:
|
DIE PACKAGE HAVING AN ADHESIVE FLOW RESTRICTION AREA
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
10930895
|
Filing Dt:
|
08/30/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
PLASMA PROCESSING, DEPOSITION, AND ALD METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
10930976
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
STARTUP CIRCUIT AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2006
|
Application #:
|
10931129
|
Filing Dt:
|
09/01/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
IMPROVED SENSING OF RESISTANCE VARIABLE MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2007
|
Application #:
|
10931140
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
TECHNIQUES TO CREATE LOW K ILD FOR BEOL
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10931182
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
TECHNIQUES TO CREATE LOW K ILD FOR BEOL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2008
|
Application #:
|
10931326
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR TRANSMITTING DATA PACKETS IN A COMPUTER SYSTEM HAVING A MEMORY HUB ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
10931340
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
LANTHANIDE OXIDE / HAFNIUM OXIDE DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
10931343
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
LANTHANIDE OXIDE / HAFNIUM OXIDE DIELECTRIC LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2005
|
Application #:
|
10931353
|
Filing Dt:
|
08/31/2004
|
Title:
|
MEMORY SYSTEM AND METHOD USING ECC TO ACHIEVE LOW POWER REFRESH
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10931354
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
DELAY-LOCKED LOOP HAVING A PRE-SHIFT PHASE DETECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
10931356
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
HIGHLY RELIABLE AMORPHOUS HIGH-K GATE OXIDE ZRO2
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2008
|
Application #:
|
10931357
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
04/07/2005
| | | | |
Title:
|
LOCAL MULTILAYERED METALLIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10931360
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
PSEUDO CMOS DYNAMIC LOGIC WITH DELAYED CLOCKS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
10931361
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR DESIGNING A PATTERN ON A SEMICONDUCTOR SURFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2007
|
Application #:
|
10931362
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
SINGLE-ENDED PSEUDO-DIFFERENTIAL OUTPUT DRIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10931363
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
ULTRATHIN LEADFRAME BGA CIRCUIT PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
10931364
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
LANTHANIDE DOPED TIOX DIELECTRIC FILMS BY PLASMA OXIDATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
10931367
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
ONE TRANSISTOR SOI NON-VOLATILE RANDOM ACCESS MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2005
|
Application #:
|
10931368
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
SEMICONDUCTOR PROCESSING METHODS OF FORMING TRANSISTORS, SEMICONDUCTOR PROCESSING METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY CIRCUITRY, AND RELATED INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10931369
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
INTEGRATED CIRCUIT DEVICE HAVING REDUCED BOW AND METHOD FOR MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
10931375
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
FULLY ASSOCIATIVE TEXTURE CACHE HAVING CONTENT ADDRESSABLE MEMORY AND METHOD FOR USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
10931377
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
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CROSS DIFFUSION BARRIER LAYER IN POLYSILICON
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10931378
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/10/2005
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Title:
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ANTIFUSE STRUCTURES, METHODS, AND APPLICATIONS
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10931379
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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CAPACITIVELY-COUPLED LEVEL RESTORE CIRCUITS FOR LOW VOLTAGE SWING LOGIC CIRCUITS
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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10931397
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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METHOD AND APPARATUS FOR TIMING DOMAIN CROSSING
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Patent #:
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Issue Dt:
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10/24/2006
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Application #:
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10931472
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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MEMORY SYSTEM AND METHOD FOR STROBING DATA, COMMAND AND ADDRESS SIGNALS
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Patent #:
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Issue Dt:
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12/20/2005
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Application #:
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10931507
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Filing Dt:
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09/01/2004
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Publication #:
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Pub Dt:
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02/17/2005
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Title:
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MOSFETS INCLUDING A DIELECTRIC PLUG TO SUPPRESS SHORT-CHANNEL EFFECTS
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Patent #:
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Issue Dt:
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02/26/2008
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Application #:
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10931510
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Filing Dt:
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09/01/2004
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Publication #:
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Pub Dt:
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02/03/2005
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Title:
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PACKAGING OF ELECTRONIC CHIPS WITH AIR-BRIDGE STRUCTURES
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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10931513
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Filing Dt:
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09/01/2004
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Publication #:
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Pub Dt:
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02/10/2005
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Title:
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TRANSISTOR STRUCTURE HAVING REDUCED TRANSISTOR LEAKAGE ATTRIBUTES
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Patent #:
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Issue Dt:
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06/26/2007
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Application #:
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10931524
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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METHODS OF FORMING TRENCH ISOLATION IN THE FABRICATION OF INTEGRATED CIRCUITRY, METHODS OF FABRICATING MEMORY CIRCUITRY, INTEGRATED CIRCUITRY AND MEMORY INTEGRATED CIRCUITRY
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Patent #:
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Issue Dt:
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09/15/2009
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Application #:
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10931533
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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METHOD OF FORMING APPARATUS HAVING OXIDE FILMS FORMED USING ATOMIC LAYER DEPOSITION
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Patent #:
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Issue Dt:
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10/04/2005
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Application #:
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10931540
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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PROGRAMMABLE ARRAY LOGIC OR MEMORY DEVICES WITH ASYMMETRICAL TUNNEL BARRIERS
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Patent #:
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Issue Dt:
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08/07/2007
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Application #:
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10931541
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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METHODS FOR MAKING INTEGRATED-CIRCUIT WIRING FROM COPPER, SILVER, GOLD, AND OTHER METALS
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Patent #:
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Issue Dt:
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12/16/2008
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Application #:
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10931544
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/17/2005
| | | | |
Title:
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CAPACITOR STRUCTURES
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Patent #:
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Issue Dt:
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07/10/2007
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Application #:
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10931545
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/10/2005
| | | | |
Title:
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VERTICAL GAIN CELL
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Patent #:
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Issue Dt:
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05/22/2007
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Application #:
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10931552
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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SWITCHED CAPACITOR DRAM SENSE AMPLIFIER WITH IMMUNITY TO MISMATCH AND OFFSETS
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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10931553
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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ULTRA-THIN SEMICONDUCTORS BONDED ON GLASS SUBSTRATES
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Patent #:
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Issue Dt:
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12/19/2006
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Application #:
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10931567
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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METHODS OF FORMING SEMICONDUCTOR CIRCUITRY,
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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10931569
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/24/2005
| | | | |
Title:
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SEMICONDUCTOR CIRCUIT CONSTRUCTIONS
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Patent #:
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Issue Dt:
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11/20/2007
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Application #:
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10931573
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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OPERATING AN ELECTRONIC DEVICE HAVING A VERTICAL GAIN CELL THAT INCLUDES VERTICAL MOS TRANSISTORS
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Patent #:
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Issue Dt:
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11/15/2005
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Application #:
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10931579
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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METHODS OF FORMING SEMICONDUCTOR LOGIC CIRCUITRY, AND SEMICONDUCTOR LOGIC CIRCUIT CONSTRUCTIONS
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Patent #:
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Issue Dt:
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08/08/2006
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Application #:
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10931581
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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METHOD AND COMPOSITE FOR DECREASING CHARGE LEAKAGE
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Patent #:
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Issue Dt:
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04/03/2007
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Application #:
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10931587
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Filing Dt:
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09/01/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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LEVEL SHIFTER FOR LOW VOLTAGE OPERATION
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Patent #:
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Issue Dt:
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11/07/2006
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Application #:
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10931591
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/10/2005
| | | | |
Title:
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DOPANT BARRIER FOR DOPED GLASS IN MEMORY DEVICES
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Patent #:
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Issue Dt:
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06/23/2009
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Application #:
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10931593
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/10/2005
| | | | |
Title:
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LOW K INTERCONNECT DIELECTRIC USING SURFACE TRANSFORMATION
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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10931601
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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SCALABLE HIGH PERFORMANCE ANTIFUSE STRUCTURE AND PROCESS
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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10931607
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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SEMICONDUCTOR PROCESSING METHODS
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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10931678
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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METHODS FOR FABRICATION OF THIN SEMICONDUCTOR ASSEMBLIES INCLUDING REDISTRIBUTION LAYERS AND PACKAGES AND ASSEMBLIES FORMED THEREBY
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Patent #:
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Issue Dt:
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05/08/2007
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Application #:
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10931689
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Filing Dt:
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09/01/2004
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Publication #:
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Pub Dt:
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02/24/2005
| | | | |
Title:
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METHOD FOR REDUCING DRAIN DISTURB IN PROGRAMMING
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Patent #:
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Issue Dt:
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06/09/2009
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Application #:
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10931704
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Filing Dt:
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09/01/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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FLASH MEMORY WITH LOW TUNNEL BARRIER INTERPOLY INSULATORS
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Patent #:
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Issue Dt:
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03/06/2007
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Application #:
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10931711
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Filing Dt:
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09/01/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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PROGRAMMABLE MEMORY ADDRESS AND DECODE CIRCUITS WITH LOW TUNNEL BARRIER INTERPOLY INSULATORS
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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10931735
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Filing Dt:
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09/01/2004
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Title:
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ZERO-ENABLED FUSE-SET
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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10931749
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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STRAINED SEMICONDUCTOR BY WAFER BONDING WITH MISORIENTATION
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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10931772
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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CRITICAL DIMENSION CONTROL FOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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03/31/2009
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Application #:
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10931775
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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FLOATING LEAD FINGER ON A LEAD FRAME, A LEAD FRAME STRIP, AND A LEAD FRAME ASSEMBLY INCLUDING SAME
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Patent #:
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Issue Dt:
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06/26/2007
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Application #:
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10931786
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Filing Dt:
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09/01/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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SAMPLE AND HOLD MEMORY SENSE AMPLIFIER
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10931796
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Filing Dt:
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09/01/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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CMOS AMPLIFIERS WITH FREQUENCY COMPENSATING CAPACITORS
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Patent #:
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Issue Dt:
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08/29/2006
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Application #:
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10931822
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Filing Dt:
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09/01/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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METHOD FOR FILLING ELECTRICALLY DIFFERENT FEATURES
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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10931831
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR LOW VOLTAGE TEMPERATURE SENSING
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Patent #:
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Issue Dt:
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07/24/2007
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Application #:
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10931840
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Filing Dt:
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09/01/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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METHOD OF COMPOSITE GATE FORMATION
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|
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Patent #:
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Issue Dt:
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10/10/2006
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Application #:
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10931843
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/24/2005
| | | | |
Title:
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DELAY LOCKED LOOP CIRCUIT WITH TIME DELAY QUANTIFIER AND CONTROL
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Patent #:
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Issue Dt:
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06/26/2007
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Application #:
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10931844
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/10/2005
| | | | |
Title:
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BOW CONTROL IN AN ELECTRONIC PACKAGE
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|
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Patent #:
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Issue Dt:
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07/17/2007
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Application #:
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10931847
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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WAFER REINFORCEMENT STRUCTURE AND METHODS OF FABRICATION
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|