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11/26/2013
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13455394
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04/25/2012
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10/31/2013
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05/27/2014
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13455489
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04/25/2012
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10/31/2013
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CET AND GATE CURRENT LEAKAGE REDUCTION IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY HEAT TREATMENT AFTER DIFFUSION LAYER REMOVAL
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03/12/2013
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13455507
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04/25/2012
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08/16/2012
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06/03/2014
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13455579
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04/25/2012
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10/31/2013
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07/08/2014
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13455616
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04/25/2012
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10/31/2013
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METHODS OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE FORMED USING REPLACEMENT GATE TECHNIQUES
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03/25/2014
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13455653
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04/25/2012
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10/31/2013
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DIODE-TRIGGERED SILICON CONTROLLED RECTIFIER WITH AN INTEGRATED DIODE
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05/07/2013
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13455725
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04/25/2012
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08/23/2012
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METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER
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06/24/2014
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13455732
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04/25/2012
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10/31/2013
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DEVICE STRUCTURES COMPATIBLE WITH FIN-TYPE FIELD-EFFECT TRANSISTOR TECHNOLOGIES
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03/04/2014
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13456456
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04/26/2012
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10/31/2013
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NON-VOLATILE MEMORY DEVICE FORMED BY DUAL FLOATING GATE DEPOSIT
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09/02/2014
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13456596
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04/26/2012
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12/27/2012
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ACCURATE DEPOSITION OF NANO-OBJECTS ON A SURFACE
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12/23/2014
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13456745
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04/26/2012
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10/25/2012
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Generating Constraints in a Class Model
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02/03/2015
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13457601
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04/27/2012
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10/31/2013
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METAL-INSULATOR-METAL (MIM) CAPACITOR WITH DEEP TRENCH (DT) STRUCTURE AND METHOD IN A SILICON-ON-INSULATOR (SOI)
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03/10/2015
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13457692
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04/27/2012
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10/31/2013
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THROUGH-SILICON-VIA WITH SACRIFICIAL DIELECTRIC LINE
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08/09/2016
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13457722
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04/27/2012
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10/31/2013
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FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING
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09/30/2014
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13457735
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04/27/2012
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10/31/2013
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PHOTORESIST COMPOSITION CONTAINING A PROTECTED HYDROXYL GROUP FOR NEGATIVE DEVELOPMENT AND PATTERN FORMING METHOD USING THEREOF
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11/11/2014
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13457748
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04/27/2012
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10/31/2013
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NARROW BODY FIELD-EFFECT TRANSISTOR STRUCTURES WITH FREE-STANDING EXTENSION REGIONS
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06/14/2016
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13459460
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04/30/2012
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10/31/2013
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Assembly of Electronic and Optical Devices
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06/24/2014
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13459785
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04/30/2012
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10/31/2013
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ELONGATED VIA STRUCTURES
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02/18/2014
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13461912
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05/02/2012
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11/07/2013
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STRUCTURE FOR MONITORING STRESS INDUCED FAILURES IN INTERLEVEL DIELECTRIC LAYERS OF SOLDER BUMP INTEGRATED CIRCUITS
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08/12/2014
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13461935
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05/02/2012
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11/07/2013
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DOPED CORE TRIGATE FET STRUCTURE AND METHOD
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09/30/2014
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13461960
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05/02/2012
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08/23/2012
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PHOTORESIST COMPOSITIONS
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12/02/2014
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13462185
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05/02/2012
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11/07/2013
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METHODS OF FORMING SPACERS ON FINFETS AND OTHER SEMICONDUCTOR DEVICES
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05/30/2017
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05/02/2012
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11/07/2013
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INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE
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12/09/2014
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13462942
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05/03/2012
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11/07/2013
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INTEGRATED CIRCUIT WITH STRESS GENERATOR FOR STRESSING TEST DEVICES
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04/12/2016
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13462964
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05/03/2012
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08/30/2012
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METHOD AND APPARATUS FOR PROBING A WAFER
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05/20/2014
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13463283
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05/03/2012
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08/23/2012
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METHOD AND STRUCTURE FOR WORK FUNCTION ENGINEERING IN TRANSISTORS INCLUDING A HIGH DIELECTRIC CONSTANT GATE INSULATOR AND METAL GATE (HKMG)
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04/08/2014
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13463592
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05/03/2012
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11/07/2013
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FINFET COMPATIBLE PC-BOUNDED ESD DIODE
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07/02/2013
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13463879
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05/04/2012
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08/30/2012
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NI PLATING OF A BLM EDGE FOR PB-FREE C4 UNDERCUT CONTROL
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02/04/2014
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13464131
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05/04/2012
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11/07/2013
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CURRENT LEAKAGE IN RC ESD CLAMPS
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09/16/2014
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13464267
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05/04/2012
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10/03/2013
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LOW EXTENSION DOSE IMPLANTS IN SRAM FABRICATION
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07/15/2014
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13464966
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05/05/2012
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11/07/2013
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Techniques for the Fabrication of Thick Gate Dielectric
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06/03/2014
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13465129
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05/07/2012
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11/07/2013
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LAYOUT DESIGNS WITH VIA ROUTING STRUCTURES
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03/25/2014
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05/07/2012
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11/07/2013
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CROSS-COUPLING-BASED DESIGN USING DIFFUSION CONTACT STRUCTURES
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05/26/2015
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13465159
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05/07/2012
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11/07/2013
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FORMING CMOS WITH CLOSE PROXIMITY STRESSORS
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10/08/2013
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13465486
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05/07/2012
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METHODS OF FORMING CMOS SEMICONDUCTOR DEVICES
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08/19/2014
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13465633
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05/07/2012
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11/07/2013
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METHODS OF FORMING CONTACTS FOR SEMICONDUCTOR DEVICES USING A LOCAL INTERCONNECT PROCESSING SCHEME
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02/23/2016
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13465909
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05/07/2012
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11/07/2013
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METHOD FOR INCREASING THE ROBUSTNESS OF A DOUBLE PATTERNING ROUTER USED TO MANUFACTURE INTEGRATED CIRCUIT DEVICES
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04/28/2015
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13466234
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05/08/2012
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11/14/2013
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HORIZONTAL EPITAXY FURNACE FOR CHANNEL SIGE FORMATION
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10/28/2014
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13466895
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05/08/2012
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11/14/2013
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INTEGRATED CIRCUITS AND PROCESSES FOR FORMING INTEGRATED CIRCUITS HAVING AN EMBEDDED ELECTRICAL INTERCONNECT WITHIN A SUBSTRATE
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12/25/2012
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13467385
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05/09/2012
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08/30/2012
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VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
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03/24/2015
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13467659
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05/09/2012
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11/14/2013
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INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE
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03/24/2015
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13467730
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05/09/2012
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08/30/2012
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SEMICONDUCTOR DEVICE FABRICATION METHOD FOR IMPROVED ISOLATION REGIONS AND DEFECT-FREE ACTIVE SEMICONDUCTOR MATERIAL
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06/03/2014
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05/10/2012
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08/30/2012
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SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS
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02/11/2014
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13468268
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05/10/2012
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11/14/2013
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INPUT JITTER FILTER FOR A PHASE-LOCKED LOOP (PLL)
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07/09/2013
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13468270
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05/10/2012
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08/30/2012
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Structure and Method for Manufacturing Asymmetric Devices
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12/24/2013
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13468281
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05/10/2012
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08/30/2012
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MOSFET WITH A NANOWIRE CHANNEL AND FULLY SILICIDED (FUSI) WRAPPED AROUND GATE
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09/03/2013
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13468307
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05/10/2012
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09/06/2012
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MOSFET WITH A NANOWIRE CHANNEL AND FULLY SILICIDED (FUSI) WRAPPED AROUND GATE
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03/24/2015
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13469220
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05/11/2012
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11/14/2013
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FABRICATE SELF-FORMED NANOMETER PORE ARRAY AT WAFER SCALE FOR DNA SEQUENCING
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09/15/2015
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13469386
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05/11/2012
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11/14/2013
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CHIP IDENTIFICATION PATTERN AND METHOD OF FORMING
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01/20/2015
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13469464
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05/11/2012
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09/06/2012
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STRIPED ON-CHIP INDUCTOR
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07/01/2014
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05/11/2012
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09/06/2012
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ELECTRONIC DEVICE WITH AEROGEL THERMAL ISOLATION
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04/16/2013
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13469604
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05/11/2012
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08/30/2012
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MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)
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07/28/2015
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13470454
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05/14/2012
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11/14/2013
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METHODS OF FORMING SEMICONDUCTOR DEVICES WITH EMBEDDED SEMICONDUCTOR MATERIAL AS SOURCE/DRAIN REGIONS USING A REDUCED NUMBER OF SPACERS
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06/16/2015
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13470620
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05/14/2012
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11/14/2013
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BURIED-CHANNEL FIELD-EFFECT TRANSISTORS
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03/22/2016
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13470645
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05/14/2012
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11/14/2013
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01/21/2014
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05/15/2012
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09/06/2012
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SYSTEM AND METHOD TO IMPROVE CHIP YIELD, RELIABILITY AND PERFORMANCE
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03/24/2015
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13471711
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05/15/2012
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09/06/2012
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HIGH DENSITY LOW POWER NANOWIRE PHASE CHANGE MATERIAL MEMORY DEVICE
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02/11/2014
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13471736
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05/15/2012
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Pub Dt:
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11/21/2013
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Title:
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SUB-CIRCUIT MODELS WITH CORNER INSTANCES FOR VLSI DESIGNS
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Issue Dt:
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03/25/2014
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13471846
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Filing Dt:
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05/15/2012
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Pub Dt:
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11/21/2013
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Title:
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METHOD FOR FORMING A SELF-ALIGNED CONTACT OPENING BY A LATERAL ETCH
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01/14/2014
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13471852
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Filing Dt:
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05/15/2012
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Pub Dt:
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11/21/2013
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Title:
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MASK FREE PROTECTION OF WORK FUNCTION MATERIAL PORTIONS IN WIDE REPLACEMENT GATE ELECTRODES
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04/22/2014
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13471955
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05/15/2012
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Pub Dt:
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11/21/2013
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Title:
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MOS CAPACITORS WITH A FINFET PROCESS
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09/03/2013
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13472044
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Filing Dt:
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05/15/2012
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Publication #:
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Pub Dt:
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12/20/2012
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Title:
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BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION
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02/25/2014
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13472584
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05/16/2012
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Pub Dt:
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11/21/2013
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Title:
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SEMICONDUCTOR ACTIVE MATRIX ON BURIED INSULATOR
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Patent #:
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Issue Dt:
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08/26/2014
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13472605
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05/16/2012
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Pub Dt:
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11/21/2013
| | | | |
Title:
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METHOD AND STRUCTURE FOR FORMING FIN RESISTORS
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Issue Dt:
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12/30/2014
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13472674
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05/16/2012
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Pub Dt:
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11/21/2013
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Title:
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ELECTRICALLY CONTROLLED OPTICAL FUSE AND METHOD OF FABRICATION
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09/10/2013
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13472680
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05/16/2012
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Pub Dt:
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03/14/2013
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Title:
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CMOS STRUCTURE HAVING MULTIPLE THRESHOLD VOLTAGE DEVICES
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Patent #:
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02/18/2014
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13474090
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05/17/2012
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06/13/2013
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Title:
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WAFER DICING EMPLOYING EDGE REGION UNDERFILL REMOVAL
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Patent #:
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Issue Dt:
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03/22/2016
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13474257
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05/17/2012
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Pub Dt:
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09/13/2012
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Title:
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SELF ALIGNED DEVICE WITH ENHANCED STRESS AND METHODS OF MANUFACTURE
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02/04/2014
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13474304
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05/17/2012
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09/13/2012
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Title:
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ANALYZING ANTICIPATED VALUE AND EFFORT IN USING CLOUD COMPUTING TO PROCESS A SPECIFIED WORKLOAD
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04/09/2013
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13474349
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05/17/2012
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Pub Dt:
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09/13/2012
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Title:
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SELF-ALIGNED DUAL DAMASCENE BEOL STRUCTURES WITH PATTERNABLE LOW- K MATERIAL AND METHODS OF FORMING SAME
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12/10/2013
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13474443
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05/17/2012
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Pub Dt:
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11/21/2013
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Title:
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METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS ON BULK SEMICONDUCTOR SUBSTRATES
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10/22/2013
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13474790
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05/18/2012
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Pub Dt:
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09/13/2012
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Title:
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TECHNIQUE TO CREATE A BURIED PLATE IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE
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12/17/2013
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13474916
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Filing Dt:
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05/18/2012
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Publication #:
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Pub Dt:
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09/13/2012
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Title:
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METAL CAP FOR BACK END OF LINE (BEOL) INTERCONNECTS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE
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01/06/2015
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13474949
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05/18/2012
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Pub Dt:
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11/14/2013
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Title:
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BURIED-CHANNEL FIELD-EFFECT TRANSISTORS
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10/15/2013
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13475485
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05/18/2012
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Title:
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RETROGRADE SUBSTRATE FOR DEEP TRENCH CAPACITORS
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02/04/2014
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13475503
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Filing Dt:
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05/18/2012
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Pub Dt:
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11/22/2012
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Title:
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LOW TEMPERATURE SELECTIVE EPITAXY OF SILICON GERMANIUM ALLOYS EMPLOYING CYCLIC DEPOSIT AND ETCH
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Patent #:
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Issue Dt:
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12/15/2015
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13476056
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Filing Dt:
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05/26/2023
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Pub Dt:
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11/21/2013
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Title:
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VIA STRUCTURE FOR THREE-DIMENSIONAL CIRCUIT INTEGRATION
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Issue Dt:
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03/04/2014
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13476552
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Filing Dt:
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05/21/2012
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Pub Dt:
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11/21/2013
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Title:
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METHODS OF FORMING A SILICON SEED LAYER AND LAYERS OF SILICON AND SILICON-CONTAINING MATERIAL THEREFROM
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Issue Dt:
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11/12/2013
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13476567
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Filing Dt:
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05/21/2012
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Pub Dt:
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11/21/2013
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Title:
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MOS CAPACITORS WITH A FINFET PROCESS
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11/12/2013
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13476645
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05/21/2012
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11/21/2013
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Title:
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METHODS OF FORMING FINFET DEVICES WITH ALTERNATIVE CHANNEL MATERIALS
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03/18/2014
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13476692
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05/21/2012
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Pub Dt:
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11/21/2013
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Title:
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METHODS OF FORMING COPPER-BASED CONDUCTIVE STRUCTURES BY FORMING A COPPER-BASED SEED LAYER HAVING AN AS-DEPOSITED THICKNESS PROFILE AND THEREAFTER PERFORMING AN ETCHING PROCESS AND ELECTROLESS COPPER DEPOSITION
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04/08/2014
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13476860
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05/21/2012
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11/21/2013
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Title:
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METHODS FOR FORMING AN INTEGRATED CIRCUIT WITH STRAIGHTENED RECESS PROFILE
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06/23/2015
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13477978
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05/22/2012
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Pub Dt:
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11/28/2013
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Title:
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INDUCTOR WITH STACKED CONDUCTORS
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06/02/2015
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13478080
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05/22/2012
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Pub Dt:
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11/28/2013
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Title:
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INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES
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02/25/2014
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13478411
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05/23/2012
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Pub Dt:
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11/28/2013
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Title:
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FORMING FACET-LESS EPITAXY WITH A CUT MASK
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02/18/2014
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13478519
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05/23/2012
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Pub Dt:
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11/28/2013
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Title:
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SUPERIOR STABILITY OF CHARACTERISTICS OF TRANSISTORS HAVING AN EARLY FORMED HIGH-K METAL GATE
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Issue Dt:
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05/27/2014
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13478932
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05/23/2012
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Pub Dt:
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11/28/2013
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Title:
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DRIFT-INSENSITIVE OR INVARIANT MATERIAL FOR PHASE CHANGE MEMORY
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02/11/2014
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13479448
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05/24/2012
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Pub Dt:
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11/28/2013
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Title:
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MULTI-BANK RANDOM ACCESS MEMORY STRUCTURE WITH GLOBAL AND LOCAL SIGNAL BUFFERING FOR IMPROVED PERFORMANCE
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06/30/2015
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13479946
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05/24/2012
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Pub Dt:
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12/06/2012
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Title:
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WIRING SWITCH DESIGNS BASED ON A FIELD EFFECT DEVICE FOR RECONFIGURABLE INTERCONNECT PATHS
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05/28/2013
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13480329
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05/24/2012
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Pub Dt:
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11/08/2012
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Title:
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THIN SUBSTRATE FABRICATION USING STRESS-INDUCED SPALLING
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08/27/2013
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13480573
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05/25/2012
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Title:
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CLOSED-LOOP SLEW-RATE CONTROL FOR PHASE INTERPOLATOR OPTIMIZATION
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03/18/2014
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13480831
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05/25/2012
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11/28/2013
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Title:
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METHOD AND APPARATUS FOR SUBSTRATE-MASK ALIGNMENT
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07/16/2013
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13481048
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05/25/2012
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Title:
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BIPOLAR JUNCTION TRANSISTOR WITH EPITAXIAL CONTACTS
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04/29/2014
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13481062
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05/25/2012
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11/28/2013
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Title:
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SPALLING UTILIZING STRESSOR LAYER PORTIONS
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Issue Dt:
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07/05/2016
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13482166
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05/29/2012
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Pub Dt:
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12/05/2013
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Title:
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CONTENT ADDRESSABLE MEMORY EARLY-PREDICT LATE-CORRECT SINGLE ENDED SENSING
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08/26/2014
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13482262
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05/29/2012
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09/20/2012
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Title:
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METHOD TO IMPROVE NUCLEATION OF MATERIALS ON GRAPHENE AND CARBON NANOTUBES
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06/09/2015
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13482352
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05/29/2012
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Pub Dt:
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12/05/2013
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Title:
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CORROSION/ETCHING PROTECTION IN INTEGRATION CIRCUIT FABRICATIONS
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03/24/2015
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13482414
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05/29/2012
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Pub Dt:
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12/05/2013
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Title:
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REACTIVE BONDING OF A FLIP CHIP PACKAGE
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Issue Dt:
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06/16/2015
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13482438
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05/29/2012
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Pub Dt:
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12/05/2013
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Title:
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LIQUID CRYSTAL INTEGRATED CIRCUIT AND METHOD TO FABRICATE SAME
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Issue Dt:
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04/29/2014
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Application #:
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13482624
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Filing Dt:
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05/29/2012
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Pub Dt:
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12/05/2013
| | | | |
Title:
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Categorization of Design Rule Errors
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