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Reel/Frame:036550/0001   Pages: 983
Recorded: 09/03/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 14793
Page 88 of 148
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148
1
Patent #:
8239794
Issue Dt:
08/07/2012
Application #:
12568985
Filing Dt:
09/29/2009
Publication #:
US20110077882
Pub Dt:
03/31/2011
Title:
SYSTEM AND METHOD FOR ESTIMATING LEAKAGE CURRENT OF AN ELECTRONIC CIRCUIT
2
Patent #:
8133805
Issue Dt:
03/13/2012
Application #:
12569077
Filing Dt:
09/29/2009
Publication #:
US20100012858
Pub Dt:
01/21/2010
Title:
METHODS FOR FORMING DENSE DIELECTRIC LAYER OVER POROUS DIELECTRICS
3
Patent #:
8202783
Issue Dt:
06/19/2012
Application #:
12569200
Filing Dt:
09/29/2009
Publication #:
US20110074044
Pub Dt:
03/31/2011
Title:
PATTERNABLE LOW-K DIELECTRIC INTERCONNECT STRUCTURE WITH A GRADED CAP LAYER AND METHOD OF FABRICATION
4
Patent #:
8680872
Issue Dt:
03/25/2014
Application #:
12569294
Filing Dt:
09/29/2009
Publication #:
US20110074436
Pub Dt:
03/31/2011
Title:
IDENTIFICATION OF FALSE POSITIVES IN HIGH IMPEDANCE FAULT DETECTION
5
Patent #:
8336008
Issue Dt:
12/18/2012
Application #:
12569421
Filing Dt:
09/29/2009
Publication #:
US20110078641
Pub Dt:
03/31/2011
Title:
CHARACTERIZATION OF LONG RANGE VARIABILITY
6
Patent #:
8423328
Issue Dt:
04/16/2013
Application #:
12570195
Filing Dt:
09/30/2009
Publication #:
US20110077916
Pub Dt:
03/31/2011
Title:
METHOD OF DISTRIBUTING A RANDOM VARIABLE USING STATISTICALLY CORRECT SPATIAL INTERPOLATION CONTINUOUSLY WITH SPATIALLY INHOMOGENEOUS STATISTICAL CORRELATION VERSUS DISTANCE, STANDARD DEVIATION, AND MEAN
7
Patent #:
8145944
Issue Dt:
03/27/2012
Application #:
12570333
Filing Dt:
09/30/2009
Publication #:
US20110078499
Pub Dt:
03/31/2011
Title:
BUSINESS PROCESS ERROR HANDLING THROUGH PROCESS INSTANCE BACKUP AND RECOVERY
8
Patent #:
8084822
Issue Dt:
12/27/2011
Application #:
12570384
Filing Dt:
09/30/2009
Publication #:
US20110073951
Pub Dt:
03/31/2011
Title:
ENHANCED STRESS-RETENTION FIN-FET DEVICES AND METHODS OF FABRICATING ENHANCED STRESS RETENTION FIN-FET DEVICES
9
Patent #:
8232177
Issue Dt:
07/31/2012
Application #:
12570415
Filing Dt:
09/30/2009
Publication #:
US20110073985
Pub Dt:
03/31/2011
Title:
METHOD OF GENERATING UNIFORMLY ALIGNED WELL AND ISOLATION REGIONS IN A SUBSTRATE AND RESULTING STRUCTURE
10
Patent #:
8239804
Issue Dt:
08/07/2012
Application #:
12570418
Filing Dt:
09/30/2009
Publication #:
US20110078642
Pub Dt:
03/31/2011
Title:
METHOD FOR CALCULATING CAPACITANCE GRADIENTS IN VLSI LAYOUTS USING A SHAPE PROCESSING ENGINE
11
Patent #:
8337627
Issue Dt:
12/25/2012
Application #:
12571477
Filing Dt:
10/01/2009
Publication #:
US20110079255
Pub Dt:
04/07/2011
Title:
CLEANING EXHAUST SCREENS IN A MANUFACTURING PROCESS
12
Patent #:
8230378
Issue Dt:
07/24/2012
Application #:
12572297
Filing Dt:
10/02/2009
Publication #:
US20100023913
Pub Dt:
01/28/2010
Title:
METHOD FOR IC WIRING YIELD OPTIMIZATION, INCLUDING WIRE WIDENING DURING AND AFTER ROUTING
13
Patent #:
8610283
Issue Dt:
12/17/2013
Application #:
12573183
Filing Dt:
10/05/2009
Publication #:
US20110079907
Pub Dt:
04/07/2011
Title:
SEMICONDUCTOR DEVICE HAVING A COPPER PLUG
14
Patent #:
8993428
Issue Dt:
03/31/2015
Application #:
12573188
Filing Dt:
10/05/2009
Publication #:
US20110079827
Pub Dt:
04/07/2011
Title:
STRUCTURE AND METHOD TO CREATE A DAMASCENE LOCAL INTERCONNECT DURING METAL GATE DEPOSITION
15
Patent #:
NONE
Issue Dt:
Application #:
12573364
Filing Dt:
10/05/2009
Publication #:
US20100019354
Pub Dt:
01/28/2010
Title:
SEMICONDUCTOR CHIP SHAPE ALTERATION
16
Patent #:
7867897
Issue Dt:
01/11/2011
Application #:
12573407
Filing Dt:
10/05/2009
Publication #:
US20100021656
Pub Dt:
01/28/2010
Title:
LOW LEAKAGE METAL-CONTAINING CAP PROCESS USING OXIDATION
17
Patent #:
8546252
Issue Dt:
10/01/2013
Application #:
12573440
Filing Dt:
10/05/2009
Publication #:
US20110079828
Pub Dt:
04/07/2011
Title:
METAL GATE FET HAVING REDUCED THRESHOLD VOLTAGE ROLL-OFF
18
Patent #:
7795940
Issue Dt:
09/14/2010
Application #:
12573910
Filing Dt:
10/06/2009
Publication #:
US20100019816
Pub Dt:
01/28/2010
Title:
MICRO-PHASE ADJUSTING AND MICRO-PHASE ADJUSTING MIXER CIRCUITS DESIGNED WITH STANDARD FIELD EFFECT TRANSISTOR STRUCTURES
19
Patent #:
7927895
Issue Dt:
04/19/2011
Application #:
12574118
Filing Dt:
10/06/2009
Publication #:
US20110080180
Pub Dt:
04/07/2011
Title:
VARYING CAPACITANCE VOLTAGE CONTRAST STRUCTURES TO DETERMINE DEFECT RESISTANCE
20
Patent #:
8680617
Issue Dt:
03/25/2014
Application #:
12574126
Filing Dt:
10/06/2009
Publication #:
US20110079851
Pub Dt:
04/07/2011
Title:
SPLIT LEVEL SHALLOW TRENCH ISOLATION FOR AREA EFFICIENT BODY CONTACTS IN SOI MOSFETS
21
Patent #:
8377631
Issue Dt:
02/19/2013
Application #:
12574171
Filing Dt:
10/06/2009
Publication #:
US20110079579
Pub Dt:
04/07/2011
Title:
PLANARIZATION OVER TOPOGRAPHY WITH MOLECULAR GLASS MATERIALS
22
Patent #:
8946028
Issue Dt:
02/03/2015
Application #:
12574296
Filing Dt:
10/06/2009
Publication #:
US20110079855
Pub Dt:
04/07/2011
Title:
MERGED FINFETS AND METHOD OF MANUFACTURING THE SAME
23
Patent #:
7943458
Issue Dt:
05/17/2011
Application #:
12574318
Filing Dt:
10/06/2009
Publication #:
US20110081754
Pub Dt:
04/07/2011
Title:
METHODS FOR OBTAINING GATE STACKS WITH TUNABLE THRESHOLD VOLTAGE AND SCALING
24
Patent #:
8626480
Issue Dt:
01/07/2014
Application #:
12574440
Filing Dt:
10/06/2009
Publication #:
US20110082680
Pub Dt:
04/07/2011
Title:
COMPACT MODEL FOR DEVICE/CIRCUIT/CHIP LEAKAGE CURRENT (IDDQ) CALCULATION INCLUDING PROCESS INDUCED UPLIFT FACTORS
25
Patent #:
8125048
Issue Dt:
02/28/2012
Application #:
12574926
Filing Dt:
10/07/2009
Publication #:
US20110079874
Pub Dt:
04/07/2011
Title:
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
26
Patent #:
8389663
Issue Dt:
03/05/2013
Application #:
12575515
Filing Dt:
10/08/2009
Publication #:
US20110083887
Pub Dt:
04/14/2011
Title:
PHOTO-PATTERNABLE DIELECTRIC MATERIALS CURABLE TO POROUS DIELECTRIC MATERIALS, FORMULATIONS, PRECURSORS AND METHODS OF USE THEREOF
27
Patent #:
8138523
Issue Dt:
03/20/2012
Application #:
12575962
Filing Dt:
10/08/2009
Publication #:
US20110084315
Pub Dt:
04/14/2011
Title:
SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL)
28
Patent #:
8408262
Issue Dt:
04/02/2013
Application #:
12575968
Filing Dt:
10/08/2009
Publication #:
US20110083786
Pub Dt:
04/14/2011
Title:
ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES
29
Patent #:
8482132
Issue Dt:
07/09/2013
Application #:
12575980
Filing Dt:
10/08/2009
Publication #:
US20110084403
Pub Dt:
04/14/2011
Title:
PAD BONDING EMPLOYING A SELF-ALIGNED PLATED LINER FOR ADHESION ENHANCEMENT
30
Patent #:
8143135
Issue Dt:
03/27/2012
Application #:
12575989
Filing Dt:
10/08/2009
Publication #:
US20110084360
Pub Dt:
04/14/2011
Title:
EMBEDDED SERIES DEEP TRENCH CAPACITORS AND METHODS OF MANUFACTURE
31
Patent #:
8130525
Issue Dt:
03/06/2012
Application #:
12576275
Filing Dt:
10/09/2009
Publication #:
US20110088005
Pub Dt:
04/14/2011
Title:
METHOD AND APPARATUS FOR CONFIGURING A CONTENT-ADDRESSABLE MEMORY (CAM) DESIGN AS BINARY CAM OR TERNARY CAM
32
Patent #:
8538129
Issue Dt:
09/17/2013
Application #:
12576597
Filing Dt:
10/09/2009
Publication #:
US20110085723
Pub Dt:
04/14/2011
Title:
MASK PROGRAM DEFECT TEST
33
Patent #:
8288657
Issue Dt:
10/16/2012
Application #:
12577259
Filing Dt:
10/12/2009
Publication #:
US20110083888
Pub Dt:
04/14/2011
Title:
NOISE COUPLING REDUCTION AND IMPEDANCE DISCONTINUITY CONTROL IN HIGH-SPEED CERAMIC MODULES
34
Patent #:
8082464
Issue Dt:
12/20/2011
Application #:
12578372
Filing Dt:
10/13/2009
Publication #:
US20110087919
Pub Dt:
04/14/2011
Title:
MANAGING AVAILABILITY OF A COMPONENT HAVING A CLOSED ADDRESS SPACE
35
Patent #:
8495427
Issue Dt:
07/23/2013
Application #:
12578975
Filing Dt:
10/14/2009
Publication #:
US20110087927
Pub Dt:
04/14/2011
Title:
DETECTING DEFECTS IN DEPLOYED SYSTEMS
36
Patent #:
8218378
Issue Dt:
07/10/2012
Application #:
12579089
Filing Dt:
10/14/2009
Publication #:
US20110085390
Pub Dt:
04/14/2011
Title:
WORD-LINE LEVEL SHIFT CIRCUIT
37
Patent #:
8538740
Issue Dt:
09/17/2013
Application #:
12579124
Filing Dt:
10/14/2009
Publication #:
US20110087469
Pub Dt:
04/14/2011
Title:
REAL-TIME PERFORMANCE MODELING OF SOFTWARE SYSTEMS WITH MULTI-CLASS WORKLOAD
38
Patent #:
NONE
Issue Dt:
Application #:
12579159
Filing Dt:
10/14/2009
Publication #:
US20110088008
Pub Dt:
04/14/2011
Title:
METHOD FOR CONVERSION OF COMMERCIAL MICROPROCESSOR TO RADIATION-HARDENED PROCESSOR AND RESULTING PROCESSOR
39
Patent #:
8296256
Issue Dt:
10/23/2012
Application #:
12579442
Filing Dt:
10/15/2009
Publication #:
US20110093431
Pub Dt:
04/21/2011
Title:
SAT-BASED SYNTHESIS OF A CLOCK GATING FUNCTION
40
Patent #:
8327302
Issue Dt:
12/04/2012
Application #:
12580330
Filing Dt:
10/16/2009
Publication #:
US20110093825
Pub Dt:
04/21/2011
Title:
TECHNIQUES FOR ANALYSIS OF LOGIC DESIGNS WITH TRANSIENT LOGIC
41
Patent #:
8423341
Issue Dt:
04/16/2013
Application #:
12581208
Filing Dt:
10/19/2009
Publication #:
US20110093242
Pub Dt:
04/21/2011
Title:
METHOD AND SYSTEM FOR CONSTRUCTING CORNER MODELS FOR MULTIPLE PERFORMANCE TARGETS
42
Patent #:
8233337
Issue Dt:
07/31/2012
Application #:
12581440
Filing Dt:
10/19/2009
Publication #:
US20110090750
Pub Dt:
04/21/2011
Title:
SRAM DELAY CIRCUIT THAT TRACKS BITCELL CHARACTERISTICS
43
Patent #:
8034692
Issue Dt:
10/11/2011
Application #:
12581924
Filing Dt:
10/20/2009
Publication #:
US20110089499
Pub Dt:
04/21/2011
Title:
STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES
44
Patent #:
8288222
Issue Dt:
10/16/2012
Application #:
12582139
Filing Dt:
10/20/2009
Publication #:
US20110089495
Pub Dt:
04/21/2011
Title:
APPLICATION OF CLUSTER BEAM IMPLANTATION FOR FABRICATING THRESHOLD VOLTAGE ADJUSTED FETS
45
Patent #:
8198396
Issue Dt:
06/12/2012
Application #:
12583030
Filing Dt:
08/12/2009
Publication #:
US20090304908
Pub Dt:
12/10/2009
Title:
METHODS OF FABRICATING PLASTICIZED, ANTIPLASTICIZED AND CRYSTALLINE CONDUCTING POLYMERS AND PRECURSORS THEREOF
46
Patent #:
NONE
Issue Dt:
Application #:
12583108
Filing Dt:
08/13/2009
Publication #:
US20090302474
Pub Dt:
12/10/2009
Title:
Atomic laminates for diffucion barrier applications
47
Patent #:
8362568
Issue Dt:
01/29/2013
Application #:
12583933
Filing Dt:
08/28/2009
Publication #:
US20110049583
Pub Dt:
03/03/2011
Title:
RECESSED CONTACT FOR MULTI-GATE FET OPTIMIZING SERIES RESISTANCE
48
Patent #:
8298459
Issue Dt:
10/30/2012
Application #:
12603567
Filing Dt:
10/21/2009
Publication #:
US20110089589
Pub Dt:
04/21/2011
Title:
SPIN-MOUNTED FABRICATION OF INJECTION MOLDED MICRO-OPTICS
49
Patent #:
8102599
Issue Dt:
01/24/2012
Application #:
12603569
Filing Dt:
10/21/2009
Publication #:
US20110090570
Pub Dt:
04/21/2011
Title:
FABRICATION OF OPTICAL FILTERS INTEGRATED WITH INJECTION MOLDED MICROLENSES
50
Patent #:
9018024
Issue Dt:
04/28/2015
Application #:
12603668
Filing Dt:
10/22/2009
Publication #:
US20110095393
Pub Dt:
04/28/2011
Title:
CREATING EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) HAVING SUBSTANTIALLY UNIFORM THICKNESS
51
Patent #:
8124427
Issue Dt:
02/28/2012
Application #:
12603671
Filing Dt:
10/22/2009
Publication #:
US20110097824
Pub Dt:
04/28/2011
Title:
METHOD OF CREATING AN EXTREMELY THIN SEMICONDUCTOR-ON- INSULATOR (ETSOI) LAYER HAVING A UNIFORM THICKNESS
52
Patent #:
8301290
Issue Dt:
10/30/2012
Application #:
12603679
Filing Dt:
10/22/2009
Publication #:
US20110098838
Pub Dt:
04/28/2011
Title:
SYSTEM AND METHOD FOR CORRECTING SYSTEMATIC PARAMETRIC VARIATIONS ON INTEGRATED CIRCUIT CHIPS IN ORDER TO MINIMIZE CIRCUIT LIMITED YIELD LOSS
53
Patent #:
8110483
Issue Dt:
02/07/2012
Application #:
12603737
Filing Dt:
10/22/2009
Publication #:
US20110095366
Pub Dt:
04/28/2011
Title:
FORMING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER
54
Patent #:
8207027
Issue Dt:
06/26/2012
Application #:
12603838
Filing Dt:
10/22/2009
Publication #:
US20100041198
Pub Dt:
02/18/2010
Title:
TRIPLE GATE AND DOUBLE GATE FINFETS WITH DIFFERENT VERTICAL DIMENSION FINS
55
Patent #:
7954021
Issue Dt:
05/31/2011
Application #:
12604614
Filing Dt:
10/23/2009
Publication #:
US20110099419
Pub Dt:
04/28/2011
Title:
SOLID STATE DRIVE WITH FLASH SPARING
56
Patent #:
8407633
Issue Dt:
03/26/2013
Application #:
12605417
Filing Dt:
10/26/2009
Publication #:
US20110099527
Pub Dt:
04/28/2011
Title:
DYNAMICALLY RECONFIGURABLE SELF-MONITORING CIRCUIT
57
Patent #:
8614492
Issue Dt:
12/24/2013
Application #:
12605523
Filing Dt:
10/26/2009
Publication #:
US20110095267
Pub Dt:
04/28/2011
Title:
NANOWIRE STRESS SENSORS, STRESS SENSOR INTEGRATED CIRCUITS, AND DESIGN STRUCTURES FOR A STRESS SENSOR INTEGRATED CIRCUIT
58
Patent #:
8605254
Issue Dt:
12/10/2013
Application #:
12605732
Filing Dt:
10/26/2009
Publication #:
US20110096313
Pub Dt:
04/28/2011
Title:
Constrained Optimization Of Lithographic Source Intensities Under Contingent Requirements
59
Patent #:
8035141
Issue Dt:
10/11/2011
Application #:
12607104
Filing Dt:
10/28/2009
Publication #:
US20110095343
Pub Dt:
04/28/2011
Title:
BI-LAYER NFET EMBEDDED STRESSOR ELEMENT AND INTEGRATION TO ENHANCE DRIVE CURRENT
60
Patent #:
NONE
Issue Dt:
Application #:
12607110
Filing Dt:
10/28/2009
Publication #:
US20110095379
Pub Dt:
04/28/2011
Title:
SCALING OF METAL GATE WITH ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT
61
Patent #:
8120058
Issue Dt:
02/21/2012
Application #:
12607116
Filing Dt:
10/28/2009
Publication #:
US20110095333
Pub Dt:
04/28/2011
Title:
HIGH-DRIVE CURRENT MOSFET
62
Patent #:
8307994
Issue Dt:
11/13/2012
Application #:
12607258
Filing Dt:
10/28/2009
Publication #:
US20110094884
Pub Dt:
04/28/2011
Title:
SURFACE CHARGE ENABLED NANOPOROUS SEMI-PERMEABLE MEMBRANE FOR DESALINATION
63
Patent #:
8159060
Issue Dt:
04/17/2012
Application #:
12608368
Filing Dt:
10/29/2009
Publication #:
US20110101537
Pub Dt:
05/05/2011
Title:
HYBRID BONDING INTERFACE FOR 3-DIMENSIONAL CHIP INTEGRATION
64
Patent #:
8232196
Issue Dt:
07/31/2012
Application #:
12608377
Filing Dt:
10/29/2009
Publication #:
US20110100697
Pub Dt:
05/05/2011
Title:
INTERCONNECT STRUCTURE HAVING A VIA WITH A VIA GOUGING FEATURE AND DIELECTRIC LINER SIDEWALLS FOR BEOL INTEGRATION
65
Patent #:
7961996
Issue Dt:
06/14/2011
Application #:
12608518
Filing Dt:
10/29/2009
Publication #:
US20100046883
Pub Dt:
02/25/2010
Title:
COUPLING DEVICE FOR USE IN OPTICAL WAVEGUIDES
66
Patent #:
NONE
Issue Dt:
Application #:
12609555
Filing Dt:
10/30/2009
Publication #:
US20100044805
Pub Dt:
02/25/2010
Title:
METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-k GATE DIELECTRIC STACKS
67
Patent #:
8340939
Issue Dt:
12/25/2012
Application #:
12610090
Filing Dt:
10/30/2009
Publication #:
US20110106483
Pub Dt:
05/05/2011
Title:
METHOD AND APPARATUS FOR SELECTING PATHS FOR USE IN AT-SPEED TESTING
68
Patent #:
8781792
Issue Dt:
07/15/2014
Application #:
12610291
Filing Dt:
10/31/2009
Publication #:
US20110106497
Pub Dt:
05/05/2011
Title:
Yield Computation and Optimization for Selective Voltage Binning
69
Patent #:
7932134
Issue Dt:
04/26/2011
Application #:
12610563
Filing Dt:
11/02/2009
Publication #:
US20100047972
Pub Dt:
02/25/2010
Title:
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
70
Patent #:
8354351
Issue Dt:
01/15/2013
Application #:
12610630
Filing Dt:
11/02/2009
Publication #:
US20100044592
Pub Dt:
02/25/2010
Title:
SERIAL IRRADIATION OF A SUBSTRATE BY MULTIPLE RADIATION SOURCES
71
Patent #:
8288271
Issue Dt:
10/16/2012
Application #:
12610679
Filing Dt:
11/02/2009
Publication #:
US20110101507
Pub Dt:
05/05/2011
Title:
METHOD FOR REWORKING ANTIREFLECTIVE COATING OVER SEMICONDUCTOR SUBSTRATE
72
Patent #:
7791086
Issue Dt:
09/07/2010
Application #:
12610791
Filing Dt:
11/02/2009
Publication #:
US20100044724
Pub Dt:
02/25/2010
Title:
DEVICE FOR DEFEATING REVERSE ENGINEERING OF INTEGRATED CIRCUITS BY OPTICAL MEANS
73
Patent #:
7791087
Issue Dt:
09/07/2010
Application #:
12610808
Filing Dt:
11/02/2009
Publication #:
US20100044725
Pub Dt:
02/25/2010
Title:
DEVICE FOR DEFEATING REVERSE ENGINEERING OF INTEGRATED CIRCUITS BY OPTICAL MEANS
74
Patent #:
7781782
Issue Dt:
08/24/2010
Application #:
12610823
Filing Dt:
11/02/2009
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US20100046756
Pub Dt:
02/25/2010
Title:
DEVICE FOR DEFEATING REVERSE ENGINEERING OF INTEGRATED CIRCUITS BY OPTICAL MEANS
75
Patent #:
8298751
Issue Dt:
10/30/2012
Application #:
12611043
Filing Dt:
11/02/2009
Publication #:
US20110104900
Pub Dt:
05/05/2011
Title:
ALKALINE RINSE AGENTS FOR USE IN LITHOGRAPHIC PATTERNING
76
Patent #:
8614435
Issue Dt:
12/24/2013
Application #:
12611421
Filing Dt:
11/03/2009
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US20110101308
Pub Dt:
05/05/2011
Title:
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77
Patent #:
8716797
Issue Dt:
05/06/2014
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12611444
Filing Dt:
11/03/2009
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US20110101455
Pub Dt:
05/05/2011
Title:
FINFET SPACER FORMATION BY ORIENTED IMPLANTATION
78
Patent #:
8210741
Issue Dt:
07/03/2012
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12611519
Filing Dt:
11/03/2009
Publication #:
US20100046574
Pub Dt:
02/25/2010
Title:
APPARATUS FOR THERMAL CHARACTERIZATION UNDER NON-UNIFORM HEAT LOAD
79
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8689180
Issue Dt:
04/01/2014
Application #:
12611561
Filing Dt:
11/03/2009
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US20110107297
Pub Dt:
05/05/2011
Title:
SYSTEMS AND METHODS FOR RESOURCE LEAK DETECTION
80
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8557665
Issue Dt:
10/15/2013
Application #:
12611577
Filing Dt:
11/03/2009
Publication #:
US20100047984
Pub Dt:
02/25/2010
Title:
SELF-ALIGNED METAL-SEMICONDUCTOR ALLOY AND METALLIZATION FOR SUB-LITHOGRAPHIC SOURCE AND DRAIN CONTACTS
81
Patent #:
8021971
Issue Dt:
09/20/2011
Application #:
12611946
Filing Dt:
11/04/2009
Publication #:
US20110101472
Pub Dt:
05/05/2011
Title:
STRUCTURE AND METHOD TO FORM A THERMALLY STABLE SILICIDE IN NARROW DIMENSION GATE STACKS
82
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8514374
Issue Dt:
08/20/2013
Application #:
12611947
Filing Dt:
11/04/2009
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US20110102760
Pub Dt:
05/05/2011
Title:
ALIGNMENT METHOD FOR SEMICONDUCTOR PROCESSING
83
Patent #:
8105928
Issue Dt:
01/31/2012
Application #:
12612018
Filing Dt:
11/04/2009
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US20110101309
Pub Dt:
05/05/2011
Title:
GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP
84
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8679906
Issue Dt:
03/25/2014
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12612035
Filing Dt:
11/04/2009
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US20100044794
Pub Dt:
02/25/2010
Title:
ASYMMETRIC MULTI-GATED TRANSISTOR AND METHOD FOR FORMING
85
Patent #:
8168449
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05/01/2012
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12612258
Filing Dt:
11/04/2009
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US20110104827
Pub Dt:
05/05/2011
Title:
TEMPLATE-REGISTERED DIBLOCK COPOLYMER MASK FOR MRAM DEVICE FORMATION
86
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9047144
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06/02/2015
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12612624
Filing Dt:
11/04/2009
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US20110107354
Pub Dt:
05/05/2011
Title:
SYSTEM AND METHOD FOR PROVIDING QUALITY-OF-SERVICES IN A MULTI-EVENT PROCESSING ENVIRONMENT
87
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NONE
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12612710
Filing Dt:
11/05/2009
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US20110101440
Pub Dt:
05/05/2011
Title:
TWO PFET SOI MEMORY CELLS
88
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7829427
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11/09/2010
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12612743
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11/05/2009
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US20100047990
Pub Dt:
02/25/2010
Title:
METHOD OF FABRICATING A HIGH Q FACTOR INTEGRATED CIRCUIT INDUCTOR
89
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NONE
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12612909
Filing Dt:
11/05/2009
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US20110107291
Pub Dt:
05/05/2011
Title:
A DESIGN SYSTEM AND A DESIGN METHOD THAT ALLOW FOR COMPENSATION OF REGIONAL TIMING VARIATIONS DURING TIMING ANALYSIS
90
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7989312
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08/02/2011
Application #:
12612957
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11/05/2009
Publication #:
US20100044759
Pub Dt:
02/25/2010
Title:
DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS
91
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8298948
Issue Dt:
10/30/2012
Application #:
12613551
Filing Dt:
11/06/2009
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US20110108990
Pub Dt:
05/12/2011
Title:
CAPPING OF COPPER INTERCONNECT LINES IN INTEGRATED CIRCUIT DEVICES
92
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8587063
Issue Dt:
11/19/2013
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12613574
Filing Dt:
11/06/2009
Publication #:
US20110108943
Pub Dt:
05/12/2011
Title:
HYBRID DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH ENHANCED MOBILITY CHANNELS
93
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8323868
Issue Dt:
12/04/2012
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12613800
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11/06/2009
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US20110111339
Pub Dt:
05/12/2011
Title:
BILAYER SYSTEMS INCLUDING A POLYDIMETHYLGLUTARIMIDE-BASED BOTTOM LAYER AND COMPOSITIONS THEREOF
94
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8492901
Issue Dt:
07/23/2013
Application #:
12614062
Filing Dt:
11/06/2009
Publication #:
US20110108958
Pub Dt:
05/12/2011
Title:
Metal Oxide Semiconductor (MOS)-Compatible High-Aspect Ratio Through-Wafer Vias and Low-Stress Configuration Thereof
95
Patent #:
8263879
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09/11/2012
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12614224
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11/06/2009
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US20110108316
Pub Dt:
05/12/2011
Title:
AXIOCENTRIC SCRUBBING LAND GRID ARRAY CONTACTS AND METHODS FOR FABRICATION
96
Patent #:
8959764
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02/24/2015
Application #:
12614231
Filing Dt:
11/06/2009
Publication #:
US20110111647
Pub Dt:
05/12/2011
Title:
METALLURGICAL CLAMSHELL METHODS FOR MICRO LAND GRID ARRAY FABRICATION
97
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8106513
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01/31/2012
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12614861
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11/09/2009
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US20100052172
Pub Dt:
03/04/2010
Title:
COPPER DAMASCENE AND DUAL DAMASCENE INTERCONNECT WIRING
98
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7993999
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08/09/2011
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12614906
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11/09/2009
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US20110108920
Pub Dt:
05/12/2011
Title:
HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE
99
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8343877
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01/01/2013
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12614952
Filing Dt:
11/09/2009
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US20110111592
Pub Dt:
05/12/2011
Title:
ANGLE ION IMPLANT TO RE-SHAPE SIDEWALL IMAGE TRANSFER PATTERNS
100
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8324036
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12/04/2012
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12614986
Filing Dt:
11/09/2009
Publication #:
US20110108961
Pub Dt:
05/12/2011
Title:
DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS FOR AN INTEGRATED CIRCUIT
Assignor
1
INTERNATIONAL BUSINESS MACHINES CORPORATION
Exec Dt:
06/29/2015
Assignee
1
GLOBALFOUNDRIES U.S. 2 LLC
2070 ROUTE 52
HOPEWELL JUNCTION, NEW YORK 12533
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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