|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
11125097
|
Filing Dt:
|
05/10/2005
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
ECLIPSE ELIMINATION BY MONITORING THE PIXEL SIGNAL LEVEL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
11126455
|
Filing Dt:
|
05/10/2005
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
Title:
|
SEMICONDUCTOR CONSTRUCTIONS AND TRANSISTOR GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2008
|
Application #:
|
11126682
|
Filing Dt:
|
05/11/2005
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
MEMORY BLOCK ERASING IN A FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2009
|
Application #:
|
11126747
|
Filing Dt:
|
05/11/2005
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
INTERNAL DATA COMPARISON FOR MEMORY TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11126826
|
Filing Dt:
|
05/11/2005
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
N WELL IMPLANTS TO SEPARATE BLOCKS IN A FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
11127465
|
Filing Dt:
|
05/12/2005
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
DEFECTIVE BLOCK HANDLING IN A FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
11127466
|
Filing Dt:
|
05/12/2005
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
FLASH MEMORY ARRAY USING ADJACENT BIT LINE AS SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
11127526
|
Filing Dt:
|
05/12/2005
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR FILTERING OUTPUT DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
11127599
|
Filing Dt:
|
05/12/2005
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
Title:
|
DATA COMPRESSION READ MODE FOR MEMORY TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
11127618
|
Filing Dt:
|
05/12/2005
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
BAND-ENGINEERED MULTI-GATED NON-VOLATILE MEMORY DEVICE WITH ENHANCED ATTRIBUTES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
11127810
|
Filing Dt:
|
05/12/2005
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
MULTIPLE-LEVEL DATA COMPRESSION READ MODE FOR MEMORY TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2010
|
Application #:
|
11127942
|
Filing Dt:
|
05/11/2005
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
IMPRINT TEMPLATES FOR IMPRINT LITHOGRAPHY, AND METHODS OF PATTERNING A PLURALITY OF SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
11127943
|
Filing Dt:
|
05/11/2005
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
METHODS OF FORMING ELECTRICALLY CONDUCTIVE PLUGS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
11127944
|
Filing Dt:
|
05/11/2005
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
METHODS OF ETCHING OXIDE, REDUCING ROUGHNESS, AND FORMING CAPACITOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
11127945
|
Filing Dt:
|
05/11/2005
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
DEPOSITION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
11128176
|
Filing Dt:
|
05/13/2005
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
Title:
|
METHOD FOR FORMING A LOW LEAKAGE CONTACT IN A CMOS IMAGER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
11128585
|
Filing Dt:
|
05/13/2005
|
Title:
|
MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL AND STAGGERED LOCAL BIT LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2008
|
Application #:
|
11129105
|
Filing Dt:
|
05/13/2005
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
LOW TEMPERATURE METHODS OF FORMING BACK SIDE REDISTRIBUTION LAYERS IN ASSOCIATION WITH THROUGH WAFER INTERCONNECTS, SEMICONDUCTOR DEVICES INCLUDING SAME, AND ASSEMBLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2008
|
Application #:
|
11129150
|
Filing Dt:
|
05/13/2005
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
Title:
|
DETECTION CIRCUIT FOR MIXED ASYNCHRONOUS AND SYNCHRONOUS MEMORY OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
11129315
|
Filing Dt:
|
05/16/2005
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
POWER CIRCUITS FOR REDUCING A NUMBER OF POWER SUPPLY VOLTAGE TAPS REQUIRED FOR SENSING A RESISTIVE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2008
|
Application #:
|
11129502
|
Filing Dt:
|
05/13/2005
|
Title:
|
MEMORY ARRAY WITH ULTRA-THIN ETCHED PILLAR SURROUND GATE ACCESS TRANSISTORS AND BURIED DATA/BIT LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2010
|
Application #:
|
11129630
|
Filing Dt:
|
05/13/2005
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICES, CAPACITOR ANTIFUSES, DYNAMIC RANDOM ACCESS MEMORIES, AND CELL PLATE BIAS CONNECTION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
11129884
|
Filing Dt:
|
05/16/2005
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
ISOLATION TRENCHES FOR MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2007
|
Application #:
|
11130598
|
Filing Dt:
|
05/17/2005
|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
Title:
|
WRITING TO FERROELECTRIC MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
11130663
|
Filing Dt:
|
05/17/2005
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
Title:
|
WRITING TO FERROELECTRIC MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
11130760
|
Filing Dt:
|
05/17/2005
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
Title:
|
ETCHING METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
11131006
|
Filing Dt:
|
05/17/2005
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
NOVEL LOW POWER NON-VOLATILE MEMORY AND GATE STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
11131070
|
Filing Dt:
|
07/07/2005
|
Publication #:
|
|
Pub Dt:
|
01/19/2006
| | | | |
Title:
|
GAS COMPOSITIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
11131078
|
Filing Dt:
|
05/17/2005
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
Title:
|
METHOD OF FORMING A CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
11131081
|
Filing Dt:
|
05/17/2005
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
Title:
|
METHOD TO PREVENT BIT LINE CAPACITIVE COUPLING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
11131165
|
Filing Dt:
|
05/17/2005
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
Title:
|
METAL-DOPED ALUMINA AND LAYERS THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
11131552
|
Filing Dt:
|
05/18/2005
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
METHODS OF FORMING PLURALITIES OF CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11131553
|
Filing Dt:
|
05/18/2005
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
Title:
|
BOARD-ON-CHIP PACKAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2009
|
Application #:
|
11131575
|
Filing Dt:
|
05/18/2005
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
METHODS OF FORMING A PLURALITY OF CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
11132472
|
Filing Dt:
|
05/19/2005
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE, AND DEVICE COMPRISING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
11132502
|
Filing Dt:
|
05/19/2005
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
GRADUATED DELAY LINE FOR INCREASED CLOCK SKEW CORRECTION CIRCUIT OPERATING RANGE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11132602
|
Filing Dt:
|
05/19/2005
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
MEMORY CELL REPAIR USING FUSE PROGRAMMING METHOD IN A FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
11132979
|
Filing Dt:
|
05/19/2005
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2007
|
Application #:
|
11133061
|
Filing Dt:
|
05/19/2005
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
Title:
|
DIELECTRIC LAYER FORMING METHOD AND DEVICES FORMED THEREWITH
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2008
|
Application #:
|
11133085
|
Filing Dt:
|
05/19/2005
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
BACKSIDE METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS WITH CONDUCTIVE INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
11133236
|
Filing Dt:
|
05/20/2005
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
Title:
|
OFFSET COMPENSATED SENSING FOR MAGNETIC RANDOM ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
11133843
|
Filing Dt:
|
05/19/2005
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
METHOD AND SYSTEM FOR STRESSING SEMICONDUCTOR WAFERS DURING BURN-IN
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11134321
|
Filing Dt:
|
05/23/2005
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
Title:
|
LAYERED MAGNETIC STRUCTURES HAVING IMPROVED SURFACE PLANARITY FOR BIT MATERIAL DEPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2008
|
Application #:
|
11134982
|
Filing Dt:
|
05/23/2005
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
METHODS FOR FORMING ARRAYS OF A SMALL, CLOSELY SPACED FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
11135558
|
Filing Dt:
|
05/24/2005
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
FRAME SCALE PACKAGE USING CONTACT LINES THROUGH THE ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
11136145
|
Filing Dt:
|
05/24/2005
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
Title:
|
PROGRAMMING FLASH MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
11136152
|
Filing Dt:
|
05/24/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
VERSION BASED NON-VOLATILE MEMORY TRANSLATION LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
11136823
|
Filing Dt:
|
05/25/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
METHODS OF FORMING INTEGRATED CIRCUIT DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
11136893
|
Filing Dt:
|
05/25/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
DELAY LINE CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2008
|
Application #:
|
11137034
|
Filing Dt:
|
05/25/2005
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
Title:
|
MULTI-PART LEAD FRAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
11137393
|
Filing Dt:
|
05/26/2005
|
Publication #:
|
|
Pub Dt:
|
10/27/2005
| | | | |
Title:
|
AUTOMATIC COLOR CONSTANCY FOR IMAGE SENSORS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2010
|
Application #:
|
11137446
|
Filing Dt:
|
05/26/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
STRUCTURE AND METHOD FOR FPN REDUCTION IN IMAGING DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
11137700
|
Filing Dt:
|
05/24/2005
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR REORDERING MEMORY REQUESTS FOR PAGE COHERENCY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
|
Application #:
|
11137978
|
Filing Dt:
|
05/25/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
PSEUDO-DIFFERENTIAL OUTPUT DRIVER WITH HIGH IMMUNITY TO NOISE AND JITTER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
11138527
|
Filing Dt:
|
05/26/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
SCALABLE HIGH DENSITY NON-VOLATILE MEMORY CELLS IN A CONTACTLESS MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
11138544
|
Filing Dt:
|
05/26/2005
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
THROUGH-SUBSTRATE INTERCONNECT FABRICATION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2009
|
Application #:
|
11138575
|
Filing Dt:
|
05/26/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
MULTI-STATE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
|
Application #:
|
11138884
|
Filing Dt:
|
05/25/2005
|
Publication #:
|
|
Pub Dt:
|
12/08/2005
| | | | |
Title:
|
SYNCHRONOUS MEMORY DEVICE WITH REDUCED POWER CONSUMPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
11138910
|
Filing Dt:
|
05/27/2005
|
Publication #:
|
|
Pub Dt:
|
12/01/2005
| | | | |
Title:
|
CLOCK RECOVERY CIRCUIT AND A METHOD OF GENERATING A RECOVERED CLOCK SIGNAL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
11138920
|
Filing Dt:
|
05/26/2005
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
Title:
|
METHOD TO PREVENT DAMAGE TO PROBE CARD
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2015
|
Application #:
|
11139274
|
Filing Dt:
|
05/27/2005
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
Title:
|
MEMORY HUB AND ACCESS METHOD HAVING A SEQUENCER AND INTERNAL ROW CACHING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2009
|
Application #:
|
11140402
|
Filing Dt:
|
05/27/2005
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
METHOD OF FORMING VIAS IN SEMICONDUCTOR SUBSTRATES WITHOUT DAMAGING ACTIVE REGIONS THEREOF AND RESULTING STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2011
|
Application #:
|
11140420
|
Filing Dt:
|
05/27/2005
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
METHODS FOR PLACING SUBSTRATES IN CONTACT WITH MOLTEN SOLDER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2009
|
Application #:
|
11140422
|
Filing Dt:
|
05/27/2005
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE ASSEMBLIES AND PACKAGES INCLUDING MULTIPLE SEMICONDUCTOR DEVICE COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2009
|
Application #:
|
11140643
|
Filing Dt:
|
05/27/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
HAFNIUM TITANIUM OXIDE FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2009
|
Application #:
|
11140791
|
Filing Dt:
|
05/31/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR HIDDEN-REFRESH RATE MODIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2008
|
Application #:
|
11140859
|
Filing Dt:
|
05/31/2005
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
Title:
|
USE OF DAR COATING TO MODULATE THE EFFICIENCY OF LASER FUSE BLOWS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
11141387
|
Filing Dt:
|
06/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
ISOLATION TECHNIQUES FOR REDUCING DARK CURRENT IN CMOS IMAGE SENSORS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
11142226
|
Filing Dt:
|
06/01/2005
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
Title:
|
INTEGRATED CIRCUIT CHARACTERIZATION PRINTED CIRCUIT BOARD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2008
|
Application #:
|
11142447
|
Filing Dt:
|
06/02/2005
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
Title:
|
STACKED COLUMNAR 1T-NMTJ MRAM STRUCTURE AND ITS METHOD OF FORMATION AND OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
11142448
|
Filing Dt:
|
06/02/2005
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
Title:
|
STACKED COLUMNAR 1T-NMTJ MRAM STRUCTURE AND ITS METHOD OF FORMATION AND OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
11142578
|
Filing Dt:
|
06/01/2005
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
Title:
|
THIN FLIP-CHIP METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
11142946
|
Filing Dt:
|
06/01/2005
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
DELAY-LOCK LOOP AND METHOD ADAPTING ITSELF TO OPERATE OVER A WIDE FREQUENCY RANGE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
|
Application #:
|
11144543
|
Filing Dt:
|
06/02/2005
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
MULTIPLE SPACER STEPS FOR PITCH MULTIPLICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
11145624
|
Filing Dt:
|
06/06/2005
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
METHOD OF MANUFACTURING DEVICES COMPRISING CONDUCTIVE NANO-DOTS, AND DEVICES COMPRISING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
11145632
|
Filing Dt:
|
06/06/2005
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
Title:
|
USE OF PALLADIUM IN IC MANUFACTURING WITH CONDUCTIVE POLYMER BUMP
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
11146090
|
Filing Dt:
|
06/07/2005
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
IMAGER METHOD AND APPARATUS EMPLOYING PHOTONIC CRYSTALS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
11146091
|
Filing Dt:
|
06/07/2005
|
Publication #:
|
|
Pub Dt:
|
01/19/2006
| | | | |
Title:
|
MEMORY DEVICE WITH SWITCHING GLASS LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
11146248
|
Filing Dt:
|
06/06/2005
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
METHODS FOR POSITIONING CARBON NANOTUBES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
11146397
|
Filing Dt:
|
06/07/2005
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
Title:
|
METHOD FOR FABRICATING ENCAPSULATED SEMICONDUCTOR COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
11146482
|
Filing Dt:
|
06/06/2005
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
Title:
|
MAGNETO-RESISTIVE MEMORY CELL STRUCTURES WITH IMPROVED SELECTIVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2008
|
Application #:
|
11146648
|
Filing Dt:
|
06/07/2005
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
METHODS OF ETCHING NICKEL SILICIDE AND COBALT SILICIDE AND METHODS OF FORMING CONDUCTIVE LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
11146852
|
Filing Dt:
|
06/07/2005
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
DYNAMIC WELL BIAS CONTROLLED BY VT DETECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2008
|
Application #:
|
11146997
|
Filing Dt:
|
06/06/2005
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
SPINTRONIC DEVICES WITH INTEGRATED TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2009
|
Application #:
|
11148028
|
Filing Dt:
|
06/08/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
ROBUST INDEX STORAGE FOR NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
11148396
|
Filing Dt:
|
06/07/2005
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
Title:
|
METHOD FOR FORMING MAGNETO-RESISTIVE MEMORY CELLS WITH SHAPE ANISOTROPY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
11148505
|
Filing Dt:
|
06/09/2005
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
Title:
|
ATOMIC LAYER DEPOSITED NANOLAMINATES OF HFO2/ZRO2 FILMS AS GATE DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
11148554
|
Filing Dt:
|
06/09/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
REDUCED IMAGER CROSSTALK AND PIXEL NOISE USING EXTENDED BURIED CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2009
|
Application #:
|
11148853
|
Filing Dt:
|
06/08/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
CAPACITORLESS DRAM ON BULK SILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11149578
|
Filing Dt:
|
06/09/2005
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
METHODS OF FORMING CONDUCTIVE INTERCONNECTS, AND METHODS OF DEPOSITING NICKEL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11149948
|
Filing Dt:
|
06/09/2005
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
DATA CONTROL UNIT CAPABLE OF CORRECTING BOOT ERRORS, AND CORRESPONDING SELF-CORRECTION METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
11150752
|
Filing Dt:
|
06/10/2005
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
Title:
|
METHOD IN AN INTEGRATED CIRCUIT (IC) MANUFACTURING PROCESS FOR IDENTIFYING AND REDIRECTING ICS MIS-PROCESSED DURING THEIR MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2010
|
Application #:
|
11151219
|
Filing Dt:
|
06/13/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
VERTICAL TRANSISTOR, MEMORY CELL, DEVICE, SYSTEM AND METHOD OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
11151568
|
Filing Dt:
|
06/13/2005
|
Publication #:
|
|
Pub Dt:
|
02/09/2006
| | | | |
Title:
|
PROGRAMMING AND EVALUATING THROUGH PMOS INJECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11151925
|
Filing Dt:
|
06/14/2005
|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
Title:
|
COMPLIANT CONTACT PIN ASSEMBLY AND CARD SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
11151952
|
Filing Dt:
|
06/14/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
LOW POWER NROM MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
11152325
|
Filing Dt:
|
06/14/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
DLL MEASURE INITIALIZATION CIRCUIT FOR HIGH FREQUENCY OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11152513
|
Filing Dt:
|
06/14/2005
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
Title:
|
CONTACT PIN ASSEMBLY AND CONTACTOR CARD
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
11152644
|
Filing Dt:
|
06/14/2005
|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
Title:
|
MEMORY DEVICE INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2009
|
Application #:
|
11152759
|
Filing Dt:
|
06/14/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
IRIDIUM / ZIRCONIUM OXIDE STRUCTURE
|
|