|
|
Patent #:
|
|
Issue Dt:
|
12/01/2015
|
Application #:
|
13648292
|
Filing Dt:
|
10/10/2012
|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
Title:
|
CHIP AUTHENTICATION USING MULTI-DOMAIN INTRINSIC IDENTIFIERS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13648321
|
Filing Dt:
|
10/10/2012
|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
Title:
|
SINGLE FIN CUT EMPLOYING ANGLED PROCESSING METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13648433
|
Filing Dt:
|
10/10/2012
|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A SELF-FORMING BARRIER LAYER AT VIA BOTTOM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
13648504
|
Filing Dt:
|
10/10/2012
|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
Title:
|
METHODS OF FORMING A CAPACITOR AND CONTACT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
13648555
|
Filing Dt:
|
10/10/2012
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
COLLECTING FAILURE INFORMATION ON ERROR CORRECTION CODE (ECC) PROTECTED DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
13649284
|
Filing Dt:
|
10/11/2012
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
Title:
|
FINFET WITH VERTICAL SILICIDE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2017
|
Application #:
|
13649699
|
Filing Dt:
|
10/11/2012
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
METHODOLOGY OF GRADING RELIABILITY AND PERFORMANCE OF CHIPS ACROSS WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13649760
|
Filing Dt:
|
10/11/2012
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
THERMAL EXPANSION CONTROL EMPLOYING PLATELET FILLERS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
13649769
|
Filing Dt:
|
10/11/2012
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
MULTI-FINGER TRANSISTOR LAYOUT FOR REDUCING CROSS-FINGER ELECTRIC VARIATIONS AND FOR FULLY UTILIZING AVAILABLE BREAKDOWN VOLTAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
13650176
|
Filing Dt:
|
10/12/2012
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
VERTICAL SOURCE/DRAIN JUNCTIONS FOR A FINFET INCLUDING A PLURALITY OF FINS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13650233
|
Filing Dt:
|
10/12/2012
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
ADVANCED FARADAY SHIELD FOR A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13651874
|
Filing Dt:
|
10/15/2012
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
13651918
|
Filing Dt:
|
10/15/2012
|
Publication #:
|
|
Pub Dt:
|
02/14/2013
| | | | |
Title:
|
SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX)
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
13651974
|
Filing Dt:
|
10/15/2012
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
Method and System for Wafer Quality Predictive Modeling based on Multi-Source Information with Heterogeneous Relatedness
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
13652521
|
Filing Dt:
|
10/16/2012
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
EMBEDDED SOURCE/DRAINS WITH EPITAXIAL OXIDE UNDERLAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13652623
|
Filing Dt:
|
10/16/2012
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
Method Of Fabricating MEMS Transistors On Far Back End Of Line
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
13652804
|
Filing Dt:
|
10/16/2012
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
NANOPILLAR E-FUSE STRUCTURE AND PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13653291
|
Filing Dt:
|
10/16/2012
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
BLOCK-INTERLEAVED AND ERROR CORRECTION CODE (ECC)-ENCODED SUB DATA SET (SDS) FORMAT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13653606
|
Filing Dt:
|
10/17/2012
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
DIRECTED SELF-ASSEMBLY OF BLOCK COPOLYMERS USING LASER ANNEALING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13653665
|
Filing Dt:
|
10/17/2012
|
Publication #:
|
|
Pub Dt:
|
05/09/2013
| | | | |
Title:
|
METAL ALLOY CAP INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13653679
|
Filing Dt:
|
10/17/2012
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR DEVICE HAVING A HYBRID METAL GATE STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13653996
|
Filing Dt:
|
10/17/2012
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
REACTIVE MATERIAL FOR INTEGRATED CIRCUIT TAMPER DETECTION AND RESPONSE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
13654040
|
Filing Dt:
|
10/17/2012
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
MULTI-DOPED SILICON ANTIFUSE DEVICE FOR INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13654717
|
Filing Dt:
|
10/18/2012
|
Publication #:
|
|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
FACILITATING GATE HEIGHT UNIFORMITY AND INTER-LAYER DIELECTRIC PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
13654849
|
Filing Dt:
|
10/18/2012
|
Publication #:
|
|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
METHODS OF REDUCING MATERIAL LOSS IN ISOLATION STRUCTURES BY INTRODUCING INERT ATOMS INTO OXIDE HARD MASK LAYER USED IN GROWING CHANNEL SEMICONDUCTOR MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13654987
|
Filing Dt:
|
10/18/2012
|
Publication #:
|
|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
STRUCTURE AND METHOD FOR FORMING A LOW GATE RESISTANCE HIGH-K METAL GATE TRANSISTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2015
|
Application #:
|
13655003
|
Filing Dt:
|
10/18/2012
|
Publication #:
|
|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
SRAM GLOBAL PRECHARGE, DISCHARGE, AND SENSE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13655426
|
Filing Dt:
|
10/18/2012
|
Title:
|
FORMING AN ARRAY OF METAL BALLS OR SHAPES ON A SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13655520
|
Filing Dt:
|
10/19/2012
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
USER-COORDINATED RESOURCE RECOVERY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
13655599
|
Filing Dt:
|
10/19/2012
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
REDUCTION OF PORE FILL MATERIAL DEWETTING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13655844
|
Filing Dt:
|
10/19/2012
|
Publication #:
|
|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A WET ETCH PROCESS FOR REMOVING SILICON NITRIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13655980
|
Filing Dt:
|
10/19/2012
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
VISUALIZATION INTERFACE OF CONTINUOUS WAVEFORM MULTI-SPEAKER IDENTIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13656396
|
Filing Dt:
|
10/19/2012
|
Publication #:
|
|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
METHOD AND SYSTEM FOR PERFORMING INVARIANT-GUIDED ABSTRACTION OF A LOGIC DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13656794
|
Filing Dt:
|
10/22/2012
|
Publication #:
|
|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH LOW-K SPACERS AND THE RESULTING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13656819
|
Filing Dt:
|
10/22/2012
|
Publication #:
|
|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR HAVING PHASE TRANSITION MATERIAL INCORPORATED INTO ONE OR MORE COMPONENTS FOR REDUCED LEAKAGE CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13656829
|
Filing Dt:
|
10/22/2012
|
Publication #:
|
|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
MEMORY SYSTEM INCORPORATING A CIRCUIT TO GENERATE A DELAY SIGNAL AND AN ASSOCIATED METHOD OF OPERATING A MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
13657058
|
Filing Dt:
|
10/22/2012
|
Publication #:
|
|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
MEMORY SYSTEM CONNECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13657182
|
Filing Dt:
|
10/22/2012
|
Title:
|
SUBTRACTIVE METAL MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
13658148
|
Filing Dt:
|
10/23/2012
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
CHANNEL MARKING FOR CHIP MARK OVERFLOW AND CALIBRATION ERRORS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13658226
|
Filing Dt:
|
10/23/2012
|
Publication #:
|
|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
IMPLEMENTING SDRAM HAVING NO RAS TO CAS DELAY IN WRITE OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13658861
|
Filing Dt:
|
10/24/2012
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
SERIAL IRRADIATION OF A SUBSTRATE BY MULTIPLE RADIATION SOURCES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13659236
|
Filing Dt:
|
10/24/2012
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
Polarization Monitoring Reticle Design for High Numerical Aperture Lithography Systems
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
13659318
|
Filing Dt:
|
10/24/2012
|
Publication #:
|
|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
13659453
|
Filing Dt:
|
10/24/2012
|
Title:
|
METHODS FOR DIRECTED SELF-ASSEMBLY PROCESS/PROXIMITY CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13660604
|
Filing Dt:
|
10/25/2012
|
Publication #:
|
|
Pub Dt:
|
03/27/2014
| | | | |
Title:
|
TRANSPARENT CONDUCTIVE ELECTRODE STACK CONTAINING CARBON-CONTAINING MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13661062
|
Filing Dt:
|
10/26/2012
|
Publication #:
|
|
Pub Dt:
|
05/01/2014
| | | | |
Title:
|
PROGRAMMABLE DUTY CYCLE SETTER EMPLOYING TIME TO VOLTAGE DOMAIN REFERENCED PULSE CREATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13661188
|
Filing Dt:
|
10/26/2012
|
Publication #:
|
|
Pub Dt:
|
05/01/2014
| | | | |
Title:
|
PERFORMANCE ENHANCEMENT IN TRANSISTORS BY PROVIDING A GRADED EMBEDDED STRAIN-INDUCING SEMICONDUCTOR REGION WITH ADAPTED ANGLES WITH RESPECT TO THE SUBSTRATE SURFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2014
|
Application #:
|
13661359
|
Filing Dt:
|
10/26/2012
|
Publication #:
|
|
Pub Dt:
|
05/01/2014
| | | | |
Title:
|
ISOLATION SCHEME FOR BIPOLAR TRANSISTORS IN BICMOS TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2015
|
Application #:
|
13661683
|
Filing Dt:
|
10/26/2012
|
Publication #:
|
|
Pub Dt:
|
05/01/2014
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING ESD PROTECTION DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13663589
|
Filing Dt:
|
10/30/2012
|
Publication #:
|
|
Pub Dt:
|
05/09/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH REDUCED THRESHOLD VARIABILITY HAVING A THRESHOLD ADJUSTING SEMICONDUCTOR ALLOY IN THE DEVICE ACTIVE REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13663768
|
Filing Dt:
|
10/30/2012
|
Publication #:
|
|
Pub Dt:
|
05/01/2014
| | | | |
Title:
|
FEED-FORWARD EQUALIZATION IN A RECEIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13663811
|
Filing Dt:
|
10/30/2012
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
Title:
|
PROTECTING A THERMAL SENSITIVE COMPONENT IN A THERMAL PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
13663816
|
Filing Dt:
|
10/30/2012
|
Publication #:
|
|
Pub Dt:
|
05/01/2014
| | | | |
Title:
|
AUTOMATIC WAFER DATA SAMPLE PLANNING AND REVIEW
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
13663836
|
Filing Dt:
|
10/30/2012
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
METHODS OF FORMING STRUCTURES WITH A FOCUSED ION BEAM FOR USE IN ATOMIC FORCE PROBING AND STRUCTURES FOR USE IN ATOMIC FORCE PROBING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2016
|
Application #:
|
13663854
|
Filing Dt:
|
10/30/2012
|
Publication #:
|
|
Pub Dt:
|
05/01/2014
| | | | |
Title:
|
METHODS OF FORMING ENHANCED MOBILITY CHANNEL REGIONS ON 3D SEMICONDUCTOR DEVICES, AND DEVICES COMPRISING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
|
Application #:
|
13664062
|
Filing Dt:
|
10/30/2012
|
Publication #:
|
|
Pub Dt:
|
05/01/2014
| | | | |
Title:
|
FIN ETCH AND FIN REPLACEMENT FOR FINFET INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13664744
|
Filing Dt:
|
10/31/2012
|
Publication #:
|
|
Pub Dt:
|
05/01/2014
| | | | |
Title:
|
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING REPLACEMENT METAL GATE PROCESS INCORPORATING A CONDUCTIVE DUMMY GATE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13664784
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
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Title:
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SEMICONDUCTOR STRUCTURE INCORPORATING A CONTACT SIDEWALL SPACER WITH A SELF-ALIGNED AIRGAP AND A METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13664812
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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COMPENSATING FOR WARPAGE OF A FLIP CHIP PACKAGE BY VARYING HEIGHTS OF A REDISTRIBUTION LAYER ON AN INTEGRATED CIRCUIT CHIP
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Patent #:
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Issue Dt:
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04/07/2015
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Application #:
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13664850
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
|
05/01/2014
| | | | |
Title:
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LOCAL INTERCONNECTS FOR FIELD EFFECT TRANSISTOR DEVICES
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Patent #:
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Issue Dt:
|
01/06/2015
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Application #:
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13664869
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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SELF-ALIGNED CONTACT STRUCTURE FOR REPLACEMENT METAL GATE
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Patent #:
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Issue Dt:
|
07/14/2015
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Application #:
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13664873
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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BULK FINFET WITH PUNCHTHROUGH STOPPER REGION AND METHOD OF FABRICATION
|
|
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Patent #:
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Issue Dt:
|
06/16/2015
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Application #:
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13665140
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS
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|
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Patent #:
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Issue Dt:
|
09/30/2014
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Application #:
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13665276
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
|
05/01/2014
| | | | |
Title:
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HIERARCHICAL DESIGN OF INTEGRATED CIRCUITS WITH MULTI-PATTERNING REQUIREMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
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Application #:
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13665315
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
|
05/01/2014
| | | | |
Title:
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PARASITIC EXTRACTION IN AN INTEGRATED CIRCUIT WITH MULTI-PATTERNING REQUIREMENTS
|
|
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Patent #:
|
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Issue Dt:
|
12/24/2013
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Application #:
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13665334
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Filing Dt:
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10/31/2012
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Title:
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Techniques for Fabricating Janus MEMS Transistors
|
|
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Patent #:
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Issue Dt:
|
05/13/2014
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Application #:
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13666031
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Filing Dt:
|
11/01/2012
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Publication #:
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|
Pub Dt:
|
05/01/2014
| | | | |
Title:
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DUAL GATE FINFET DEVICES
|
|
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Patent #:
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|
Issue Dt:
|
03/24/2015
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Application #:
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13666214
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Filing Dt:
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11/01/2012
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Publication #:
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Pub Dt:
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03/07/2013
| | | | |
Title:
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TRANSISTORS HAVING STRESSED CHANNEL REGIONS AND METHODS OF FORMING TRANSISTORS HAVING STRESSED CHANNEL REGIONS
|
|
|
Patent #:
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|
Issue Dt:
|
01/14/2014
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Application #:
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13666484
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Filing Dt:
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11/01/2012
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Publication #:
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Pub Dt:
|
03/07/2013
| | | | |
Title:
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IMPLEMENTING ENHANCED CLOCK TREE DISTRIBUTIONS TO DECOUPLE ACROSS N-LEVEL HIERARCHICAL ENTITIES
|
|
|
Patent #:
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Issue Dt:
|
08/11/2015
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Application #:
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13667384
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Filing Dt:
|
11/02/2012
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Publication #:
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Pub Dt:
|
05/08/2014
| | | | |
Title:
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FABRICATION OF LOCALIZED SOI ON LOCALIZED THICK BOX USING SELECTIVE EPITAXY ON BULK SEMICONDUCTOR SUBSTRATES FOR PHOTONICS DEVICE INTEGRATION
|
|
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Patent #:
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|
Issue Dt:
|
01/12/2016
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Application #:
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13667389
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Filing Dt:
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11/02/2012
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Publication #:
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Pub Dt:
|
05/08/2014
| | | | |
Title:
|
FABRICATION OF LOCALIZED SOI ON LOCALIZED THICK BOX LATERAL EPITAXIAL REALIGNMENT OF DEPOSITED NON-CRYSTALLINE FILM ON BULK SEMICONDUCTOR SUBSTRATES FOR PHOTONICS DEVICE INTEGRATION
|
|
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Patent #:
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Issue Dt:
|
03/18/2014
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Application #:
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13667657
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Filing Dt:
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11/02/2012
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Publication #:
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Pub Dt:
|
03/07/2013
| | | | |
Title:
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COMPLEMENTARY STRESS LINER TO IMPROVE DGO/AVT DEVICES AND POLY AND DIFFUSION RESISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13668401
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Filing Dt:
|
11/05/2012
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Publication #:
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Pub Dt:
|
12/12/2013
| | | | |
Title:
|
SIDE-GATE DEFINED TUNABLE NANOCONSTRICTION IN DOUBLE-GATED GRAPHENE MULTILAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13668869
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Filing Dt:
|
11/05/2012
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Publication #:
|
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Pub Dt:
|
05/08/2014
| | | | |
Title:
|
MAGNETORESISTIVE RANDOM ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
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13669627
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Filing Dt:
|
11/06/2012
|
Publication #:
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|
Pub Dt:
|
05/08/2014
| | | | |
Title:
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CLEANING COMPOSITION AND PROCESS FOR CLEANING SEMICONDUCTOR DEVICES AND/OR TOOLING DURING MANUFACTURING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2014
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Application #:
|
13669651
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Filing Dt:
|
11/06/2012
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Title:
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PROCESS FOR CLEANING SEMICONDUCTOR DEVICES AND/OR TOOLING DURING MANUFACTURING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2015
|
Application #:
|
13669891
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Filing Dt:
|
11/06/2012
|
Publication #:
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|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
MAPPING DENSITY AND TEMPERATURE OF A CHIP, IN SITU
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2016
|
Application #:
|
13670251
|
Filing Dt:
|
11/06/2012
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Publication #:
|
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Pub Dt:
|
05/08/2014
| | | | |
Title:
|
METAL GATE STRUCTURE FOR MIDGAP SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
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Application #:
|
13670566
|
Filing Dt:
|
11/07/2012
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
FABRICATION OF REVERSE SHALLOW TRENCH ISOLATION STRUCTURES WITH SUPER-STEEP RETROGRADE WELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13670605
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Filing Dt:
|
11/07/2012
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Title:
|
METHODS OF FORMING FINS AND ISOLATION REGIONS ON A FINFET SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13670674
|
Filing Dt:
|
11/07/2012
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Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13670694
|
Filing Dt:
|
11/07/2012
|
Publication #:
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|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
ENHANCED CAPTURE PADS FOR THROUGH SEMICONDUCTOR VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13670711
|
Filing Dt:
|
11/07/2012
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
COPPER INTERCONNECT STRUCTURES AND METHODS OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13670748
|
Filing Dt:
|
11/07/2012
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
ROBUST REPLACEMENT GATE INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13670768
|
Filing Dt:
|
11/07/2012
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
METHOD AND STRUCTURE FOR FORMING A LOCALIZED SOI FINFET
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13670880
|
Filing Dt:
|
11/07/2012
|
Title:
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FINFET ALIGNMENT STRUCTURES USING A DOUBLE TRENCH FLOW
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13670921
|
Filing Dt:
|
11/07/2012
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Title:
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SELF-FORMATION OF HIGH-DENSITY DEFECT-FREE AND ALIGNED NANOSTRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13671098
|
Filing Dt:
|
11/07/2012
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Title:
|
WAFER-TO-WAFER PROCESS FOR MANUFACTURING A STACKED STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13671186
|
Filing Dt:
|
11/07/2012
|
Title:
|
SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
13671226
|
Filing Dt:
|
11/07/2012
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
METHOD FOR SELECTIVELY MODELING NARROW-WIDTH STACKED DEVICE PERFORMANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
13671605
|
Filing Dt:
|
11/08/2012
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
13671776
|
Filing Dt:
|
11/08/2012
|
Publication #:
|
|
Pub Dt:
|
05/01/2014
| | | | |
Title:
|
Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13671940
|
Filing Dt:
|
11/08/2012
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13672040
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Filing Dt:
|
11/08/2012
|
Publication #:
|
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Pub Dt:
|
03/14/2013
| | | | |
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE RESISTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2016
|
Application #:
|
13672751
|
Filing Dt:
|
11/09/2012
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Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
Title:
|
MEMORY MODULE AND MEMORY CONTROLLER FOR CONTROLLING A MEMORY MODULE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13672770
|
Filing Dt:
|
11/09/2012
|
Publication #:
|
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Pub Dt:
|
05/15/2014
| | | | |
Title:
|
PROACTIVE RISK ANALYSIS AND GOVERNANCE OF UPGRADE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2015
|
Application #:
|
13672925
|
Filing Dt:
|
11/09/2012
|
Publication #:
|
|
Pub Dt:
|
05/01/2014
| | | | |
Title:
|
DUAL GATE FINFET DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2016
|
Application #:
|
13673262
|
Filing Dt:
|
11/09/2012
|
Publication #:
|
|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
MEMORY ARCHITECTURES HAVING WIRING STRUCTURES THAT ENABLE DIFFERENT ACCESS PATTERNS IN MULTIPLE DIMENSIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2015
|
Application #:
|
13673549
|
Filing Dt:
|
11/09/2012
|
Publication #:
|
|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
INTEGRATED CIRCUITS AND METHODS OF FORMING INTEGRATED CIRCUITS WITH INTERLAYER DIELECTRIC PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13674142
|
Filing Dt:
|
11/12/2012
|
Publication #:
|
|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
METHODS OF MANUFACTURING INTEGRATED CIRCUITS HAVING FINFET STRUCTURES WITH EPITAXIALLY FORMED SOURCE/DRAIN REGIONS
|
|