|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
11342425
|
Filing Dt:
|
01/30/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
DYNAMICALLY ADAPTABLE SEMICONDUCTOR PARAMETRIC TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2007
|
Application #:
|
11343502
|
Filing Dt:
|
01/30/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
PLANARITY DIAGNOSTIC SYSTEM, E.G., FOR MICROELECTRONIC COMPONENT TEST SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
11343517
|
Filing Dt:
|
01/30/2006
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
REDUCTION OF FUSIBLE LINKS AND ASSOCIATED CIRCUITRY ON MEMORY DIES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
11343525
|
Filing Dt:
|
01/30/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
REDUCTION OF FUSIBLE LINKS AND ASSOCIATED CIRCUITRY ON MEMORY DIES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
11343526
|
Filing Dt:
|
01/30/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
REDUCTION OF FUSIBLE LINKS AND ASSOCIATED CIRCUITRY ON MEMORY DIES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
11343527
|
Filing Dt:
|
01/30/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
REDUCTION OF FUSIBLE LINKS AND ASSOCIATED CIRCUITRY ON MEMORY DIES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2009
|
Application #:
|
11343593
|
Filing Dt:
|
01/30/2006
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
PROCESS FOR MANUFACTURING INTEGRATED RESISTIVE ELEMENTS WITH SILICIDATION PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
11343818
|
Filing Dt:
|
01/31/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
PIPELINED BURST MEMORY ACCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2010
|
Application #:
|
11344519
|
Filing Dt:
|
01/31/2006
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
Title:
|
REMOVABLE DATA STORAGE DEVICE AND RELATED ASSEMBLING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
11344988
|
Filing Dt:
|
01/31/2006
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
DELAY-LOCKED LOOP HAVING A PRE-SHIFT PHASE DETECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
11345080
|
Filing Dt:
|
02/01/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
BALLISTIC INJECTION NROM FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
11345552
|
Filing Dt:
|
01/31/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
DELAY-LOCKED LOOP HAVING A PRE-SHIFT PHASE DETECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
11345982
|
Filing Dt:
|
02/02/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
11346049
|
Filing Dt:
|
02/02/2006
|
Publication #:
|
|
Pub Dt:
|
03/19/2009
| | | | |
Title:
|
NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
11346063
|
Filing Dt:
|
02/02/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
11346131
|
Filing Dt:
|
02/02/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2006
|
Application #:
|
11346386
|
Filing Dt:
|
02/03/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
MEMORY ARCHITECTURE AND METHOD OF MANUFACTURE AND OPERATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2009
|
Application #:
|
11346413
|
Filing Dt:
|
02/02/2006
|
Publication #:
|
|
Pub Dt:
|
01/08/2009
| | | | |
Title:
|
NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
11346421
|
Filing Dt:
|
02/02/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
11346870
|
Filing Dt:
|
02/02/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
MANUFACTURING METHOD FOR A MOS TRANSISTOR COMPRISING LAYERED RELAXED AND STRAINED SIGE LAYERS AS A CHANNEL REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
11346914
|
Filing Dt:
|
02/02/2006
|
Publication #:
|
|
Pub Dt:
|
08/02/2007
| | | | |
Title:
|
METHODS OF FORMING FIELD EFFECT TRANSISTORS, METHODS OF FORMING FIELD EFFECT TRANSISTOR GATES, METHODS OF FORMING INTEGRATED CIRCUITRY COMPRISING A TRANSISTOR GATE ARRAY AND CIRCUITRY PERIPHERAL TO THE GATE ARRAY, AND METHODS OF FORMING INTEGRATED CIRCUITRY COMPRIS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
11346963
|
Filing Dt:
|
02/03/2006
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
11346985
|
Filing Dt:
|
02/02/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
SEMICONDUCTOR CIRCUITRY CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
11347051
|
Filing Dt:
|
02/03/2006
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
AGGLOMERATION CONTROL USING EARLY TRANSITION METAL ALLOYS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
11347153
|
Filing Dt:
|
02/03/2006
|
Publication #:
|
|
Pub Dt:
|
08/09/2007
| | | | |
Title:
|
METHODS FOR FABRICATING AND FILLING CONDUCTIVE VIAS AND CONDUCTIVE VIAS SO FORMED
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2008
|
Application #:
|
11347477
|
Filing Dt:
|
02/03/2006
|
Publication #:
|
|
Pub Dt:
|
08/09/2007
| | | | |
Title:
|
INPUT BUFFER WITH OPTIMAL BIASING AND METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2009
|
Application #:
|
11347858
|
Filing Dt:
|
02/06/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
METHODS AND APPARATUSES FOR SHAPING A PRINTED CIRCUIT BOARD
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
11347863
|
Filing Dt:
|
02/06/2006
|
Publication #:
|
|
Pub Dt:
|
08/09/2007
| | | | |
Title:
|
MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2008
|
Application #:
|
11347930
|
Filing Dt:
|
02/06/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS WITH CONDUCTIVE SPRING CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
11347961
|
Filing Dt:
|
02/06/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
APPARATUS WITH EQUALIZING VOLTAGE GENERATION CIRCUIT AND METHODS OF USE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
11348513
|
Filing Dt:
|
02/06/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
METHOD FOR PROGRAMMING A MEMORY DEVICE SUITABLE TO MINIMIZE THE LATERAL COUPLING EFFECTS BETWEEN MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2009
|
Application #:
|
11348571
|
Filing Dt:
|
02/06/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS OF FORMING MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
11348678
|
Filing Dt:
|
02/07/2006
|
Publication #:
|
|
Pub Dt:
|
08/09/2007
| | | | |
Title:
|
ERASE OPERATION IN A FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
11348724
|
Filing Dt:
|
02/06/2006
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
INCREASING THE MEMORY PERFORMANCE OF FLASH MEMORY DEVICES BY WRITING SECTORS SIMULTANEOUSLY TO MULTIPLE FLASH MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2008
|
Application #:
|
11349397
|
Filing Dt:
|
02/06/2006
|
Publication #:
|
|
Pub Dt:
|
08/09/2007
| | | | |
Title:
|
DELAY LINE CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
11349801
|
Filing Dt:
|
02/08/2006
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
MULTIPHASE CLOCK GENERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2009
|
Application #:
|
11349854
|
Filing Dt:
|
02/08/2006
|
Publication #:
|
|
Pub Dt:
|
08/09/2007
| | | | |
Title:
|
MEMORY ARRAY SEGMENTATION AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11349959
|
Filing Dt:
|
02/09/2006
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
Title:
|
PHASE CHANGE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
11350061
|
Filing Dt:
|
02/08/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
METHODS OF FORMING TRANSISTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
11350961
|
Filing Dt:
|
02/08/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
MEMORY SUBSYSTEM VOLTAGE CONTROL AND METHOD THAT REPROGRAMS A PREFERRED OPERATING VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
11351006
|
Filing Dt:
|
02/08/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
METHODS OF MANUFACTURE OF A VIA STRUCTURE COMPRISING A PLURALITY OF CONDUCTIVE ELEMENTS AND METHODS OF FORMING MULTICHIP MODULES INCLUDING SUCH VIA STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
11351008
|
Filing Dt:
|
02/08/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
OPERATIONAL VOLTAGE CONTROL CIRCUIT AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2010
|
Application #:
|
11351009
|
Filing Dt:
|
02/08/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
INTERPOSER INCLUDING AT LEAST ONE PASSIVE ELEMENT AT LEAST PARTIALLY DEFINED BY A RECESS FORMED THEREIN, SYSTEM INCLUDING SAME, AND WAFER-SCALE INTERPOSER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
11351037
|
Filing Dt:
|
02/08/2006
|
Publication #:
|
|
Pub Dt:
|
08/09/2007
| | | | |
Title:
|
TEMPERATURE COMPENSATION VIA POWER SUPPLY MODIFICATION TO PRODUCE A TEMPERATURE-INDEPENDENT DELAY IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
11351277
|
Filing Dt:
|
02/08/2006
|
Publication #:
|
|
Pub Dt:
|
08/31/2006
| | | | |
Title:
|
DUTY CYCLE DISTORTION COMPENSATION FOR THE DATA OUTPUT OF A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2011
|
Application #:
|
11351640
|
Filing Dt:
|
02/10/2006
|
Publication #:
|
|
Pub Dt:
|
08/16/2007
| | | | |
Title:
|
METHODS FOR CAUSING FLUID TO FLOW THROUGH OR INTO VIA HOLES, VENTS, AND OTHER OPENINGS OR RECESSES THAT COMMUNICATE WITH SURFACES OF SUBSTRATES OF SEMICONDUCTOR DEVICE COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
11351836
|
Filing Dt:
|
02/10/2006
|
Publication #:
|
|
Pub Dt:
|
06/22/2006
| | | | |
Title:
|
MEMORY SYSTEM AND METHOD FOR STROBING DATA, COMMAND AND ADDRESS SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
11351934
|
Filing Dt:
|
02/09/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
A HOST COMPUTER USING BASIC INPUT AND OUTPUT SYSTEM TO PROCESS CONTROL COMMAND RECEIVED FROM A REMOTE COMPUTER ACCORDING TO TIMER INTERRUPTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
11351991
|
Filing Dt:
|
02/09/2006
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
A SYSTEM PROCESSING DATA PACKETS RECEIVED FROM REMOTE HOST TO CONTROL SYSTEM OPERATION ACCORDING TO ADJUSTABLE TIMER INTERRUPTS BASED ON DATA FLOW RATE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
11352078
|
Filing Dt:
|
02/10/2006
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
MEMORY SYSTEM AND METHOD FOR STROBING DATA, COMMAND AND ADDRESS SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
11352131
|
Filing Dt:
|
02/10/2006
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
MEMORY SYSTEM AND METHOD FOR STROBING DATA, COMMAND AND ADDRESS SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2007
|
Application #:
|
11352142
|
Filing Dt:
|
02/10/2006
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
MEMORY SYSTEM AND METHOD FOR STROBING DATA, COMMAND AND ADDRESS SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
11353406
|
Filing Dt:
|
02/14/2006
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
METHOD OF FORMING CELLULAR MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
11353592
|
Filing Dt:
|
02/14/2006
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
METHODS OF FORMING CMOS CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
11354126
|
Filing Dt:
|
02/15/2006
|
Publication #:
|
|
Pub Dt:
|
08/16/2007
| | | | |
Title:
|
METHOD AND APPARATUS OF DETERMINING THE BEST FOCUS POSITION OF A LENS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2009
|
Application #:
|
11354786
|
Filing Dt:
|
02/14/2006
|
Publication #:
|
|
Pub Dt:
|
06/22/2006
| | | | |
Title:
|
DETECTION CIRCUIT FOR MIXED ASYNCHRONOUS AND SYNCHRONOUS MEMORY OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
11355490
|
Filing Dt:
|
02/16/2006
|
Publication #:
|
|
Pub Dt:
|
08/16/2007
| | | | |
Title:
|
CONDUCTIVE LAYERS FOR HAFNIUM SILICON OXYNITRIDE FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
11355802
|
Filing Dt:
|
02/16/2006
|
Publication #:
|
|
Pub Dt:
|
08/16/2007
| | | | |
Title:
|
WRITE LATENCY TRACKING USING A DELAY LOCK LOOP IN A SYNCHRONOUS DRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2008
|
Application #:
|
11355830
|
Filing Dt:
|
02/16/2006
|
Publication #:
|
|
Pub Dt:
|
08/16/2007
| | | | |
Title:
|
PROGRAMMING METHOD TO REDUCE GATE COUPLING INTERFERENCE FOR NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2009
|
Application #:
|
11356335
|
Filing Dt:
|
02/16/2006
|
Publication #:
|
|
Pub Dt:
|
08/16/2007
| | | | |
Title:
|
LOCALIZED COMPRESSIVE STRAINED SEMICONDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
11356910
|
Filing Dt:
|
02/17/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
REFERENCE CIRCUIT WITH START-UP CONTROL,GENERATOR,DEVICE,SYSTEM AND METHOD INCLUDIND SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11358089
|
Filing Dt:
|
02/21/2006
|
Publication #:
|
|
Pub Dt:
|
08/02/2007
| | | | |
Title:
|
LOW VOLTAGE DATA PATH AND CURRENT SENSE AMPLIFIER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
11358234
|
Filing Dt:
|
02/21/2006
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
ISOLATION DEVICE OVER FIELD IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
11358235
|
Filing Dt:
|
02/21/2006
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
VARIABLE IMPEDENCE OUTPUT BUFFER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
11358265
|
Filing Dt:
|
02/21/2006
|
Publication #:
|
|
Pub Dt:
|
09/06/2007
| | | | |
Title:
|
DVI LINK WITH CIRCUIT AND METHOD FOR TEST
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11358266
|
Filing Dt:
|
02/21/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
LOOP FILTERING FOR FAST PLL LOCKING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
11358268
|
Filing Dt:
|
02/21/2006
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
INTEGRATED CIRCUIT DEVICE HAVING REDUCED BOW AND METHOD FOR MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
11358583
|
Filing Dt:
|
02/21/2006
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
METHOD AND APPARATUS ON (110) SURFACES OF SILICON STRUCTURES WITH CONDUCTION IN THE <110> DIRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11358647
|
Filing Dt:
|
02/21/2006
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
CAPACITOR STRUCTURES WITH OXYNITRIDE LAYER BETWEEN CAPACITOR PLATE AND CAPACITOR DIELECTRIC LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2009
|
Application #:
|
11358659
|
Filing Dt:
|
02/21/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
HIGH ASPECT RATIO CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
11359001
|
Filing Dt:
|
02/21/2006
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2009
|
Application #:
|
11359098
|
Filing Dt:
|
02/21/2006
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
ATOMIC LAYER DEPOSITION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
11359104
|
Filing Dt:
|
02/22/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
MINIMIZING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2007
|
Application #:
|
11359275
|
Filing Dt:
|
02/21/2006
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
SUPPRESSION OF RINGING ARTIFACTS DURING IMAGE RESIZING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
11359311
|
Filing Dt:
|
02/21/2006
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
SUPPRESSION OF RINGING ARTIFACTS DURING IMAGE RESIZING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2010
|
Application #:
|
11359863
|
Filing Dt:
|
02/22/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
ELECTRONIC DEVICES INCLUDING CONDUCTIVE VIAS HAVING TWO OR MORE CONDUCTIVE ELEMENTS FOR PROVIDING ELECTRICAL COMMUNICATION BETWEEN TRACES IN DIFFERENT PLANES IN A SUBSTRATE, AND ACCOMPANYING METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
11359985
|
Filing Dt:
|
02/22/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING FACE-TO-FACE SEMICONDUCTOR DICE AND SYSTEMS INCLUDING SUCH ASSEMBLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2011
|
Application #:
|
11360093
|
Filing Dt:
|
02/22/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
CONTINUOUS HIGH-FREQUENCY EVENT FILTER
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11360868
|
Filing Dt:
|
02/23/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
Systems and methods for controlling fluid flow
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2009
|
Application #:
|
11360873
|
Filing Dt:
|
02/23/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
BIT LINE COUPLING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
11361228
|
Filing Dt:
|
02/24/2006
|
Publication #:
|
|
Pub Dt:
|
08/30/2007
| | | | |
Title:
|
MOVEABLE LOCKED LINES IN A MULTI-LEVEL CACHE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11362119
|
Filing Dt:
|
02/23/2006
|
Publication #:
|
|
Pub Dt:
|
03/15/2007
| | | | |
Title:
|
METHOD OF FORMING CONDUCTIVE METAL SILICIDES BY REACTION OF METAL WITH SILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
11362409
|
Filing Dt:
|
02/23/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
USING POSITIVE DC OFFSET OF BIAS RF TO NEUTRALIZE CHARGE BUILD-UP OF ETCH FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2007
|
Application #:
|
11362455
|
Filing Dt:
|
02/23/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
METHODS OF FORMING SILICON DIOXIDE LAYERS, AND METHODS OF FORMING TRENCH ISOLATION REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2008
|
Application #:
|
11363730
|
Filing Dt:
|
02/28/2006
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
NON-PLANAR FLASH MEMORY ARRAY WITH SHIELDED FLOATING GATES ON SILICON MESAS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
11364383
|
Filing Dt:
|
02/27/2006
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
CAPACITORS COMPRISING DIELECTRIC REGIONS HAVING FIRST AND SECOND OXIDE MATERIAL PORTIONS OF THE SAME CHEMICAL COMPOSITON BUT DIFFERENT DENSITIES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
11365036
|
Filing Dt:
|
03/01/2006
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
PROGRAMMING AND EVALUATING THROUGH PMOS INJECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2009
|
Application #:
|
11366212
|
Filing Dt:
|
03/02/2006
|
Publication #:
|
|
Pub Dt:
|
09/06/2007
| | | | |
Title:
|
VERTICAL GATED ACCESS TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
|
Application #:
|
11367020
|
Filing Dt:
|
03/02/2006
|
Publication #:
|
|
Pub Dt:
|
09/06/2007
| | | | |
Title:
|
MASKING PROCESS FOR SIMULTANEOUSLY PATTERNING SEPARATE REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
11367707
|
Filing Dt:
|
03/02/2006
|
Publication #:
|
|
Pub Dt:
|
09/21/2006
| | | | |
Title:
|
MEMORY DEVICE WITH TIME-SHIFTING BASED EMULATION OF REFERENCE CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
11367859
|
Filing Dt:
|
03/03/2006
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
INTEGRATED DRAM-NVRAM MULTI-LEVEL MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
11367860
|
Filing Dt:
|
03/03/2006
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
INTEGRATED DRAM-NVRAM MULTI-LEVEL MEMORY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11367914
|
Filing Dt:
|
03/03/2006
|
Publication #:
|
|
Pub Dt:
|
09/06/2007
| | | | |
Title:
|
Method, circuit and system for detecting a locked state of a clock synchronization circuit
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
11368037
|
Filing Dt:
|
03/03/2006
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
INTEGRATED DRAM-NVRAM MULTI-LEVEL MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
11368248
|
Filing Dt:
|
03/03/2006
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
INTEGRATED DRAM-NVRAM MULTI-LEVEL MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2009
|
Application #:
|
11368363
|
Filing Dt:
|
03/03/2006
|
Publication #:
|
|
Pub Dt:
|
09/28/2006
| | | | |
Title:
|
MEMORY DEVICE WITH A RAMP-LIKE VOLTAGE BIASING STRUCTURE AND REDUCED NUMBER OF REFERENCE CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
11368455
|
Filing Dt:
|
03/07/2006
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
ELECTRODE STRUCTURES AND METHOD TO FORM ELECTRODE STRUCTURES THAT MINIMIZE ELECTRODE WORK FUNCTION VARIATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2010
|
Application #:
|
11368898
|
Filing Dt:
|
03/06/2006
|
Publication #:
|
|
Pub Dt:
|
09/06/2007
| | | | |
Title:
|
METHOD OF FORMING CONTACTS FOR A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
11369236
|
Filing Dt:
|
03/07/2006
|
Publication #:
|
|
Pub Dt:
|
09/13/2007
| | | | |
Title:
|
TRENCH ISOLATION IMPLANTATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11369347
|
Filing Dt:
|
03/07/2006
|
Publication #:
|
|
Pub Dt:
|
09/13/2007
| | | | |
Title:
|
PROGRAMMING A FLASH MEMORY DEVICE
|
|