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Patent #:
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07/31/2012
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12983995
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Filing Dt:
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01/04/2011
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Publication #:
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Pub Dt:
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04/28/2011
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Title:
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CONTENT ADDRESSABLE MEMORY WITH CONCURRENT READ AND SEARCH/COMPARE OPERATIONS AT THE SAME MEMORY CELL
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NONE
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12984069
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Filing Dt:
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01/04/2011
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Pub Dt:
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07/05/2012
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Title:
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CONTROLLING DENSITY OF PARTICLES WITHIN UNDERFILL SURROUNDING SOLDER BUMP CONTACTS
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05/27/2014
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12984180
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01/04/2011
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Pub Dt:
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07/05/2012
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Title:
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ADVANCED ROUTING OF VEHICLE FLEETS
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09/10/2013
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12984252
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01/04/2011
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Pub Dt:
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08/18/2011
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Title:
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CACHE DIRECTORY LOOK-UP RE-USE AS CONFLICT CHECK MECHANISM FOR SPECULATIVE MEMORY REQUESTS
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09/16/2014
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12984308
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Filing Dt:
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01/04/2011
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Publication #:
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Pub Dt:
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07/14/2011
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Title:
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EVICT ON WRITE, A MANAGEMENT STRATEGY FOR A PREFETCH UNIT AND/OR FIRST LEVEL CACHE IN A MULTIPROCESSOR SYSTEM WITH SPECULATIVE EXECUTION
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12/10/2013
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12984359
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01/04/2011
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Pub Dt:
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07/05/2012
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Title:
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FLAT RESPONSE DEVICE STRUCTURES FOR BIPOLAR JUNCTION TRANSISTORS
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06/17/2014
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12984638
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01/05/2011
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Pub Dt:
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07/05/2012
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Title:
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INTEGRATED CIRCUIT CHIP INCORPORATING EMBEDDED THERMAL RADIATORS FOR LOCALIZED, ON-DEMAND, HEATING AND A SYSTEM AND METHOD FOR DESIGNING SUCH AN INTEGRATED CIRCUIT CHIP
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NONE
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12984640
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Filing Dt:
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01/05/2011
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07/05/2012
| | | | |
Title:
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Methods and Structures Involving Terminal Connections
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01/28/2014
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12984653
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01/05/2011
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05/12/2011
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Title:
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VERTICAL NANOWIRE FET DEVICES
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03/27/2012
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12984682
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Filing Dt:
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01/05/2011
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Publication #:
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04/28/2011
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Title:
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MEMORY READING METHOD FOR RESISTANCE DRIFT MITIGATION
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06/24/2014
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12984704
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01/05/2011
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Pub Dt:
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07/05/2012
| | | | |
Title:
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Analyzing Simulated Operation Of A Computer
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NONE
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12984773
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Filing Dt:
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01/05/2011
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Publication #:
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Pub Dt:
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07/05/2012
| | | | |
Title:
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TRANSMISSION GATES WITH ASYMMETRIC FIELD EFFECT TRANSISTORS
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11/05/2013
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12984927
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01/05/2011
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Publication #:
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Pub Dt:
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05/05/2011
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Title:
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SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRAIN AND METHODS OF MANUFACTURING AND DESIGN STRUCTURE
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11/08/2011
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12985060
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01/05/2011
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Publication #:
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Pub Dt:
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05/05/2011
| | | | |
Title:
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ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
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Patent #:
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Issue Dt:
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05/26/2015
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12985443
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01/06/2011
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Pub Dt:
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07/12/2012
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Title:
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VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR
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Patent #:
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01/29/2013
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12985456
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01/06/2011
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Pub Dt:
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05/05/2011
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Title:
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SUBSTRATE ANCHOR STRUCTURE AND METHOD
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Patent #:
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12/24/2013
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12985462
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Filing Dt:
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01/06/2011
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Publication #:
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Pub Dt:
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07/12/2012
| | | | |
Title:
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VOLTAGE DRIVER FOR A VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR
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Patent #:
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NONE
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12985484
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Filing Dt:
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01/06/2011
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Publication #:
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Pub Dt:
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07/12/2012
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGING INCLUDING AUXILIARY CIRCUITRY
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Patent #:
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Issue Dt:
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07/05/2016
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12985669
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01/06/2011
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Publication #:
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Pub Dt:
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07/12/2012
| | | | |
Title:
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Structure and Method to Fabricate Resistor on FinFET Processes
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03/20/2012
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12985726
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Filing Dt:
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01/06/2011
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Publication #:
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Pub Dt:
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05/05/2011
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Title:
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A SYSTEM FOR RECONFIGURING CACHE MEMORY HAVING AN ACCESS BIT ASSOCIATED WITH A SECTOR OF A LOWER-LEVEL CACHE MEMORY AND A GRANULARITY BIT ASSOCIATED WITH A SECTOR OF A HIGHER-LEVEL CACHE MEMORY
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12/09/2014
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12985840
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Filing Dt:
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01/06/2011
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Publication #:
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Pub Dt:
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07/12/2012
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Title:
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SILICON CONTROLLED RECTIFIERS (SCR), METHODS OF MANUFACTURE AND DESIGN STRUCTURES
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Patent #:
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07/16/2013
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12986132
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01/06/2011
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Pub Dt:
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07/12/2012
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Title:
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TALL MEZZANINE CONNECTOR
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Patent #:
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11/26/2013
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12986233
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01/07/2011
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Publication #:
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Pub Dt:
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11/17/2011
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Title:
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AUDITING VIDEO ANALYTICS THROUGH ESSENCE GENERATION
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02/11/2014
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12986266
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01/07/2011
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Publication #:
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Pub Dt:
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07/12/2012
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Title:
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CONDUCTIVE METAL AND DIFFUSION BARRIER SEED COMPOSITIONS, AND METHODS OF USE IN SEMICONDUCTOR AND INTERLEVEL DIELECTRIC SUBSTRATES
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11/18/2014
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12986652
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01/07/2011
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Publication #:
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Pub Dt:
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07/21/2011
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Title:
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STORE-OPERATE-COHERENCE-ON-VALUE
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11/08/2011
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12987089
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01/08/2011
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Publication #:
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Pub Dt:
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05/05/2011
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Title:
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FOUR-TERMINAL RECONFIGURABLE DEVICES
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01/15/2013
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12987106
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01/08/2011
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Pub Dt:
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05/05/2011
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Title:
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APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES
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11/05/2013
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12987182
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01/10/2011
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Pub Dt:
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07/12/2012
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Title:
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JOYSTICK TYPE COMPUTER INPUT DEVICE WITH MOUSE
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10/01/2013
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12987202
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Filing Dt:
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01/10/2011
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Publication #:
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Pub Dt:
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07/12/2012
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Title:
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ALIGNMENT MARKS TO ENABLE 3D INTEGRATION
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09/17/2013
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12987221
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01/10/2011
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Publication #:
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07/12/2012
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Title:
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SELF-ALIGNED CONTACTS FOR HIGH K/METAL GATE PROCESS FLOW
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03/26/2013
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12987232
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01/10/2011
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Pub Dt:
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05/05/2011
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Title:
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CONTOURED INSULATOR LAYER OF SILICON-ON-INSULATOR WAFERS AND PROCESS OF MANUFACTURE
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05/13/2014
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12987353
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01/10/2011
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Pub Dt:
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07/12/2012
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Title:
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METHODS AND APPARATUS FOR DETECTION OF GASEOUS CORROSIVE CONTAMINANTS
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07/14/2015
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13004007
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01/10/2011
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Pub Dt:
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09/08/2011
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Title:
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MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
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04/16/2013
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13004104
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01/11/2011
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07/12/2012
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Title:
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DENSE REGISTER ARRAY FOR ENABLING SCAN OUT OBSERVATION OF BOTH L1 AND L2 LATCHES
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11/10/2015
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13004129
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01/11/2011
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Pub Dt:
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05/05/2011
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Title:
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A THREE-TERMINAL ANTIFUSE STRUCTURE HAVING INTEGRATED HEATING ELEMENTS FOR A PROGRAMMABLE CIRCUIT
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05/08/2012
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13004201
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01/11/2011
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Title:
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PROCESS FOR EPITAXIALLY GROWING EPITAXIAL MATERIAL REGIONS
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03/12/2013
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13004471
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01/11/2011
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05/26/2011
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Title:
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SINGLE MASK ADDER PHASE CHANGE MEMORY ELEMENT
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01/08/2013
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13004883
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01/12/2011
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07/12/2012
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Title:
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FLASH ANALOG TO DIGITAL CONVERTER WITH METHOD AND SYSTEM FOR DYNAMIC CALIBRATION
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05/07/2013
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13005089
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01/12/2011
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Pub Dt:
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07/12/2012
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Title:
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IMPLEMENTING SEMICONDUCTOR SOC WITH METAL VIA GATE NODE HIGH PERFORMANCE STACKED TRANSISTORS
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01/01/2013
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13005201
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01/12/2011
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05/12/2011
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DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES
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07/09/2013
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13005330
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01/12/2011
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07/12/2012
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ROUTING-BASED PIN PLACEMENT
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03/11/2014
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13005560
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01/13/2011
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07/19/2012
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Title:
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SEMICONDUCTOR STRUCTURES WITH THINNED JUNCTIONS AND METHODS OF MANUFACTURE
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03/05/2013
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13005599
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01/13/2011
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07/19/2012
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Title:
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SYSTEM, METHOD AND PROGRAM STORAGE DEVICE FOR DEVELOPING CONDENSED NETLISTS REPRESENTATIVE OF GROUPS OF ACTIVE DEVICES IN AN INTEGRATED CIRCUIT AND FOR MODELING THE PERFORMANCE OF THE INTEGRATED CIRCUIT BASED ON THE CONDENSED NETLISTS
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10/15/2013
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13005650
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01/13/2011
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07/19/2012
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Title:
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PIXEL SENSOR CELLS WITH A SPLIT-DIELECTRIC TRANSFER GATE
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05/15/2012
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13005821
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01/13/2011
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06/16/2011
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SUSPENDED GERMANIUM PHOTODETECTOR FOR SILICON WAVEGUIDE
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08/02/2016
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13005883
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01/13/2011
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07/19/2012
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INTEGRATED CIRCUIT AND DESIGN STRUCTURE HAVING REDUCED THROUGH SILICON VIA-INDUCED STRESS
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01/03/2012
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13005894
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01/13/2011
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05/12/2011
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Title:
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SRAM CELL HAVING A RECTANGULAR COMBINED ACTIVE AREA FOR PLANAR PASS GATE AND PLANAR PULL-DOWN NFETS
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NONE
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13006001
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01/13/2011
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05/12/2011
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A PRECISION BURIED RESISTOR PRESENT IN A SEMINCONDUCTOR SUBSTRATE
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10/01/2013
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13006081
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01/13/2011
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07/19/2012
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Title:
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RADIATION HARDENED TRANSISTORS BASED ON GRAPHENE AND CARBON NANOTUBES
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04/16/2013
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13006403
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01/13/2011
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05/12/2011
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Title:
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SUB-LITHOGRAPHIC PRINTING METHOD
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04/16/2013
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13006412
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01/13/2011
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Pub Dt:
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05/05/2011
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Title:
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SUB-LITHOGRAPHIC PRINTING METHOD
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07/08/2014
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13006450
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01/14/2011
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07/19/2012
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Title:
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Method for Improving Static Timing Analysis and Optimizing Circuits Using Reverse Merge
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11/12/2013
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13006656
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01/14/2011
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07/19/2012
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Title:
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REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT
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06/04/2013
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13006664
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01/14/2011
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07/19/2012
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METHOD TO CONTROL METAL SEMICONDUCTOR MICRO-STRUCTURE
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08/27/2013
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13007242
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01/14/2011
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07/19/2012
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Title:
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MULTIPLE LITHOGRAPHIC SYSTEM MASK SHAPE SLEEVING
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12/31/2013
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13007644
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01/16/2011
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07/19/2012
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HIGH-SPEED GRAPHENE TRANSISTOR AND METHOD OF FABRICATION BY PATTERNABLE HARD MASK MATERIALS
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02/18/2014
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13008459
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01/18/2011
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Pub Dt:
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07/19/2012
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COMPACT THERMALLY CONTROLLED THIN FILM RESISTORS UTILIZING SUBSTRATE CONTACTS AND METHODS OF MANUFACTURE
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10/30/2012
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Application #:
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13008465
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Filing Dt:
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01/18/2011
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Publication #:
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Pub Dt:
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07/19/2012
| | | | |
Title:
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COMPACT THERMALLY CONTROLLED THIN FILM RESISTORS UTILIZING SUBSTRATE CONTACTS AND METHODS OF MANUFACTURE
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Patent #:
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Issue Dt:
|
11/29/2016
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Application #:
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13008531
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Filing Dt:
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01/18/2011
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Publication #:
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Pub Dt:
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09/08/2011
| | | | |
Title:
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CACHE AS POINT OF COHERENCE IN MULTIPROCESSOR SYSTEM
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13008546
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Filing Dt:
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01/18/2011
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Publication #:
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Pub Dt:
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09/08/2011
| | | | |
Title:
|
ATOMICITY: A MULTI-PRONGED APPROACH
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Patent #:
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Issue Dt:
|
06/10/2014
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Application #:
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13008583
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Filing Dt:
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01/18/2011
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Publication #:
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Pub Dt:
|
09/08/2011
| | | | |
Title:
|
READER SET ENCODING FOR DIRECTORY OF SHARED CACHE MEMORY IN MULTIPROCESSOR SYSTEM
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Patent #:
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Issue Dt:
|
10/21/2014
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Application #:
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13008602
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Filing Dt:
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01/18/2011
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Publication #:
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Pub Dt:
|
09/08/2011
| | | | |
Title:
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CACHE DIRECTORY LOOKUP READER SET ENCODING FOR PARTIAL CACHE LINE SPECULATION SUPPORT
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Patent #:
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|
Issue Dt:
|
05/13/2014
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Application #:
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13008935
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Filing Dt:
|
01/19/2011
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Publication #:
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Pub Dt:
|
07/19/2012
| | | | |
Title:
|
MINIMIZING THE MAXIMUM REQUIRED LINK CAPACITY FOR THREE-DIMENSIONAL INTERCONNECT ROUTING
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Patent #:
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|
Issue Dt:
|
01/29/2013
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Application #:
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13009029
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Filing Dt:
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01/19/2011
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Publication #:
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Pub Dt:
|
07/19/2012
| | | | |
Title:
|
STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS
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Patent #:
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|
Issue Dt:
|
01/15/2013
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Application #:
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13009048
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Filing Dt:
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01/19/2011
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Publication #:
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Pub Dt:
|
07/19/2012
| | | | |
Title:
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SEMICONDUCTOR STRUCTURE AND CIRCUIT INCLUDING ORDERED ARRANGEMENT OF GRAPHENE NANORIBBONS, AND METHODS OF FORMING SAME
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
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13009271
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Filing Dt:
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01/19/2011
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Publication #:
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Pub Dt:
|
07/19/2012
| | | | |
Title:
|
Methods for Forming Field Effect Transistor Devices With Protective Spacers
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Patent #:
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|
Issue Dt:
|
04/02/2013
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Application #:
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13009280
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Filing Dt:
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01/19/2011
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Publication #:
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Pub Dt:
|
07/19/2012
| | | | |
Title:
|
Graphene Devices and Silicon Field Effect Transistors in 3D Hybrid Integrated Circuits
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|
Patent #:
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|
Issue Dt:
|
03/25/2014
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Application #:
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13009758
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Filing Dt:
|
01/19/2011
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Publication #:
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|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
PATTERNING PROCESS FOR SMALL DEVICES
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|
|
Patent #:
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|
Issue Dt:
|
11/20/2012
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Application #:
|
13010004
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Filing Dt:
|
01/20/2011
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Publication #:
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|
Pub Dt:
|
07/28/2011
| | | | |
Title:
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HOMOGENEOUS POROUS LOW DIELECTRIC CONSTANT MATERIALS
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|
Patent #:
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|
Issue Dt:
|
07/02/2013
|
Application #:
|
13010009
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Filing Dt:
|
01/20/2011
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Publication #:
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|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
GATE CONDUCTOR WITH A DIFFUSION BARRIER
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13010041
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Filing Dt:
|
01/20/2011
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Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
STRUCTURE AND METHOD FOR REDUCTION OF VT-W EFFECT IN HIGH-K METAL GATE DEVICES
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|
Patent #:
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|
Issue Dt:
|
06/16/2015
|
Application #:
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13010057
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Filing Dt:
|
01/20/2011
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Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
CIRCUIT FOR DETECTING STRUCTURAL DEFECTS IN AN INTEGRATED CIRCUIT CHIP, METHODS OF USE AND MANUFACTURE AND DESIGN STRUCTURES
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|
Patent #:
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|
Issue Dt:
|
06/23/2015
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Application #:
|
13010184
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Filing Dt:
|
01/20/2011
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Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
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TRANSFERRING HEAT THROUGH AN OPTICAL LAYER OF INTEGRATED CIRCUITRY
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|
Patent #:
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|
Issue Dt:
|
01/01/2013
|
Application #:
|
13010249
|
Filing Dt:
|
01/20/2011
|
Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
SELF-CALIBRATED, BROADBAND, TUNABLE, ACTIVE FILTER WITH UNITY GAIN CELLS FOR MULTI-STANDARD AND/OR MULTIBAND CHANNEL SELECTION
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|
Patent #:
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|
Issue Dt:
|
01/08/2013
|
Application #:
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13010285
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Filing Dt:
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01/20/2011
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Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
TRACK AND HOLD AMPLIFIERS AND DIGITAL CALIBRATION FOR ANALOG-TO-DIGITAL CONVERTERS
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|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
13010326
|
Filing Dt:
|
01/20/2011
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
METHODS FOR SELF-ALIGNED SELF-ASSEMBLED PATTERNING ENHANCEMENT
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|
|
Patent #:
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|
Issue Dt:
|
10/30/2012
|
Application #:
|
13010878
|
Filing Dt:
|
01/21/2011
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
PREVENTING METASTABILITY OF A DIVIDE-BY-TWO QUADRATURE DIVIDER
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|
|
Patent #:
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|
Issue Dt:
|
06/25/2013
|
Application #:
|
13011215
|
Filing Dt:
|
01/21/2011
|
Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
FINFET FUSE WITH ENHANCED CURRENT CROWDING
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|
|
Patent #:
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|
Issue Dt:
|
04/24/2012
|
Application #:
|
13011509
|
Filing Dt:
|
01/21/2011
|
Publication #:
|
|
Pub Dt:
|
05/19/2011
| | | | |
Title:
|
ULTRAVIOLET ENERGY CURABLE TAPE AND METHOD OF MAKING A SEMICONDUCTOR CHIP USING THE TAPE
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|
|
Patent #:
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|
Issue Dt:
|
10/02/2012
|
Application #:
|
13012043
|
Filing Dt:
|
01/24/2011
|
Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
METAL-SEMICONDUCTOR INTERMIXED REGIONS
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|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13012137
|
Filing Dt:
|
01/24/2011
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
SEMICONDUCTOR-ON-INSULATOR DEVICE WITH ASYMMETRIC STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
07/30/2013
|
Application #:
|
13012142
|
Filing Dt:
|
01/24/2011
|
Publication #:
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|
Pub Dt:
|
04/05/2012
| | | | |
Title:
|
Shallow Trench Isolation Chemical Mechanical Planarization
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|
|
Patent #:
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|
Issue Dt:
|
01/28/2014
|
Application #:
|
13012147
|
Filing Dt:
|
01/24/2011
|
Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
LOW ENERGY ELECTROMAGNETIC RELAY
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|
|
Patent #:
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|
Issue Dt:
|
08/05/2014
|
Application #:
|
13012166
|
Filing Dt:
|
01/24/2011
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
BILAYER TRENCH FIRST HARDMASK STRUCTURE AND PROCESS FOR REDUCED DEFECTIVITY
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|
|
Patent #:
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|
Issue Dt:
|
01/07/2014
|
Application #:
|
13012179
|
Filing Dt:
|
01/24/2011
|
Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
DISCRETE SAMPLING BASED NONLINEAR CONTROL SYSTEM
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|
|
Patent #:
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|
Issue Dt:
|
09/03/2013
|
Application #:
|
13012821
|
Filing Dt:
|
01/25/2011
|
Publication #:
|
|
Pub Dt:
|
04/05/2012
| | | | |
Title:
|
CHEMICAL MECHANICAL PLANARIZATION WITH OVERBURDEN MASK
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|
|
Patent #:
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|
Issue Dt:
|
08/20/2013
|
Application #:
|
13012836
|
Filing Dt:
|
01/25/2011
|
Publication #:
|
|
Pub Dt:
|
04/05/2012
| | | | |
Title:
|
Chemical Mechanical Planarization Processes For Fabrication of FINFET Devices
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|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
13012879
|
Filing Dt:
|
01/25/2011
|
Publication #:
|
|
Pub Dt:
|
04/05/2012
| | | | |
Title:
|
FABRICATION OF REPLACEMENT METAL GATE DEVICES
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|
|
Patent #:
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|
Issue Dt:
|
12/16/2014
|
Application #:
|
13013055
|
Filing Dt:
|
01/25/2011
|
Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
eFUSE AND METHOD OF FABRICATION
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|
|
Patent #:
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|
Issue Dt:
|
12/02/2014
|
Application #:
|
13013067
|
Filing Dt:
|
01/25/2011
|
Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
Deposition On A Nanowire Using Atomic Layer Deposition
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|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13013108
|
Filing Dt:
|
01/25/2011
|
Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
AIR-DIELECTRIC FOR SUBTRACTIVE ETCH LINE AND VIA METALLIZATION
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|
|
Patent #:
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|
Issue Dt:
|
03/19/2013
|
Application #:
|
13013133
|
Filing Dt:
|
01/25/2011
|
Publication #:
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|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
TEST STRUCTURE FOR DETECTION OF GAP IN CONDUCTIVE LAYER OF MULTILAYER GATE STACK
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
13013206
|
Filing Dt:
|
01/25/2011
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
SELF-ALIGNED III-V MOSFET FABRICATION WITH IN-SITU III-V EPITAXY AND IN-SITU METAL EPITAXY AND CONTACT FORMATION
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|
|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
13013311
|
Filing Dt:
|
01/25/2011
|
Publication #:
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|
Pub Dt:
|
05/19/2011
| | | | |
Title:
|
DOUBLE GATE DEPLETION MODE MOSFET
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|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13013357
|
Filing Dt:
|
01/25/2011
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
DEVICE AND METHOD FOR BORON DIFFUSION IN SEMICONDUCTORS
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|
|
Patent #:
|
|
Issue Dt:
|
02/12/2013
|
Application #:
|
13013801
|
Filing Dt:
|
01/25/2011
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
FABRICATION OF CMOS TRANSISTORS HAVING DIFFERENTIALLY STRESSED SPACERS
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|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
13013935
|
Filing Dt:
|
01/26/2011
|
Title:
|
MASK AND ETCH PROCESS FOR PATTERN ASSEMBLY
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|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13014114
|
Filing Dt:
|
01/26/2011
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
NON-CONFORMAL HARDMASK DEPOSITION FOR THROUGH SILICON ETCH
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|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13014152
|
Filing Dt:
|
01/26/2011
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
DIAGNOSING IN-LINE CRITICAL DIMENSION CONTROL ADJUSTMENTS USING OPTICAL PROXIMITY CORRECTION VERIFICATION
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|
|
Patent #:
|
|
Issue Dt:
|
07/30/2013
|
Application #:
|
13014159
|
Filing Dt:
|
01/26/2011
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
OPTICAL PROXIMITY CORRECTION VERIFICATION ACCOUNTING FOR MASK DEVIATIONS
|
|