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249
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10841162
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Filing Dt:
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05/07/2004
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Publication #:
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Pub Dt:
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01/06/2005
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Title:
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MULTIPLE CHIP SEMICONDUCTOR ARRANGEMENT HAVING ELECTRICAL COMPONENTS IN SEPARATING REGIONS
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Patent #:
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Issue Dt:
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12/20/2005
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Application #:
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10870780
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Filing Dt:
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06/17/2004
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Publication #:
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Pub Dt:
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12/22/2005
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Title:
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MTJ STACK WITH CRYSTALLIZATION INHIBITING LAYER
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10873010
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Filing Dt:
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06/22/2004
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Publication #:
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Pub Dt:
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12/22/2005
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Title:
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STANDBY CURRENT REDUCTION OVER A PROCESS WINDOW WITH A TRIMMABLE WELL BIAS
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Patent #:
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Issue Dt:
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03/06/2007
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Application #:
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10881598
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Filing Dt:
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06/30/2004
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Publication #:
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Pub Dt:
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01/05/2006
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Title:
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DIGITAL DUTY CYCLE CORRECTOR
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Patent #:
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Issue Dt:
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10/30/2007
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Application #:
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10882592
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Filing Dt:
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07/01/2004
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Publication #:
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Pub Dt:
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01/05/2006
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Title:
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CIRCUIT AND METHOD FOR ADJUSTING THRESHOLD DRIFT OVER TEMPERATURE IN A CMOS RECEIVER
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Patent #:
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Issue Dt:
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05/29/2007
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Application #:
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10899253
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Filing Dt:
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07/26/2004
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Publication #:
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Pub Dt:
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01/26/2006
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Title:
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ALIGNMENT OF MTJ STACK TO CONDUCTIVE LINES IN THE ABSENCE OF TOPOGRAPHY
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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10901765
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Filing Dt:
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07/29/2004
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Publication #:
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Pub Dt:
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01/06/2005
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Title:
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SCANNING TIP ORIENTATION ADJUSTMENT METHOD FOR ATOMIC FORCE MICROSCOPY
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Patent #:
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Issue Dt:
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10/28/2008
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Application #:
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10909599
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Filing Dt:
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08/02/2004
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Publication #:
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Pub Dt:
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02/02/2006
| | | | |
Title:
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DEEP ALIGNMENT MARKS ON EDGE CHIPS FOR SUBSEQUENT ALIGNMENT OF OPAQUE LAYERS
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Patent #:
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Issue Dt:
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07/31/2007
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Application #:
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10921766
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Filing Dt:
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08/19/2004
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Publication #:
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Pub Dt:
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02/23/2006
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Title:
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SEMICONDUCTOR MEMORY DEVICE COMPRISING MEMORY CELLS WITH FLOATING GATE ELECTRODE AND METHOD OF PRODUCTION
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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10928616
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Filing Dt:
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08/27/2004
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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CIRCUIT BOARD AND METHOD FOR PRODUCING A CIRCUIT BOARD
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Patent #:
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Issue Dt:
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10/10/2006
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Application #:
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10930132
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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METHOD FOR TESTING THE SERVICEABILITY OF BIT LINES IN A DRAM MEMORY DEVICE
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Patent #:
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Issue Dt:
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05/20/2008
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Application #:
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10938845
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Filing Dt:
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09/13/2004
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Publication #:
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Pub Dt:
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03/16/2006
| | | | |
Title:
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SEMICONDUCTOR CHIP WITH FLEXIBLE CONTACTS AT A FACE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10938847
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Filing Dt:
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09/13/2004
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Publication #:
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Pub Dt:
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03/16/2006
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Title:
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Method for producing a stack of chips, a stack of chips and method for producing a chip for a multi-chip stack
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Patent #:
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Issue Dt:
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11/07/2006
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Application #:
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10939255
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Filing Dt:
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09/10/2004
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Publication #:
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Pub Dt:
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03/16/2006
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Title:
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TRANSISTOR, MEMORY CELL ARRAY AND METHOD OF MANUFACTURING A TRANSISTOR
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Patent #:
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Issue Dt:
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05/30/2006
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Application #:
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10940414
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Filing Dt:
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09/14/2004
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Publication #:
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Pub Dt:
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03/16/2006
| | | | |
Title:
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CHARGE-TRAPPING SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/15/2008
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Application #:
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10940490
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Filing Dt:
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09/14/2004
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Publication #:
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Pub Dt:
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03/16/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR CHARACTERIZING A RECESS LOCATED ON A SURFACE OF A SUBSTRATE
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10952233
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Filing Dt:
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09/28/2004
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Publication #:
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Pub Dt:
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03/30/2006
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Title:
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NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/09/2008
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Application #:
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10952707
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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CHARGE-TRAPPING MEMORY CELL AND CHARGE-TRAPPING MEMORY DEVICE
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Patent #:
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Issue Dt:
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04/04/2006
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Application #:
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10953606
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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RESISTIVE MEMORY ELEMENT
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10954869
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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03/30/2006
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Title:
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MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM HAVING BIDIRECTIONAL CLOCK LINES
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Patent #:
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Issue Dt:
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02/06/2007
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Application #:
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10955177
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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MEMORY SYSTEM WITH TWO CLOCK LINES AND A MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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10957803
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Filing Dt:
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10/04/2004
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Publication #:
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Pub Dt:
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04/06/2006
| | | | |
Title:
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FLEXIBLE BLENDER
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Patent #:
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Issue Dt:
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10/21/2008
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Application #:
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10958464
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Filing Dt:
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10/05/2004
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Publication #:
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Pub Dt:
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04/06/2006
| | | | |
Title:
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GATE LAYER DIODE METHOD AND APPARATUS
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Patent #:
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|
Issue Dt:
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08/22/2006
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Application #:
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10964102
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Filing Dt:
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10/13/2004
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Publication #:
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Pub Dt:
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04/13/2006
| | | | |
Title:
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MEASURING FLARE IN SEMICONDUCTOR LITHOGRAPHY
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10966776
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Filing Dt:
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10/15/2004
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Publication #:
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Pub Dt:
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04/20/2006
| | | | |
Title:
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COMBINED RECEIVER AND LATCH
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Patent #:
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Issue Dt:
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02/27/2007
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Application #:
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10967768
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Filing Dt:
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10/18/2004
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Publication #:
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Pub Dt:
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04/20/2006
| | | | |
Title:
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DQS FOR DATA FROM A MEMORY ARRAY
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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10969343
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Filing Dt:
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10/21/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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SIMULATING A FLOATING WORDLINE CONDITION IN A MEMORY DEVICE, AND RELATED TECHNIQUES
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Patent #:
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Issue Dt:
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05/16/2006
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Application #:
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10973389
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Filing Dt:
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10/27/2004
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Publication #:
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Pub Dt:
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04/27/2006
| | | | |
Title:
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METHOD AND APPARATUS COMPENSATING FOR FREQUENCY DRIFT IN A DELAY LOCKED LOOP
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Patent #:
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Issue Dt:
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04/10/2007
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Application #:
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10974019
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Filing Dt:
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10/27/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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SEMICONDUCTOR MEMORY HAVING TRI-STATE DRIVER DEVICE
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Patent #:
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Issue Dt:
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04/03/2007
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Application #:
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10974521
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Filing Dt:
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10/27/2004
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Publication #:
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Pub Dt:
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04/27/2006
| | | | |
Title:
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CIRCUIT HAVING DELAY LOCKED LOOP FOR CORRECTING OFF CHIP DRIVER DUTY DISTORTION
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10974564
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Filing Dt:
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10/27/2004
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Publication #:
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Pub Dt:
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04/27/2006
| | | | |
Title:
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VARIABLE DELAY LINE USING TWO BLENDER DELAYS
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Patent #:
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Issue Dt:
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08/22/2006
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Application #:
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10976159
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Filing Dt:
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10/29/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
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METHOD FOR DETERMINING AN OPTIMAL ABSORBER STACK GEOMETRY OF A LITHOGRAPHIC REFLECTION MASK
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Patent #:
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Issue Dt:
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07/03/2007
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Application #:
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10978216
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Filing Dt:
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10/29/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING A SEMICONDUCTOR DEVICE
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Patent #:
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|
Issue Dt:
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01/09/2007
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Application #:
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10980301
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Filing Dt:
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11/04/2004
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Publication #:
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Pub Dt:
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05/18/2006
| | | | |
Title:
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APPARATUS AND METHOD FOR MAKING GROUND CONNECTION
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Patent #:
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|
Issue Dt:
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08/15/2006
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Application #:
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10981947
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Filing Dt:
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11/05/2004
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Publication #:
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|
Pub Dt:
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05/11/2006
| | | | |
Title:
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DUTY DISTORTION DETECTOR
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Patent #:
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|
Issue Dt:
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05/23/2006
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Application #:
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10986767
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Filing Dt:
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11/15/2004
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Publication #:
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|
Pub Dt:
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05/18/2006
| | | | |
Title:
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SEMICONDUCTOR MEMORY SYSTEM AND METHOD FOR THE TRANSFER OF WRITE AND READ DATA SIGNALS IN A SEMICONDUCTOR MEMORY SYSTEM
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Patent #:
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|
Issue Dt:
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09/04/2007
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Application #:
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10987812
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Filing Dt:
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11/12/2004
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Publication #:
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Pub Dt:
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05/18/2006
| | | | |
Title:
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MEMORY ACCESS USING MULTIPLE SETS OF ADDRESS/DATA LINES
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Patent #:
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Issue Dt:
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01/09/2007
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Application #:
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10988787
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Filing Dt:
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11/15/2004
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Publication #:
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Pub Dt:
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05/18/2006
| | | | |
Title:
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SENSE AMPLIFIER BITLINE BOOST CIRCUIT
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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10990420
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Filing Dt:
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11/18/2004
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Publication #:
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Pub Dt:
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05/18/2006
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Title:
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METHOD FOR FULL WAFER CONTACT PROBING, WAFER DESIGN AND PROBE CARD DEVICE WITH REDUCED PROBE CONTACTS
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Patent #:
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Issue Dt:
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01/16/2007
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Application #:
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10991434
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Filing Dt:
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11/19/2004
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Publication #:
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Pub Dt:
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05/25/2006
| | | | |
Title:
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FLEXIBLE INTERNAL ADDRESS COUNTING METHOD AND APPARATUS
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10992826
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Filing Dt:
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11/19/2004
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Publication #:
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Pub Dt:
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05/25/2006
| | | | |
Title:
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TWIN-CELL BIT LINE SENSING CONFIGURATION
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Patent #:
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Issue Dt:
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07/25/2006
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Application #:
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10993250
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Filing Dt:
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11/19/2004
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Publication #:
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Pub Dt:
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05/25/2006
| | | | |
Title:
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RANDOM ACCESS MEMORY HAVING FAST COLUMN ACCESS
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Patent #:
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Issue Dt:
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03/27/2007
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Application #:
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10994977
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Filing Dt:
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11/22/2004
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Publication #:
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Pub Dt:
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05/25/2006
| | | | |
Title:
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ESD PROTECTION APPARATUS FOR AN ELECTRICAL DEVICE
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Patent #:
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Issue Dt:
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09/26/2006
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Application #:
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10995643
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Filing Dt:
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11/23/2004
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Publication #:
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Pub Dt:
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05/25/2006
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Title:
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ENERGY ADJUSTED WRITE PULSES IN PHASE-CHANGE MEMORIES
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10995644
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Filing Dt:
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11/23/2004
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Title:
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MULTI-PULSE RESET WRITE SCHEME FOR PHASE-CHANGE MEMORIES
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Patent #:
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Issue Dt:
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03/14/2006
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Application #:
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10996669
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Filing Dt:
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11/24/2004
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Publication #:
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Pub Dt:
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07/14/2005
| | | | |
Title:
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POLYELECTROLYTE DISPENSING POLISHING PAD
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Patent #:
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Issue Dt:
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04/08/2008
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Application #:
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10998975
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Filing Dt:
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11/30/2004
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Publication #:
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Pub Dt:
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06/01/2006
| | | | |
Title:
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TRANSISTOR ARRAY FOR SEMICONDUCTOR MEMORY DEVICES AND METHOD FOR FABRICATING A VERTICAL CHANNEL TRANSISTOR ARRAY
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Patent #:
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Issue Dt:
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11/25/2008
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Application #:
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11000323
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Filing Dt:
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11/30/2004
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Publication #:
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Pub Dt:
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06/01/2006
| | | | |
Title:
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CIRCUIT AND METHOD FOR TRANSMITTING A SIGNAL
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Patent #:
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Issue Dt:
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12/19/2006
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Application #:
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11000335
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Filing Dt:
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11/30/2004
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Publication #:
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Pub Dt:
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06/01/2006
| | | | |
Title:
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NON-VOLATILE SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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11/20/2007
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Application #:
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11000350
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Filing Dt:
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11/30/2004
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Publication #:
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Pub Dt:
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06/01/2006
| | | | |
Title:
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CHARGE-TRAPPING MEMORY CELL AND METHOD FOR PRODUCTION
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Patent #:
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Issue Dt:
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02/19/2008
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Application #:
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11002148
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Filing Dt:
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12/03/2004
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Publication #:
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Pub Dt:
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06/08/2006
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Title:
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MEMORY MODULE WITH A CLOCK SIGNAL REGENERATION CIRCUIT AND A REGISTER CIRCUIT FOR TEMPORARILY STORING THE INCOMING COMMAND AND ADDRESS SIGNALS
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Patent #:
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Issue Dt:
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11/21/2006
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Application #:
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11004881
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Filing Dt:
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12/07/2004
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Publication #:
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Pub Dt:
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06/08/2006
| | | | |
Title:
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MEMORY CELL ARRAY
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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11005045
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Filing Dt:
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12/07/2004
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Title:
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MEMORY DEVICE AND METHOD OF MANUFACTURING A MEMORY DEVICE
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Patent #:
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Issue Dt:
|
04/11/2006
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Application #:
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11006484
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Filing Dt:
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12/07/2004
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Title:
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METHOD FOR PRODUCTION OF CHARGE-TRAPPING MEMORY DEVICES
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Patent #:
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Issue Dt:
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04/10/2007
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Application #:
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11006865
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Filing Dt:
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12/08/2004
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Publication #:
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Pub Dt:
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06/08/2006
| | | | |
Title:
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INTEGRATED DRAM MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/04/2007
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Application #:
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11010182
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Filing Dt:
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12/10/2004
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Publication #:
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Pub Dt:
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06/15/2006
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Title:
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MEMORY RANK DECODER FOR A MULTI-RANK DUAL INLINE MEMORY MODULE (DIMM)
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Patent #:
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Issue Dt:
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04/03/2007
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Application #:
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11010942
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Filing Dt:
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12/10/2004
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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STACKED DRAM MEMORY CHIP FOR A DUAL INLINE MEMORY MODULE (DIMM)
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Patent #:
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Issue Dt:
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04/24/2007
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Application #:
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11011038
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Filing Dt:
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12/15/2004
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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METHOD FOR FABRICATING BOTTOM ELECTRODES OF STACKED CAPACITOR MEMORY CELLS AND METHOD FOR CLEANING AND DRYING A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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11011039
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Filing Dt:
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12/15/2004
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Title:
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METHOD FOR FABRICATING BOTTOM ELECTRODES OF STACKED CAPACITOR MEMORY CELLS
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Patent #:
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Issue Dt:
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01/13/2009
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Application #:
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11011040
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Filing Dt:
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12/15/2004
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Publication #:
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Pub Dt:
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12/14/2006
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Title:
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6F2 ACCESS TRANSISTOR ARRANGEMENT AND SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/04/2007
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Application #:
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11012777
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Filing Dt:
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12/14/2004
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Publication #:
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Pub Dt:
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06/15/2006
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Title:
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METHOD TO IMPROVE CURRENT AND SLEW RATE RATIO OF OFF-CHIP DRIVERS
|
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Patent #:
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Issue Dt:
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01/30/2007
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Application #:
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11013582
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Filing Dt:
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12/16/2004
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Publication #:
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Pub Dt:
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06/22/2006
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Title:
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MEMORY CIRCUIT RECEIVERS ACTIVATED BY ENABLE CIRCUIT
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Patent #:
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Issue Dt:
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08/28/2007
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Application #:
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11013870
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Filing Dt:
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12/16/2004
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Publication #:
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Pub Dt:
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06/22/2006
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Title:
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MEMORY HAVING TEST CIRCUIT
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Patent #:
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Issue Dt:
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11/07/2006
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Application #:
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11017194
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Filing Dt:
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12/20/2004
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Publication #:
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Pub Dt:
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06/22/2006
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Title:
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CHARGE-TRAPPING MEMORY DEVICE AND METHOD OF PRODUCTION
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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11018313
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Filing Dt:
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12/21/2004
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Publication #:
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Pub Dt:
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06/22/2006
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Title:
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MEMORY ACCESS USING MULTIPLE ACTIVATED MEMORY CELL ROWS
|
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Patent #:
|
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Issue Dt:
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12/12/2006
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Application #:
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11021370
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Filing Dt:
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12/23/2004
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Publication #:
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Pub Dt:
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06/29/2006
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Title:
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DELAY LOCKED LOOP USING SYNCHRONOUS MIRROR DELAY
|
|
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Patent #:
|
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Issue Dt:
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10/17/2006
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Application #:
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11022202
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Filing Dt:
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12/22/2004
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Publication #:
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Pub Dt:
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06/22/2006
| | | | |
Title:
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MEMORY HAVING INTERNAL COLUMN COUNTER FOR COMPRESSION TEST MODE
|
|
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Patent #:
|
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Issue Dt:
|
09/04/2007
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Application #:
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11024932
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Filing Dt:
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12/30/2004
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Publication #:
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Pub Dt:
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07/06/2006
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Title:
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OPTO-ELECTRONIC MEMORY ELEMENT ON THE BASIS OF ORGANIC METALLOPORPHYRIN MOLECULES
|
|
|
Patent #:
|
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Issue Dt:
|
08/07/2007
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Application #:
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11025561
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Filing Dt:
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12/29/2004
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Publication #:
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Pub Dt:
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06/29/2006
| | | | |
Title:
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MEMORY WITH SELECTABLE SINGLE CELL OR TWIN CELL CONFIGURATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2008
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Application #:
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11031716
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Filing Dt:
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01/07/2005
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Publication #:
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Pub Dt:
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07/13/2006
| | | | |
Title:
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HIGH DIELECTRIC CONSTANT MATERIALS
|
|
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Patent #:
|
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Issue Dt:
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06/12/2007
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Application #:
|
11032459
|
Filing Dt:
|
01/10/2005
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Publication #:
|
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Pub Dt:
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07/13/2006
| | | | |
Title:
|
DUTY CYCLE CORRECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
11034006
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Filing Dt:
|
01/12/2005
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Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
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DUTY CYCLE DETECTOR WITH FIRST, SECOND, AND THIRD VALUES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
11038465
|
Filing Dt:
|
01/21/2005
|
Publication #:
|
|
Pub Dt:
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07/27/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
11039665
|
Filing Dt:
|
01/20/2005
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Publication #:
|
|
Pub Dt:
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07/27/2006
| | | | |
Title:
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INTERNAL REFERENCE VOLTAGE GENERATION FOR INTEGRATED CIRCUIT TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
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Application #:
|
11039740
|
Filing Dt:
|
01/20/2005
|
Publication #:
|
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Pub Dt:
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07/20/2006
| | | | |
Title:
|
STORAGE CAPACITOR AND METHOD OF MANUFACTURING A STORAGE CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
11040176
|
Filing Dt:
|
01/21/2005
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Title:
|
SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2008
|
Application #:
|
11040630
|
Filing Dt:
|
01/21/2005
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
INTEGRATED CIRCUIT INCLUDING A MEMORY HAVING LOW INITIAL LATENCY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
11043950
|
Filing Dt:
|
01/28/2005
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
METHOD OF TREATING A STRUCTURED SURFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2011
|
Application #:
|
11044721
|
Filing Dt:
|
01/28/2005
|
Publication #:
|
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Pub Dt:
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08/03/2006
| | | | |
Title:
|
METHOD FOR PRODUCING A DIELECTRIC MATERIAL ON A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
11046065
|
Filing Dt:
|
01/28/2005
|
Publication #:
|
|
Pub Dt:
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08/03/2006
| | | | |
Title:
|
TEST DATA TOPOLOGY WRITE TO MEMORY USING LATCHED SENSE AMPLIFIER DATA AND ROW ADDRESS SCRAMBLING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
11046160
|
Filing Dt:
|
01/28/2005
|
Publication #:
|
|
Pub Dt:
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08/17/2006
| | | | |
Title:
|
MEMORY DEVICE HAVING COMPONENTS FOR TRANSMITTING AND RECEIVING SIGNALS SYNCHRONOUSLY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
11048185
|
Filing Dt:
|
02/01/2005
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
DUTY CYCLE CORRECTOR
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11048186
|
Filing Dt:
|
02/01/2005
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
Pillar phase change memory cell
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
11049857
|
Filing Dt:
|
02/04/2005
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
Title:
|
METHODS AND APPARATUS FOR IMPLEMENTING A POWER DOWN IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
|
Application #:
|
11051257
|
Filing Dt:
|
02/04/2005
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
Title:
|
METHOD FOR INTERCONNECTING SEMICONDUCTOR COMPONENTS WITH SUBSTRATES AND CONTACT MEANS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
11051969
|
Filing Dt:
|
02/04/2005
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
Title:
|
DISSOCIATED FABRICATION OF PACKAGES AND CHIPS OF INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
11054853
|
Filing Dt:
|
02/10/2005
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
Title:
|
INTEGRATED CIRCUIT HAVING A MEMORY INCLUDING A LOW-K DIELECTRIC MATERIAL FOR THERMAL ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
11058723
|
Filing Dt:
|
02/15/2005
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
Title:
|
ENHANCED MEGASONIC BASED CLEAN USING AN ALTERNATIVE CLEANING CHEMISTRY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
11060737
|
Filing Dt:
|
02/18/2005
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR SEMICONDUCTOR TESTING UTILIZING DIES WITH INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
11061314
|
Filing Dt:
|
02/18/2005
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
CHARGE-TRAPPING MEMORY DEVICE AND METHOD FOR PRODUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
11065196
|
Filing Dt:
|
02/24/2005
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
RANDOM ACCESS MEMORY INCLUDING SELECTIVE ACTIVATION OF SELECT LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
11066320
|
Filing Dt:
|
02/25/2005
|
Title:
|
METHOD AND SYSTEM FOR FABRICATING FREE-STANDING NANOSTRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
11066555
|
Filing Dt:
|
02/28/2005
|
Publication #:
|
|
Pub Dt:
|
08/31/2006
| | | | |
Title:
|
CHIP STACK EMPLOYING A FLEX CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2007
|
Application #:
|
11066731
|
Filing Dt:
|
02/25/2005
|
Publication #:
|
|
Pub Dt:
|
08/31/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF OPERATING A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
11068582
|
Filing Dt:
|
02/28/2005
|
Publication #:
|
|
Pub Dt:
|
08/31/2006
| | | | |
Title:
|
DATA STROBE SYNCHRONIZATION FOR DRAM DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
11073523
|
Filing Dt:
|
03/08/2005
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
MEMORY DEVICE HAVING OFF-CHIP DRIVER ENABLE CIRCUIT AND METHOD FOR REDUCING DELAYS DURING READ OPERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
11078647
|
Filing Dt:
|
03/11/2005
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
11079726
|
Filing Dt:
|
03/14/2005
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
MEMORY WITH DATA LATCHING CIRCUIT INCLUDING A SELECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
11089860
|
Filing Dt:
|
03/25/2005
|
Publication #:
|
|
Pub Dt:
|
09/28/2006
| | | | |
Title:
|
POWER SAVING REFRESH SCHEME FOR DRAMS WITH SEGMENTED WORD LINE ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
11098780
|
Filing Dt:
|
04/04/2005
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
STACKED DIE PACKAGE
|
|