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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:023806/0001   Pages: 392
Recorded: 01/14/2010
Attorney Dkt #:609612800100
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 249
Page 1 of 3
Pages: 1 2 3
1
Patent #:
Issue Dt:
06/13/2006
Application #:
10841162
Filing Dt:
05/07/2004
Publication #:
Pub Dt:
01/06/2005
Title:
MULTIPLE CHIP SEMICONDUCTOR ARRANGEMENT HAVING ELECTRICAL COMPONENTS IN SEPARATING REGIONS
2
Patent #:
Issue Dt:
12/20/2005
Application #:
10870780
Filing Dt:
06/17/2004
Publication #:
Pub Dt:
12/22/2005
Title:
MTJ STACK WITH CRYSTALLIZATION INHIBITING LAYER
3
Patent #:
Issue Dt:
06/13/2006
Application #:
10873010
Filing Dt:
06/22/2004
Publication #:
Pub Dt:
12/22/2005
Title:
STANDBY CURRENT REDUCTION OVER A PROCESS WINDOW WITH A TRIMMABLE WELL BIAS
4
Patent #:
Issue Dt:
03/06/2007
Application #:
10881598
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
DIGITAL DUTY CYCLE CORRECTOR
5
Patent #:
Issue Dt:
10/30/2007
Application #:
10882592
Filing Dt:
07/01/2004
Publication #:
Pub Dt:
01/05/2006
Title:
CIRCUIT AND METHOD FOR ADJUSTING THRESHOLD DRIFT OVER TEMPERATURE IN A CMOS RECEIVER
6
Patent #:
Issue Dt:
05/29/2007
Application #:
10899253
Filing Dt:
07/26/2004
Publication #:
Pub Dt:
01/26/2006
Title:
ALIGNMENT OF MTJ STACK TO CONDUCTIVE LINES IN THE ABSENCE OF TOPOGRAPHY
7
Patent #:
Issue Dt:
12/27/2005
Application #:
10901765
Filing Dt:
07/29/2004
Publication #:
Pub Dt:
01/06/2005
Title:
SCANNING TIP ORIENTATION ADJUSTMENT METHOD FOR ATOMIC FORCE MICROSCOPY
8
Patent #:
Issue Dt:
10/28/2008
Application #:
10909599
Filing Dt:
08/02/2004
Publication #:
Pub Dt:
02/02/2006
Title:
DEEP ALIGNMENT MARKS ON EDGE CHIPS FOR SUBSEQUENT ALIGNMENT OF OPAQUE LAYERS
9
Patent #:
Issue Dt:
07/31/2007
Application #:
10921766
Filing Dt:
08/19/2004
Publication #:
Pub Dt:
02/23/2006
Title:
SEMICONDUCTOR MEMORY DEVICE COMPRISING MEMORY CELLS WITH FLOATING GATE ELECTRODE AND METHOD OF PRODUCTION
10
Patent #:
Issue Dt:
09/18/2007
Application #:
10928616
Filing Dt:
08/27/2004
Publication #:
Pub Dt:
03/02/2006
Title:
CIRCUIT BOARD AND METHOD FOR PRODUCING A CIRCUIT BOARD
11
Patent #:
Issue Dt:
10/10/2006
Application #:
10930132
Filing Dt:
08/31/2004
Publication #:
Pub Dt:
03/02/2006
Title:
METHOD FOR TESTING THE SERVICEABILITY OF BIT LINES IN A DRAM MEMORY DEVICE
12
Patent #:
Issue Dt:
05/20/2008
Application #:
10938845
Filing Dt:
09/13/2004
Publication #:
Pub Dt:
03/16/2006
Title:
SEMICONDUCTOR CHIP WITH FLEXIBLE CONTACTS AT A FACE
13
Patent #:
NONE
Issue Dt:
Application #:
10938847
Filing Dt:
09/13/2004
Publication #:
Pub Dt:
03/16/2006
Title:
Method for producing a stack of chips, a stack of chips and method for producing a chip for a multi-chip stack
14
Patent #:
Issue Dt:
11/07/2006
Application #:
10939255
Filing Dt:
09/10/2004
Publication #:
Pub Dt:
03/16/2006
Title:
TRANSISTOR, MEMORY CELL ARRAY AND METHOD OF MANUFACTURING A TRANSISTOR
15
Patent #:
Issue Dt:
05/30/2006
Application #:
10940414
Filing Dt:
09/14/2004
Publication #:
Pub Dt:
03/16/2006
Title:
CHARGE-TRAPPING SEMICONDUCTOR MEMORY DEVICE
16
Patent #:
Issue Dt:
01/15/2008
Application #:
10940490
Filing Dt:
09/14/2004
Publication #:
Pub Dt:
03/16/2006
Title:
METHOD AND APPARATUS FOR CHARACTERIZING A RECESS LOCATED ON A SURFACE OF A SUBSTRATE
17
Patent #:
Issue Dt:
06/13/2006
Application #:
10952233
Filing Dt:
09/28/2004
Publication #:
Pub Dt:
03/30/2006
Title:
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
18
Patent #:
Issue Dt:
09/09/2008
Application #:
10952707
Filing Dt:
09/29/2004
Publication #:
Pub Dt:
04/06/2006
Title:
CHARGE-TRAPPING MEMORY CELL AND CHARGE-TRAPPING MEMORY DEVICE
19
Patent #:
Issue Dt:
04/04/2006
Application #:
10953606
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
04/06/2006
Title:
RESISTIVE MEMORY ELEMENT
20
Patent #:
Issue Dt:
02/20/2007
Application #:
10954869
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
03/30/2006
Title:
MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM HAVING BIDIRECTIONAL CLOCK LINES
21
Patent #:
Issue Dt:
02/06/2007
Application #:
10955177
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
03/30/2006
Title:
MEMORY SYSTEM WITH TWO CLOCK LINES AND A MEMORY DEVICE
22
Patent #:
Issue Dt:
09/19/2006
Application #:
10957803
Filing Dt:
10/04/2004
Publication #:
Pub Dt:
04/06/2006
Title:
FLEXIBLE BLENDER
23
Patent #:
Issue Dt:
10/21/2008
Application #:
10958464
Filing Dt:
10/05/2004
Publication #:
Pub Dt:
04/06/2006
Title:
GATE LAYER DIODE METHOD AND APPARATUS
24
Patent #:
Issue Dt:
08/22/2006
Application #:
10964102
Filing Dt:
10/13/2004
Publication #:
Pub Dt:
04/13/2006
Title:
MEASURING FLARE IN SEMICONDUCTOR LITHOGRAPHY
25
Patent #:
Issue Dt:
09/05/2006
Application #:
10966776
Filing Dt:
10/15/2004
Publication #:
Pub Dt:
04/20/2006
Title:
COMBINED RECEIVER AND LATCH
26
Patent #:
Issue Dt:
02/27/2007
Application #:
10967768
Filing Dt:
10/18/2004
Publication #:
Pub Dt:
04/20/2006
Title:
DQS FOR DATA FROM A MEMORY ARRAY
27
Patent #:
Issue Dt:
08/01/2006
Application #:
10969343
Filing Dt:
10/21/2004
Publication #:
Pub Dt:
04/27/2006
Title:
SIMULATING A FLOATING WORDLINE CONDITION IN A MEMORY DEVICE, AND RELATED TECHNIQUES
28
Patent #:
Issue Dt:
05/16/2006
Application #:
10973389
Filing Dt:
10/27/2004
Publication #:
Pub Dt:
04/27/2006
Title:
METHOD AND APPARATUS COMPENSATING FOR FREQUENCY DRIFT IN A DELAY LOCKED LOOP
29
Patent #:
Issue Dt:
04/10/2007
Application #:
10974019
Filing Dt:
10/27/2004
Publication #:
Pub Dt:
04/27/2006
Title:
SEMICONDUCTOR MEMORY HAVING TRI-STATE DRIVER DEVICE
30
Patent #:
Issue Dt:
04/03/2007
Application #:
10974521
Filing Dt:
10/27/2004
Publication #:
Pub Dt:
04/27/2006
Title:
CIRCUIT HAVING DELAY LOCKED LOOP FOR CORRECTING OFF CHIP DRIVER DUTY DISTORTION
31
Patent #:
Issue Dt:
10/03/2006
Application #:
10974564
Filing Dt:
10/27/2004
Publication #:
Pub Dt:
04/27/2006
Title:
VARIABLE DELAY LINE USING TWO BLENDER DELAYS
32
Patent #:
Issue Dt:
08/22/2006
Application #:
10976159
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
05/04/2006
Title:
METHOD FOR DETERMINING AN OPTIMAL ABSORBER STACK GEOMETRY OF A LITHOGRAPHIC REFLECTION MASK
33
Patent #:
Issue Dt:
07/03/2007
Application #:
10978216
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
05/04/2006
Title:
SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING A SEMICONDUCTOR DEVICE
34
Patent #:
Issue Dt:
01/09/2007
Application #:
10980301
Filing Dt:
11/04/2004
Publication #:
Pub Dt:
05/18/2006
Title:
APPARATUS AND METHOD FOR MAKING GROUND CONNECTION
35
Patent #:
Issue Dt:
08/15/2006
Application #:
10981947
Filing Dt:
11/05/2004
Publication #:
Pub Dt:
05/11/2006
Title:
DUTY DISTORTION DETECTOR
36
Patent #:
Issue Dt:
05/23/2006
Application #:
10986767
Filing Dt:
11/15/2004
Publication #:
Pub Dt:
05/18/2006
Title:
SEMICONDUCTOR MEMORY SYSTEM AND METHOD FOR THE TRANSFER OF WRITE AND READ DATA SIGNALS IN A SEMICONDUCTOR MEMORY SYSTEM
37
Patent #:
Issue Dt:
09/04/2007
Application #:
10987812
Filing Dt:
11/12/2004
Publication #:
Pub Dt:
05/18/2006
Title:
MEMORY ACCESS USING MULTIPLE SETS OF ADDRESS/DATA LINES
38
Patent #:
Issue Dt:
01/09/2007
Application #:
10988787
Filing Dt:
11/15/2004
Publication #:
Pub Dt:
05/18/2006
Title:
SENSE AMPLIFIER BITLINE BOOST CIRCUIT
39
Patent #:
Issue Dt:
01/02/2007
Application #:
10990420
Filing Dt:
11/18/2004
Publication #:
Pub Dt:
05/18/2006
Title:
METHOD FOR FULL WAFER CONTACT PROBING, WAFER DESIGN AND PROBE CARD DEVICE WITH REDUCED PROBE CONTACTS
40
Patent #:
Issue Dt:
01/16/2007
Application #:
10991434
Filing Dt:
11/19/2004
Publication #:
Pub Dt:
05/25/2006
Title:
FLEXIBLE INTERNAL ADDRESS COUNTING METHOD AND APPARATUS
41
Patent #:
Issue Dt:
02/13/2007
Application #:
10992826
Filing Dt:
11/19/2004
Publication #:
Pub Dt:
05/25/2006
Title:
TWIN-CELL BIT LINE SENSING CONFIGURATION
42
Patent #:
Issue Dt:
07/25/2006
Application #:
10993250
Filing Dt:
11/19/2004
Publication #:
Pub Dt:
05/25/2006
Title:
RANDOM ACCESS MEMORY HAVING FAST COLUMN ACCESS
43
Patent #:
Issue Dt:
03/27/2007
Application #:
10994977
Filing Dt:
11/22/2004
Publication #:
Pub Dt:
05/25/2006
Title:
ESD PROTECTION APPARATUS FOR AN ELECTRICAL DEVICE
44
Patent #:
Issue Dt:
09/26/2006
Application #:
10995643
Filing Dt:
11/23/2004
Publication #:
Pub Dt:
05/25/2006
Title:
ENERGY ADJUSTED WRITE PULSES IN PHASE-CHANGE MEMORIES
45
Patent #:
Issue Dt:
04/18/2006
Application #:
10995644
Filing Dt:
11/23/2004
Title:
MULTI-PULSE RESET WRITE SCHEME FOR PHASE-CHANGE MEMORIES
46
Patent #:
Issue Dt:
03/14/2006
Application #:
10996669
Filing Dt:
11/24/2004
Publication #:
Pub Dt:
07/14/2005
Title:
POLYELECTROLYTE DISPENSING POLISHING PAD
47
Patent #:
Issue Dt:
04/08/2008
Application #:
10998975
Filing Dt:
11/30/2004
Publication #:
Pub Dt:
06/01/2006
Title:
TRANSISTOR ARRAY FOR SEMICONDUCTOR MEMORY DEVICES AND METHOD FOR FABRICATING A VERTICAL CHANNEL TRANSISTOR ARRAY
48
Patent #:
Issue Dt:
11/25/2008
Application #:
11000323
Filing Dt:
11/30/2004
Publication #:
Pub Dt:
06/01/2006
Title:
CIRCUIT AND METHOD FOR TRANSMITTING A SIGNAL
49
Patent #:
Issue Dt:
12/19/2006
Application #:
11000335
Filing Dt:
11/30/2004
Publication #:
Pub Dt:
06/01/2006
Title:
NON-VOLATILE SEMICONDUCTOR MEMORY
50
Patent #:
Issue Dt:
11/20/2007
Application #:
11000350
Filing Dt:
11/30/2004
Publication #:
Pub Dt:
06/01/2006
Title:
CHARGE-TRAPPING MEMORY CELL AND METHOD FOR PRODUCTION
51
Patent #:
Issue Dt:
02/19/2008
Application #:
11002148
Filing Dt:
12/03/2004
Publication #:
Pub Dt:
06/08/2006
Title:
MEMORY MODULE WITH A CLOCK SIGNAL REGENERATION CIRCUIT AND A REGISTER CIRCUIT FOR TEMPORARILY STORING THE INCOMING COMMAND AND ADDRESS SIGNALS
52
Patent #:
Issue Dt:
11/21/2006
Application #:
11004881
Filing Dt:
12/07/2004
Publication #:
Pub Dt:
06/08/2006
Title:
MEMORY CELL ARRAY
53
Patent #:
Issue Dt:
04/25/2006
Application #:
11005045
Filing Dt:
12/07/2004
Title:
MEMORY DEVICE AND METHOD OF MANUFACTURING A MEMORY DEVICE
54
Patent #:
Issue Dt:
04/11/2006
Application #:
11006484
Filing Dt:
12/07/2004
Title:
METHOD FOR PRODUCTION OF CHARGE-TRAPPING MEMORY DEVICES
55
Patent #:
Issue Dt:
04/10/2007
Application #:
11006865
Filing Dt:
12/08/2004
Publication #:
Pub Dt:
06/08/2006
Title:
INTEGRATED DRAM MEMORY DEVICE
56
Patent #:
Issue Dt:
09/04/2007
Application #:
11010182
Filing Dt:
12/10/2004
Publication #:
Pub Dt:
06/15/2006
Title:
MEMORY RANK DECODER FOR A MULTI-RANK DUAL INLINE MEMORY MODULE (DIMM)
57
Patent #:
Issue Dt:
04/03/2007
Application #:
11010942
Filing Dt:
12/10/2004
Publication #:
Pub Dt:
06/15/2006
Title:
STACKED DRAM MEMORY CHIP FOR A DUAL INLINE MEMORY MODULE (DIMM)
58
Patent #:
Issue Dt:
04/24/2007
Application #:
11011038
Filing Dt:
12/15/2004
Publication #:
Pub Dt:
06/15/2006
Title:
METHOD FOR FABRICATING BOTTOM ELECTRODES OF STACKED CAPACITOR MEMORY CELLS AND METHOD FOR CLEANING AND DRYING A SEMICONDUCTOR WAFER
59
Patent #:
Issue Dt:
03/28/2006
Application #:
11011039
Filing Dt:
12/15/2004
Title:
METHOD FOR FABRICATING BOTTOM ELECTRODES OF STACKED CAPACITOR MEMORY CELLS
60
Patent #:
Issue Dt:
01/13/2009
Application #:
11011040
Filing Dt:
12/15/2004
Publication #:
Pub Dt:
12/14/2006
Title:
6F2 ACCESS TRANSISTOR ARRANGEMENT AND SEMICONDUCTOR MEMORY DEVICE
61
Patent #:
Issue Dt:
09/04/2007
Application #:
11012777
Filing Dt:
12/14/2004
Publication #:
Pub Dt:
06/15/2006
Title:
METHOD TO IMPROVE CURRENT AND SLEW RATE RATIO OF OFF-CHIP DRIVERS
62
Patent #:
Issue Dt:
01/30/2007
Application #:
11013582
Filing Dt:
12/16/2004
Publication #:
Pub Dt:
06/22/2006
Title:
MEMORY CIRCUIT RECEIVERS ACTIVATED BY ENABLE CIRCUIT
63
Patent #:
Issue Dt:
08/28/2007
Application #:
11013870
Filing Dt:
12/16/2004
Publication #:
Pub Dt:
06/22/2006
Title:
MEMORY HAVING TEST CIRCUIT
64
Patent #:
Issue Dt:
11/07/2006
Application #:
11017194
Filing Dt:
12/20/2004
Publication #:
Pub Dt:
06/22/2006
Title:
CHARGE-TRAPPING MEMORY DEVICE AND METHOD OF PRODUCTION
65
Patent #:
Issue Dt:
09/18/2007
Application #:
11018313
Filing Dt:
12/21/2004
Publication #:
Pub Dt:
06/22/2006
Title:
MEMORY ACCESS USING MULTIPLE ACTIVATED MEMORY CELL ROWS
66
Patent #:
Issue Dt:
12/12/2006
Application #:
11021370
Filing Dt:
12/23/2004
Publication #:
Pub Dt:
06/29/2006
Title:
DELAY LOCKED LOOP USING SYNCHRONOUS MIRROR DELAY
67
Patent #:
Issue Dt:
10/17/2006
Application #:
11022202
Filing Dt:
12/22/2004
Publication #:
Pub Dt:
06/22/2006
Title:
MEMORY HAVING INTERNAL COLUMN COUNTER FOR COMPRESSION TEST MODE
68
Patent #:
Issue Dt:
09/04/2007
Application #:
11024932
Filing Dt:
12/30/2004
Publication #:
Pub Dt:
07/06/2006
Title:
OPTO-ELECTRONIC MEMORY ELEMENT ON THE BASIS OF ORGANIC METALLOPORPHYRIN MOLECULES
69
Patent #:
Issue Dt:
08/07/2007
Application #:
11025561
Filing Dt:
12/29/2004
Publication #:
Pub Dt:
06/29/2006
Title:
MEMORY WITH SELECTABLE SINGLE CELL OR TWIN CELL CONFIGURATION
70
Patent #:
Issue Dt:
01/08/2008
Application #:
11031716
Filing Dt:
01/07/2005
Publication #:
Pub Dt:
07/13/2006
Title:
HIGH DIELECTRIC CONSTANT MATERIALS
71
Patent #:
Issue Dt:
06/12/2007
Application #:
11032459
Filing Dt:
01/10/2005
Publication #:
Pub Dt:
07/13/2006
Title:
DUTY CYCLE CORRECTOR
72
Patent #:
Issue Dt:
12/05/2006
Application #:
11034006
Filing Dt:
01/12/2005
Publication #:
Pub Dt:
07/13/2006
Title:
DUTY CYCLE DETECTOR WITH FIRST, SECOND, AND THIRD VALUES
73
Patent #:
Issue Dt:
09/25/2007
Application #:
11038465
Filing Dt:
01/21/2005
Publication #:
Pub Dt:
07/27/2006
Title:
SEMICONDUCTOR DEVICE
74
Patent #:
Issue Dt:
07/24/2007
Application #:
11039665
Filing Dt:
01/20/2005
Publication #:
Pub Dt:
07/27/2006
Title:
INTERNAL REFERENCE VOLTAGE GENERATION FOR INTEGRATED CIRCUIT TESTING
75
Patent #:
Issue Dt:
09/18/2007
Application #:
11039740
Filing Dt:
01/20/2005
Publication #:
Pub Dt:
07/20/2006
Title:
STORAGE CAPACITOR AND METHOD OF MANUFACTURING A STORAGE CAPACITOR
76
Patent #:
Issue Dt:
04/11/2006
Application #:
11040176
Filing Dt:
01/21/2005
Title:
SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
77
Patent #:
Issue Dt:
07/15/2008
Application #:
11040630
Filing Dt:
01/21/2005
Publication #:
Pub Dt:
07/27/2006
Title:
INTEGRATED CIRCUIT INCLUDING A MEMORY HAVING LOW INITIAL LATENCY
78
Patent #:
Issue Dt:
04/24/2007
Application #:
11043950
Filing Dt:
01/28/2005
Publication #:
Pub Dt:
08/03/2006
Title:
METHOD OF TREATING A STRUCTURED SURFACE
79
Patent #:
Issue Dt:
11/01/2011
Application #:
11044721
Filing Dt:
01/28/2005
Publication #:
Pub Dt:
08/03/2006
Title:
METHOD FOR PRODUCING A DIELECTRIC MATERIAL ON A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
80
Patent #:
Issue Dt:
01/30/2007
Application #:
11046065
Filing Dt:
01/28/2005
Publication #:
Pub Dt:
08/03/2006
Title:
TEST DATA TOPOLOGY WRITE TO MEMORY USING LATCHED SENSE AMPLIFIER DATA AND ROW ADDRESS SCRAMBLING
81
Patent #:
Issue Dt:
05/08/2007
Application #:
11046160
Filing Dt:
01/28/2005
Publication #:
Pub Dt:
08/17/2006
Title:
MEMORY DEVICE HAVING COMPONENTS FOR TRANSMITTING AND RECEIVING SIGNALS SYNCHRONOUSLY
82
Patent #:
Issue Dt:
05/22/2007
Application #:
11048185
Filing Dt:
02/01/2005
Publication #:
Pub Dt:
08/03/2006
Title:
DUTY CYCLE CORRECTOR
83
Patent #:
NONE
Issue Dt:
Application #:
11048186
Filing Dt:
02/01/2005
Publication #:
Pub Dt:
08/03/2006
Title:
Pillar phase change memory cell
84
Patent #:
Issue Dt:
07/18/2006
Application #:
11049857
Filing Dt:
02/04/2005
Publication #:
Pub Dt:
08/10/2006
Title:
METHODS AND APPARATUS FOR IMPLEMENTING A POWER DOWN IN A MEMORY DEVICE
85
Patent #:
Issue Dt:
04/29/2008
Application #:
11051257
Filing Dt:
02/04/2005
Publication #:
Pub Dt:
08/10/2006
Title:
METHOD FOR INTERCONNECTING SEMICONDUCTOR COMPONENTS WITH SUBSTRATES AND CONTACT MEANS
86
Patent #:
Issue Dt:
12/02/2008
Application #:
11051969
Filing Dt:
02/04/2005
Publication #:
Pub Dt:
08/10/2006
Title:
DISSOCIATED FABRICATION OF PACKAGES AND CHIPS OF INTEGRATED CIRCUITS
87
Patent #:
Issue Dt:
04/22/2008
Application #:
11054853
Filing Dt:
02/10/2005
Publication #:
Pub Dt:
08/10/2006
Title:
INTEGRATED CIRCUIT HAVING A MEMORY INCLUDING A LOW-K DIELECTRIC MATERIAL FOR THERMAL ISOLATION
88
Patent #:
Issue Dt:
10/23/2007
Application #:
11058723
Filing Dt:
02/15/2005
Publication #:
Pub Dt:
08/17/2006
Title:
ENHANCED MEGASONIC BASED CLEAN USING AN ALTERNATIVE CLEANING CHEMISTRY
89
Patent #:
Issue Dt:
08/21/2007
Application #:
11060737
Filing Dt:
02/18/2005
Publication #:
Pub Dt:
08/24/2006
Title:
METHOD AND APPARATUS FOR SEMICONDUCTOR TESTING UTILIZING DIES WITH INTEGRATED CIRCUIT
90
Patent #:
Issue Dt:
03/06/2007
Application #:
11061314
Filing Dt:
02/18/2005
Publication #:
Pub Dt:
08/24/2006
Title:
CHARGE-TRAPPING MEMORY DEVICE AND METHOD FOR PRODUCTION
91
Patent #:
Issue Dt:
07/24/2007
Application #:
11065196
Filing Dt:
02/24/2005
Publication #:
Pub Dt:
08/24/2006
Title:
RANDOM ACCESS MEMORY INCLUDING SELECTIVE ACTIVATION OF SELECT LINE
92
Patent #:
Issue Dt:
03/07/2006
Application #:
11066320
Filing Dt:
02/25/2005
Title:
METHOD AND SYSTEM FOR FABRICATING FREE-STANDING NANOSTRUCTURES
93
Patent #:
Issue Dt:
11/06/2007
Application #:
11066555
Filing Dt:
02/28/2005
Publication #:
Pub Dt:
08/31/2006
Title:
CHIP STACK EMPLOYING A FLEX CIRCUIT
94
Patent #:
Issue Dt:
05/01/2007
Application #:
11066731
Filing Dt:
02/25/2005
Publication #:
Pub Dt:
08/31/2006
Title:
SEMICONDUCTOR DEVICE AND METHOD OF OPERATING A SEMICONDUCTOR DEVICE
95
Patent #:
Issue Dt:
04/24/2007
Application #:
11068582
Filing Dt:
02/28/2005
Publication #:
Pub Dt:
08/31/2006
Title:
DATA STROBE SYNCHRONIZATION FOR DRAM DEVICES
96
Patent #:
Issue Dt:
05/29/2007
Application #:
11073523
Filing Dt:
03/08/2005
Publication #:
Pub Dt:
09/14/2006
Title:
MEMORY DEVICE HAVING OFF-CHIP DRIVER ENABLE CIRCUIT AND METHOD FOR REDUCING DELAYS DURING READ OPERATIONS
97
Patent #:
Issue Dt:
07/29/2008
Application #:
11078647
Filing Dt:
03/11/2005
Publication #:
Pub Dt:
09/14/2006
Title:
SEMICONDUCTOR MEMORY
98
Patent #:
Issue Dt:
10/10/2006
Application #:
11079726
Filing Dt:
03/14/2005
Publication #:
Pub Dt:
09/14/2006
Title:
MEMORY WITH DATA LATCHING CIRCUIT INCLUDING A SELECTOR
99
Patent #:
Issue Dt:
01/30/2007
Application #:
11089860
Filing Dt:
03/25/2005
Publication #:
Pub Dt:
09/28/2006
Title:
POWER SAVING REFRESH SCHEME FOR DRAMS WITH SEGMENTED WORD LINE ARCHITECTURE
100
Patent #:
Issue Dt:
02/05/2008
Application #:
11098780
Filing Dt:
04/04/2005
Publication #:
Pub Dt:
10/05/2006
Title:
STACKED DIE PACKAGE
Assignor
1
Exec Dt:
04/25/2006
Assignee
1
GUSTAV-HEINEMANN-RING 212
MUNICH, GERMANY 81739
Correspondence name and address
JONATHAN BOCKMAN
C/O MORRISON & FOERSTER LLP
1650 TYSONS BOULEVARD SUITE 400
MCLEAN, VA 22102

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