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Patent Assignment Details
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Reel/Frame:027234/0001   Pages: 19
Recorded: 11/16/2011
Attorney Dkt #:HYNIX
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 20
1
Patent #:
Issue Dt:
08/15/1995
Application #:
08341892
Filing Dt:
11/15/1994
Title:
METHOD FOR FORMING A TWO-LAYERED POLYSILICON GATER ELECTRODE IN A SEMICONDUCTOR DEVICE USING GRAIN BOUNDARIES
2
Patent #:
Issue Dt:
08/12/1997
Application #:
08494645
Filing Dt:
06/23/1995
Title:
WIRING STRUCTURE FOR SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR
3
Patent #:
Issue Dt:
07/14/1998
Application #:
08764083
Filing Dt:
12/06/1996
Title:
SUB WORD LINE DRIVING CIRCUIT AND A SEMICONDUCTOR MEMORY DEVICE USING THE SAME
4
Patent #:
Issue Dt:
07/17/2001
Application #:
08773174
Filing Dt:
12/27/1996
Title:
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
5
Patent #:
Issue Dt:
08/18/1998
Application #:
08796219
Filing Dt:
02/07/1997
Title:
SYNCHRONOUS MEMORY DEVICE HAVING DUAL INPUT REGISTERS OF PIPELINE STRUCTURE IN DATA PATH
6
Patent #:
Issue Dt:
02/23/1999
Application #:
08828817
Filing Dt:
02/06/1997
Title:
WORD LINE DRIVER FOR SEMICONDUCTOR MEMORIES
7
Patent #:
Issue Dt:
05/02/2000
Application #:
08862926
Filing Dt:
05/27/1997
Title:
WIRING STRUCTURE FOR SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR
8
Patent #:
Issue Dt:
11/10/1998
Application #:
08887280
Filing Dt:
07/02/1997
Title:
SUB WORD LINE DRIVING CIRCUIT AND A SEMICONDUCTOR MEMORY DEVICE USING THE SAME
9
Patent #:
Issue Dt:
05/16/2000
Application #:
09106308
Filing Dt:
06/29/1998
Title:
SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY IN A SEMICONDUCTOR MEMORY DEVICE
10
Patent #:
Issue Dt:
05/23/2000
Application #:
09143096
Filing Dt:
08/28/1998
Title:
METHOD FOR MANUFACTURING A CAPACITOR OF A SEMICONDUCTOR DEVICE
11
Patent #:
Issue Dt:
01/04/2000
Application #:
09182943
Filing Dt:
10/29/1998
Title:
WORD LINE DRIVER FOR SEMICONDUCTOR MEMORIES
12
Patent #:
Issue Dt:
12/03/2002
Application #:
09747886
Filing Dt:
12/22/2000
Publication #:
Pub Dt:
08/16/2001
Title:
DELAY LOCKED LOOP WITH DELAY CONTROL UNIT FOR NOISE ELIMINATION
13
Patent #:
Issue Dt:
12/25/2001
Application #:
09867584
Filing Dt:
05/31/2001
Publication #:
Pub Dt:
10/04/2001
Title:
Semiconductor device and method for fabricating the same
14
Patent #:
Issue Dt:
11/04/2003
Application #:
10253779
Filing Dt:
09/25/2002
Publication #:
Pub Dt:
05/01/2003
Title:
CMOS OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
15
Patent #:
Issue Dt:
06/26/2007
Application #:
10511253
Filing Dt:
04/25/2005
Publication #:
Pub Dt:
10/13/2005
Title:
MEMORY CHIP ARCHITECTURE HAVING NON-RECTANGULAR MEMORY BANKS AND METHOD FOR ARRANGING MEMORY BANKS
16
Patent #:
Issue Dt:
07/27/2004
Application #:
10663910
Filing Dt:
09/17/2003
Publication #:
Pub Dt:
04/01/2004
Title:
CMOS OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
17
Patent #:
Issue Dt:
11/11/2008
Application #:
11321877
Filing Dt:
12/30/2005
Publication #:
Pub Dt:
11/02/2006
Title:
SEMICONDUCTOR MEMORY DEVICE
18
Patent #:
Issue Dt:
04/08/2008
Application #:
11396193
Filing Dt:
03/30/2006
Publication #:
Pub Dt:
10/19/2006
Title:
SEMICONDUCTOR MEMORY DEVICE
19
Patent #:
Issue Dt:
02/10/2009
Application #:
11647402
Filing Dt:
12/29/2006
Publication #:
Pub Dt:
01/03/2008
Title:
SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF
20
Patent #:
Issue Dt:
11/06/2012
Application #:
11809244
Filing Dt:
05/30/2007
Publication #:
Pub Dt:
01/03/2008
Title:
MEMORY CHIP ARCHITECTURE HAVING NON-RECTANGULAR MEMORY BANKS AND METHOD FOR ARRANGING MEMORY BANKS
Assignor
1
Exec Dt:
08/22/2011
Assignee
1
44 CHIPMAN HILL
SUITE 1000
SAINT JOHN, NB, CANADA E2L 2A9
Correspondence name and address
MOSAID CORPORATION LTD.
5700 GRANITE PARKWAY
SUITE 960
PLANO, TX 75024

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