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Total properties:
25
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09006495
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Filing Dt:
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01/13/1998
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Title:
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TRUNGSTEN PLUG FORMATION
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09163310
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Filing Dt:
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09/30/1998
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Title:
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SELF-ALIGNING POLY 1 ONO DIELECTRIC FOR NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09199772
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Filing Dt:
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11/25/1998
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Title:
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METHOD FOR IMPROVING ELECTROSTATIC DISCHARGE ( ESD) ROBUSTNESS
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09252185
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Filing Dt:
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02/18/1999
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Title:
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LOW DIELECTRIC SEMICONDUCTOR DEVICE WITH RIGID, CONDUCTIVELY LINED INTERCONNECTION SYSTEM
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09252854
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Filing Dt:
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09/08/1998
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Title:
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NOVEL PROCESS FOR RELIABLE ULTRATHIN OXYNITRIDE FORMATION
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09352801
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Filing Dt:
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07/13/1999
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Title:
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THIN FLOATING GATE AND CONDUCTIVE SELECT GATE IN SITU DOPED AMORPHOUS SILICON MATERIAL FOR NAND TYPE FLASH MEMORY DEVICE APPLICATIONS
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09353267
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Filing Dt:
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07/14/1999
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Title:
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REDUCTION OF VOLTAGE STRESS ACROSS A GATE OXIDE AND ACROSS A JUNCTION WITHIN A HIGH VOLTAGE TRANSISTOR OF AN ERASABLE MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09376658
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Filing Dt:
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08/18/1999
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Title:
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METHOD FOR PROTECTING GATE EDGES FROM CHARGE GAIN/LOSS IN SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09385550
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Filing Dt:
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08/30/1999
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Title:
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USING POLYSILICON FUSE FOR IC PROGRAMMING
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09412544
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Filing Dt:
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10/05/1999
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Title:
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METHOD AND SYSTEM FOR REDUCING SHORT CHANNEL EFFECTS IN A MEMORY DEVICE
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09417131
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Filing Dt:
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10/13/1999
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Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH REDUCED ARC LOSS IN PERIPHERAL CIRCUITRY REGION
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09426430
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Filing Dt:
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10/25/1999
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Title:
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METHOD OF FABRICATING AN ONO DIELECTRIC BY NITRIDATION FOR MNOS MEMORY CELLS
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09427404
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Filing Dt:
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10/25/1999
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Title:
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PROCESS FOR FABRICATING A BIT-LINE USING BURIED DIFFUSION ISOLATION
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09461376
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Filing Dt:
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12/15/1999
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Title:
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BIASING METHOD AND STRUCTURE FOR REDUCING BAND-TO-BAND AND/OR AVALANCHE CURRENTS DURING THE ERASE OF FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09476584
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Filing Dt:
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01/03/2000
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Title:
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USE OF ETCH TO BLUNT GATE CORNERS
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09489232
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Filing Dt:
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01/21/2000
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Title:
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High speed charging of core cell drain lines in a memory device
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09495214
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Filing Dt:
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01/31/2000
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Title:
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Method to reduce read gate disturb for flash eeprom application
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09501159
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Filing Dt:
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02/09/2000
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Title:
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Voltage boost reset circuit for a flash memory
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09504186
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Filing Dt:
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02/15/2000
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Title:
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Two-stage pipeline sensing for page mode flash memory
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09505259
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Filing Dt:
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02/16/2000
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Title:
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Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09511652
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Filing Dt:
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02/22/2000
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Title:
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Symmetrical program and erase scheme to improve erase time degradation in NAND devices
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09514560
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Filing Dt:
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02/28/2000
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Title:
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System for erasing a memory cell
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09526239
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Filing Dt:
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03/15/2000
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Title:
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Multiple bank simultaneous operation for a flash memory
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09627565
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Filing Dt:
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07/28/2000
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Title:
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Dual bit isolation scheme for flash memory devices having polysilicon floating gates
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09693650
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Filing Dt:
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10/21/2000
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Title:
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Self-limiting multi-level programming states
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