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Total properties:
29
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Patent #:
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Issue Dt:
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03/12/2013
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Application #:
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12913716
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Filing Dt:
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10/27/2010
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Title:
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BCH DATA CORRECTION SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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04/22/2014
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Application #:
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13023336
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Filing Dt:
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02/08/2011
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Title:
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NONVOLATILE MEMORY CONTROLLER WITH TWO-STAGE ERROR CORRECTION TECHNIQUE FOR ENHANCED RELIABILITY
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Patent #:
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Issue Dt:
|
11/19/2013
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Application #:
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13052008
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Filing Dt:
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03/18/2011
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Title:
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NONVOLATILE MEMORY CONTROLLER WITH HOST CONTROLLER INTERFACE FOR RETRIEVING AND DISPATCHING NONVOLATILE MEMORY COMMANDS IN A DISTRIBUTED MANNER
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Patent #:
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Issue Dt:
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10/08/2013
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Application #:
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13052388
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Filing Dt:
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03/21/2011
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Title:
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INTERRUPT TECHNIQUE FOR A NONVOLATILE MEMORY CONTROLLER
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Patent #:
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Issue Dt:
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12/03/2013
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Application #:
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13052835
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Filing Dt:
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03/21/2011
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Title:
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SYSTEM AND METHOD FOR GENERATING PARITY DATA IN A NONVOLATILE MEMORY CONTROLLER BY USING A DISTRIBUTED PROCESSING TECHNIQUE
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Patent #:
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Issue Dt:
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02/18/2014
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Application #:
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13107265
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Filing Dt:
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05/13/2011
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Title:
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SYSTEM AND METHOD FOR ROUTING A DATA MESSAGE THROUGH A MESSAGE NETWORK
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Patent #:
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Issue Dt:
|
04/08/2014
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Application #:
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13287443
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Filing Dt:
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11/02/2011
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Title:
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ERROR CORRECTION CODE TECHNIQUE FOR IMPROVING READ STRESS ENDURANCE
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Patent #:
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Issue Dt:
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02/18/2014
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Application #:
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13434770
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Filing Dt:
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03/29/2012
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Title:
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NONVOLATILE MEMORY CONTROLLER WITH CONCATENATED ERROR CORRECTION CODES
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Patent #:
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Issue Dt:
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12/31/2013
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Application #:
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13435572
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Filing Dt:
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03/30/2012
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Title:
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NONVOLATILE MEMORY CONTROLLER WITH ERROR DETECTION FOR CONCATENATED ERROR CORRECTION CODES
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Patent #:
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Issue Dt:
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02/02/2016
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Application #:
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13787351
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Filing Dt:
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03/06/2013
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Title:
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METHOD AND APPARATUS FOR DRIVING A LASER DIODE
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Patent #:
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Issue Dt:
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12/29/2015
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Application #:
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14132229
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Filing Dt:
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12/18/2013
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Title:
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THRESHOLD VOLTAGE ADJUSTMENT IN SOLID STATE MEMORY
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Patent #:
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Issue Dt:
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10/27/2015
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Application #:
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14144857
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Filing Dt:
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12/31/2013
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Title:
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METHOD AND SYSTEM FOR DECODING ENCODED DATA STORED IN A NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
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01/12/2016
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Application #:
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14165135
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Filing Dt:
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01/27/2014
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Publication #:
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Pub Dt:
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09/18/2014
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Title:
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SYSTEM AND METHOD WITH REFERENCE VOLTAGE PARTITIONING FOR LOW DENSITY PARITY CHECK DECODING
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Patent #:
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Issue Dt:
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01/12/2016
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Application #:
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14168222
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Filing Dt:
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01/30/2014
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Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
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Title:
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SYSTEM AND METHOD FOR RANDOM NOISE GENERATION
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Patent #:
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Issue Dt:
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04/26/2016
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Application #:
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14186786
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Filing Dt:
|
02/21/2014
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|
Title:
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FORWARD ERROR CORRECTION DECODER AND METHOD THEREFOR
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|
|
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Patent #:
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|
Issue Dt:
|
03/07/2017
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Application #:
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14210067
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Filing Dt:
|
03/13/2014
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Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
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Title:
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SYSTEM AND METHOD FOR HIGHER QUALITY LOG LIKELIHOOD RATIOS IN LDPC DECODING
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|
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Patent #:
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|
Issue Dt:
|
08/29/2017
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Application #:
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14322327
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Filing Dt:
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07/02/2014
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|
Title:
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MEMORY SYSTEM WITH HIGH SPEED NON-VOLATILE MEMORY BACKUP USING PRE-AGED FLASH MEMORY DEVICES
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|
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Patent #:
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Issue Dt:
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08/16/2016
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Application #:
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14325212
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Filing Dt:
|
07/07/2014
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Publication #:
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Pub Dt:
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01/07/2016
| | | | |
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Title:
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SYSTEM AND METHOD FOR MEMORY BLOCK POOL WEAR LEVELING
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Patent #:
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Issue Dt:
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04/05/2016
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Application #:
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14475757
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Filing Dt:
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09/03/2014
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Publication #:
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Pub Dt:
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03/03/2016
| | | | |
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Title:
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NONVOLATILE MEMORY SYSTEM THAT USES PROGRAMMING TIME TO REDUCE BIT ERRORS
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|
|
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Patent #:
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|
Issue Dt:
|
09/20/2016
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Application #:
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14557214
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Filing Dt:
|
12/01/2014
|
|
Title:
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HIGH QUALITY LOG LIKELIHOOD RATIOS DETERMINED USING TWO-INDEX LOOK-UP TABLE
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Patent #:
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Issue Dt:
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03/21/2017
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Application #:
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14606579
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Filing Dt:
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01/27/2015
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Title:
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SYSTEM AND METHOD FOR BOOST FLOOR MITIGATION
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Patent #:
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|
Issue Dt:
|
10/24/2017
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Application #:
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14812891
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Filing Dt:
|
07/29/2015
|
|
Title:
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NONVOLATILE MEMORY SYSTEM WITH READ CIRCUIT FOR PERFORMING READS USING THRESHOLD VOLTAGE SHIFT READ INSTRUCTION
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|
|
|
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Patent #:
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|
Issue Dt:
|
03/06/2018
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Application #:
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14861451
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Filing Dt:
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09/22/2015
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|
Title:
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HARDWARE BASED XIP EXIT SEQUENCE TO ENABLE XIP MODE OPERATION ON SPI BOOT INTERFACE
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|
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Patent #:
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|
Issue Dt:
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06/26/2018
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Application #:
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14974803
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Filing Dt:
|
12/18/2015
|
|
Publication #:
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Pub Dt:
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06/22/2017
| | | | |
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Title:
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METHOD OF CONFIGURING MEMORY CELLS IN A SOLID STATE DRIVE BASED ON READ/WRITE ACTIVITY AND CONTROLLER THEREFOR
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|
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Patent #:
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Issue Dt:
|
04/18/2017
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Application #:
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14989276
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Filing Dt:
|
01/06/2016
|
|
Title:
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METHOD AND APPARATUS FOR DRIVING A LASER DIODE
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|
|
|
Patent #:
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|
Issue Dt:
|
10/11/2016
|
Application #:
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14991323
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Filing Dt:
|
01/08/2016
|
|
Title:
|
FORWARD ERROR CORRECTION DECODER AND METHOD THEREFOR
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/20/2018
|
Application #:
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15042125
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Filing Dt:
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02/11/2016
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Publication #:
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Pub Dt:
|
07/27/2017
| | | | |
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Title:
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NONVOLATILE MEMORY SYSTEM WITH PROGRAM STEP MANAGER AND METHOD FOR PROGRAM STEP MANAGEMENT
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Patent #:
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Issue Dt:
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02/06/2018
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Application #:
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15370391
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Filing Dt:
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12/06/2016
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Publication #:
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Pub Dt:
|
06/15/2017
| | | | |
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Title:
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NONVOLATILE MEMORY SYSTEM WITH ERASE SUSPEND CIRCUIT AND METHOD FOR ERASE SUSPEND MANAGEMENT
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Patent #:
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Issue Dt:
|
02/13/2018
|
Application #:
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15396721
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Filing Dt:
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01/02/2017
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Publication #:
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Pub Dt:
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07/06/2017
| | | | |
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Title:
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METHOD AND APPARATUS WITH PROGRAM SUSPEND USING TEST MODE
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