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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:045216/0020   Pages: 334
Recorded: 02/01/2018
Attorney Dkt #:43172.01200
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 3463
Page 13 of 35
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
1
Patent #:
Issue Dt:
06/27/2000
Application #:
09299967
Filing Dt:
04/26/1999
Title:
COMPARING AERIAL IMAGE TO ACTUAL PHOTORESIST PATTERN FOR MASKING PROCESS CHARACTERIZATION
2
Patent #:
Issue Dt:
02/29/2000
Application #:
09300823
Filing Dt:
04/27/1999
Title:
CATALYTIC ACCELERATION AND ELECTRICAL BIAS CONTROL OF CMP PROCESSING
3
Patent #:
Issue Dt:
10/24/2000
Application #:
09302830
Filing Dt:
04/30/1999
Title:
METHOD AND ARRANGEMENT FOR FABRICATING A SEMICONDUCTOR DEVICE
4
Patent #:
Issue Dt:
09/11/2001
Application #:
09302832
Filing Dt:
04/30/1999
Title:
METHOD AND APPARATUS FOR DEPOSITION OF POROUS SILICA DIELECTRICS
5
Patent #:
Issue Dt:
05/18/2004
Application #:
09305722
Filing Dt:
05/05/1999
Title:
HIGH-RESOLUTION METHOD FOR PATTERNING A SUBSTRATE WITH MICRO-PRINTING
6
Patent #:
Issue Dt:
10/31/2000
Application #:
09305732
Filing Dt:
05/05/1999
Title:
POWER AND GROUND AND SIGNAL LAYOUT FOR HIGHER DENSITY INTEGRATED CIRCUIT CONNECTIONS WITH FLIP-CHIP BONDING
7
Patent #:
Issue Dt:
03/27/2001
Application #:
09305766
Filing Dt:
05/05/1999
Title:
BOND PAD DESIGN FOR INTEGRATED CIRCUITS
8
Patent #:
Issue Dt:
05/15/2001
Application #:
09306287
Filing Dt:
05/06/1999
Title:
METHOD OF ELECTRON BEAM EXPOSURE UTILIZING EMITTER WITH CONDUCTIVE MESH GRID
9
Patent #:
Issue Dt:
06/15/2004
Application #:
09310388
Filing Dt:
05/12/1999
Title:
DAMASCENE CAPACITORS FOR INTEGRATED CIRCUITS
10
Patent #:
Issue Dt:
12/10/2002
Application #:
09310701
Filing Dt:
05/07/1999
Title:
IMPROVED WEHNELT GUN FOR ELECTRON LITHOGRAPHY
11
Patent #:
Issue Dt:
10/24/2000
Application #:
09311253
Filing Dt:
05/13/1999
Title:
SEMICONDUCTOR WAFER HAVING A LAYER-TO-LAYER ALIGNMENT MARK AND METHOD FOR FABRICATING THE SAME
12
Patent #:
Issue Dt:
03/19/2002
Application #:
09311631
Filing Dt:
05/14/1999
Publication #:
Pub Dt:
01/03/2002
Title:
OXIDATION OF SILICON USING FLUORINE IMPLANT
13
Patent #:
Issue Dt:
12/31/2002
Application #:
09312386
Filing Dt:
05/14/1999
Publication #:
Pub Dt:
10/17/2002
Title:
STEPPED ETALON
14
Patent #:
Issue Dt:
02/25/2003
Application #:
09317430
Filing Dt:
05/24/1999
Title:
USING FAST HOT-CARRIER AGING METHOD FOR MEASURING PLASMA CHARGING DAMAGE
15
Patent #:
Issue Dt:
10/03/2000
Application #:
09321298
Filing Dt:
05/27/1999
Title:
CAVITY DOWN PLASTIC BALL GRID ARRAY MULTI-CHIP MODULE
16
Patent #:
Issue Dt:
08/21/2001
Application #:
09321658
Filing Dt:
05/28/1999
Title:
ANTI-MICROBUBBLE DEPOSITION APPARATUS
17
Patent #:
Issue Dt:
10/09/2001
Application #:
09321659
Filing Dt:
05/28/1999
Title:
ANTI-AIRLOCK APPARATUS FOR FILTERS
18
Patent #:
Issue Dt:
10/17/2000
Application #:
09322064
Filing Dt:
05/27/1999
Title:
FLIP CHIP BALL GRID ARRAY PACKAGE WITH LAMINATED SUBSTRATE
19
Patent #:
Issue Dt:
03/07/2000
Application #:
09322191
Filing Dt:
05/28/1999
Title:
LIQUID LEVEL SENSOR FOR BUFFERED HYDROFLUORIC ACID
20
Patent #:
Issue Dt:
02/12/2002
Application #:
09323607
Filing Dt:
06/01/1999
Title:
PROCESS FOR SYNTHESIZING A PALLADIUM REPLENISHER FOR ELECTROPLATING BATHS
21
Patent #:
Issue Dt:
04/02/2002
Application #:
09324946
Filing Dt:
06/03/1999
Title:
TUNGSTEN SILICIDE NITRIDE AS A BARRIER FOR HIGH TEMPERATURE ANNEALS TO IMPROVE HOT CARRIER RELIABILITY
22
Patent #:
Issue Dt:
09/26/2000
Application #:
09327793
Filing Dt:
06/08/1999
Title:
METHOD OF REDUCING CARBON CONTAMINATION OF A THIN DIELECTRIC FILM BY USING GASEOUS ORGANIC PRECURSORS, INERT GAS, AND OZONE TO REACT WITH CARBON CONTAMINANTS
23
Patent #:
Issue Dt:
11/06/2001
Application #:
09329420
Filing Dt:
06/10/1999
Title:
SELF ALIGNMENT DEVICE FOR BALL GRID ARRAY DEVICES
24
Patent #:
Issue Dt:
06/26/2001
Application #:
09332061
Filing Dt:
06/14/1999
Title:
PROCESS FOR FABRICATING A PROJECTION ELECTRON LITHOGRAPHY MASK AND A REMOVABLE REUSABLE COVER FOR USE THEREIN
25
Patent #:
Issue Dt:
08/28/2001
Application #:
09332216
Filing Dt:
06/14/1999
Title:
WAFER CARRIER MODIFICATION FOR REDUCED EXTRACTION FORCE
26
Patent #:
Issue Dt:
07/24/2001
Application #:
09333626
Filing Dt:
06/15/1999
Title:
PROCESS AND APPARATUS FOR MAKING COMPOSITE FILMS
27
Patent #:
Issue Dt:
10/30/2001
Application #:
09334491
Filing Dt:
06/16/1999
Title:
PROCESS FOR FORMING A PLASMA NITRIDE FILM SUITABLE FOR GATE DIELECTRIC APPLICATION IN SUB-0.25 UM TECHNOLOGIES
28
Patent #:
Issue Dt:
07/09/2002
Application #:
09334977
Filing Dt:
06/17/1999
Title:
LAYERED DIELECTRIC FILM STRUCTURE SUITABLE FOR GATE DIELECTRIC APPLICATION IN SUB-0.25 uM TECHNOLOGIES
29
Patent #:
Issue Dt:
03/06/2001
Application #:
09335707
Filing Dt:
06/18/1999
Title:
PROCESS FOR FABRICATING VERTICAL TRANSISTORS
30
Patent #:
Issue Dt:
09/10/2002
Application #:
09337741
Filing Dt:
06/22/1999
Title:
BONDED ARTICLE HAVING IMPROVED CRYSTALLINE STRUCTURE AND WORK FUNCTION UNIFORMITY AND METHOD FOR MAKING THE SAME
31
Patent #:
Issue Dt:
03/26/2002
Application #:
09337966
Filing Dt:
06/22/1999
Title:
SCANNING ELECTRON MICROSCOPE/ENERGY DISPERSIVE SPECTROSCOPY SAMPLE PREPARATION METHOD AND SAMPLE PRODUCED THEREBY
32
Patent #:
Issue Dt:
07/03/2001
Application #:
09338143
Filing Dt:
06/22/1999
Title:
INTEGRATED CIRCUIT HAVING A MICROMAGNETIC DEVICE INCLUDING A FERROMAGNETIC CORE AND METHOD OF MANUFACTURE THEREFOR
33
Patent #:
Issue Dt:
10/08/2002
Application #:
09338338
Filing Dt:
06/23/1999
Title:
METHOD FOR IMPLEMENTING A BIST SCHEME INTO INTEGRATED CIRCUITS FOR TESTING RTL CONTROLLER-DATA PATHS IN THE INTEGRATED CIRCUITS.
34
Patent #:
Issue Dt:
11/09/2004
Application #:
09338520
Filing Dt:
06/23/1999
Title:
CATHODE WITH IMPROVED WORK FUNCTION AND METHOD FOR MAKING THE SAME
35
Patent #:
Issue Dt:
09/05/2000
Application #:
09338735
Filing Dt:
06/23/1999
Title:
METHOD OF MAKING A SEMICONDUCTOR WITH COPPER PASSIVATING FILM
36
Patent #:
Issue Dt:
08/28/2001
Application #:
09338939
Filing Dt:
06/24/1999
Title:
SYSTEM AND METHOD FOR FORMING A UNIFORM THIN GATE OXIDE LAYER
37
Patent #:
Issue Dt:
06/06/2000
Application #:
09339085
Filing Dt:
06/23/1999
Title:
METHOD OF PASSIVATING COPPER INTERCONNECTS IN A SEMICONDUCTOR
38
Patent #:
Issue Dt:
04/25/2000
Application #:
09339306
Filing Dt:
06/23/1999
Title:
METHOD OF MAKING INTEGRATED CIRCUITS WITH TUB-TIES
39
Patent #:
Issue Dt:
04/15/2003
Application #:
09339893
Filing Dt:
06/25/1999
Title:
ACCELEROMETER INFLUENCED COMMUNICATION DEVICE
40
Patent #:
Issue Dt:
10/16/2001
Application #:
09339894
Filing Dt:
06/25/1999
Title:
CHARGE INJECTION TRANSISTOR USING HIGH-K DIELECTRIC BARRIER LAYER
41
Patent #:
Issue Dt:
11/20/2001
Application #:
09339895
Filing Dt:
06/25/1999
Title:
GATE STRUCTURE FOR INTEGRATED CIRCUIT FABRICATION
42
Patent #:
Issue Dt:
05/22/2001
Application #:
09340224
Filing Dt:
06/25/1999
Title:
METHODS OF FABRICATING AN INTEGRATED CIRCUIT DEVICE WITH COMPOSITE OXIDE DIELECTRIC
43
Patent #:
Issue Dt:
02/19/2002
Application #:
09344056
Filing Dt:
06/25/1999
Title:
MOBILE IONIC CONTAMINATION DETECTION IN MANUFACTURE OF SEMICONDUCTOR DEVICES
44
Patent #:
Issue Dt:
09/29/2009
Application #:
09344169
Filing Dt:
06/24/1999
Title:
DETERMINING TIMING OF INTEGRATED CIRCUITS
45
Patent #:
Issue Dt:
04/16/2002
Application #:
09344656
Filing Dt:
06/25/1999
Title:
PLASTIC PACKAGED OPTOELECTRONIC DEVICE
46
Patent #:
Issue Dt:
04/09/2002
Application #:
09345039
Filing Dt:
06/30/1999
Title:
METHOD FOR MAKING AN INTEGRATED CIRCUIT INCLUDING ALIGNMENT MARKS
47
Patent #:
Issue Dt:
11/21/2000
Application #:
09345432
Filing Dt:
07/01/1999
Title:
ROUTING DENSITY ENHANCEMENT FOR SEMICOMDUCTOR BGA PACKAGES AND PRINTED WIRING BOARDS
48
Patent #:
Issue Dt:
07/24/2001
Application #:
09345556
Filing Dt:
06/30/1999
Title:
METHOD FOR MAKING AN INTEGRATED CIRCUIT CAPACITOR INCLUDING TANTALUM PENTOXIDE
49
Patent #:
Issue Dt:
08/28/2001
Application #:
09346100
Filing Dt:
07/01/1999
Title:
LOW COST BALL GRID ARRAY PACKAGE
50
Patent #:
Issue Dt:
05/15/2001
Application #:
09346493
Filing Dt:
06/30/1999
Title:
PROCESS TO PREVENT STRESS CRACKING OF DIELECTRIC FILMS ON SEMICONDUCTOR WAFERS
51
Patent #:
Issue Dt:
07/10/2001
Application #:
09347313
Filing Dt:
07/02/1999
Title:
METHOD ANALYZING A SEMICONDUCTOR SURFACE USING LINE WIDTH METROLOGY WITH AUTO-CORRELATION OPERATION
52
Patent #:
Issue Dt:
08/28/2001
Application #:
09347487
Filing Dt:
07/02/1999
Title:
METHOD FOR MANUFACTURING A METAL-TO-METAL CAPACITOR UTILIZING ONLY ONE MASKING STEP
53
Patent #:
Issue Dt:
07/08/2003
Application #:
09347628
Filing Dt:
07/02/1999
Title:
METHOD FOR IDENTIFYING CYCLICITY IN CIRCUIT DESIGNS
54
Patent #:
Issue Dt:
09/03/2002
Application #:
09349538
Filing Dt:
07/08/1999
Publication #:
Pub Dt:
01/31/2002
Title:
METHOD FOR FABRICATING BIPOLAR TRANSISTORS
55
Patent #:
Issue Dt:
04/08/2003
Application #:
09350645
Filing Dt:
07/09/1999
Title:
SYSTEM AND METHOD FOR TESTING AN INTEGRATED CIRCUIT DEVICE USING FFT ANALYSIS BASED ON A NON-ITERATIVE FFT COHERENCY ANALYSIS ALGORITHM
56
Patent #:
Issue Dt:
08/21/2001
Application #:
09351220
Filing Dt:
10/14/1999
Title:
APPARATUS AND METHOD FOR SOLDER ATTACHMENT OF HIGH POWERED TRANSISTORS TO BASE HEATSINK
57
Patent #:
Issue Dt:
03/13/2001
Application #:
09351546
Filing Dt:
07/12/1999
Title:
METHOD AND APPARATUS FOR CUTTING A SUBSTRATE
58
Patent #:
Issue Dt:
11/20/2001
Application #:
09351945
Filing Dt:
07/12/1999
Title:
ENCAPSULATED CIRCUIT USING VENTED MOLD
59
Patent #:
Issue Dt:
09/25/2001
Application #:
09351971
Filing Dt:
07/12/1999
Title:
METHOD OF MAKING DEVICES HAVING THIN DIELECTRIC LAYERS
60
Patent #:
Issue Dt:
06/26/2001
Application #:
09352674
Filing Dt:
07/11/1999
Title:
METHOD FOR COATING AN ARTICLE WITH A LADDER SILOXANE POLYMER AND COATED ARTICLE
61
Patent #:
Issue Dt:
08/01/2000
Application #:
09353860
Filing Dt:
07/15/1999
Title:
LOCATION OF DEFECTS USING DYE PENETRATION
62
Patent #:
Issue Dt:
07/02/2002
Application #:
09354657
Filing Dt:
07/16/1999
Title:
VERY LOW MAGNETIC FIELD INTEGRATED CIRCUIT
63
Patent #:
Issue Dt:
02/06/2001
Application #:
09354711
Filing Dt:
07/16/1999
Title:
ARTICLE COMPRISING A VARIABLE INDUCTOR
64
Patent #:
Issue Dt:
11/27/2001
Application #:
09354928
Filing Dt:
07/15/1999
Title:
NANOSCALE CONDUCTIVE CONNECTORS AND METHOD FOR MAKING SAME
65
Patent #:
Issue Dt:
07/10/2001
Application #:
09356396
Filing Dt:
07/16/1999
Title:
ZONE PLATES FOR X-RAYS
66
Patent #:
Issue Dt:
07/30/2002
Application #:
09358606
Filing Dt:
07/21/1999
Title:
OFF-AXIS PUPIL APERTURE AND METHOD FOR MAKING THE SAME
67
Patent #:
Issue Dt:
05/09/2000
Application #:
09361684
Filing Dt:
07/27/1999
Title:
CONSISTENT ALIGNMENT MARK PROFILES ON SEMICONDUCTOR WAFERS USING FINE GRAIN TUNGSTEN PROTECTIVE LAYER
68
Patent #:
Issue Dt:
09/05/2000
Application #:
09362645
Filing Dt:
07/27/1999
Title:
PROCESS FOR TREATING EXPOSED SURFACES OF A LOW DIELECTRIC CONSTANT CARBON DOPED SILICON OXIDE DIELECTRIC MATERIAL TO PROTECT THE MATERIAL FROM DAMAGE
69
Patent #:
Issue Dt:
08/14/2001
Application #:
09362648
Filing Dt:
07/27/1999
Title:
PRE-CONDITIONING POLISHING PADS FOR CHEMICAL-MECHANICAL POLISHING
70
Patent #:
Issue Dt:
11/22/2005
Application #:
09363311
Filing Dt:
07/28/1999
Title:
FUNCTIONAL-PATTERN MANAGEMENT SYSTEM FOR DEVICE VERIFICATION
71
Patent #:
Issue Dt:
11/28/2000
Application #:
09363758
Filing Dt:
07/29/1999
Title:
METHOD FOR PRODUCING ORIENTED PIEZOELECTRIC FILMS
72
Patent #:
Issue Dt:
03/27/2001
Application #:
09363769
Filing Dt:
07/29/1999
Title:
METHOD FOR MAKING AN INTEGRATED CIRCUIT INCLUDING HIGH AND LOW VOLTAGE TRANSISTORS
73
Patent #:
Issue Dt:
01/16/2001
Application #:
09363781
Filing Dt:
07/29/1999
Title:
MONOLITHIC RESISTOR HAVING DYNAMICALLY CONTROLLABLE IMPEDANCE AND METHOD OF MANUFACTURING THE SAME
74
Patent #:
Issue Dt:
08/15/2000
Application #:
09364025
Filing Dt:
07/30/1999
Title:
METHOD FOR MAKING INTEGRATED CIRCUIT CAPACITOR INCLUDING ANCHORED PLUGS
75
Patent #:
Issue Dt:
09/17/2002
Application #:
09364140
Filing Dt:
07/30/1999
Title:
METHOD AND APPARATUS FOR PLANRIZING A WAFER SURFACE OF A SEMICONDUCTOR WAFER HAVING AN ELEVATED PORTION EXTENDING THEREFROM
76
Patent #:
Issue Dt:
01/02/2001
Application #:
09364208
Filing Dt:
07/30/1999
Title:
METHOD FOR MAKING INTEGRATED CIRCUIT CAPACITOR INCLUDING ANCHORED PLUG
77
Patent #:
Issue Dt:
03/20/2001
Application #:
09364366
Filing Dt:
07/30/1999
Title:
METHOD OF MAKING INTEGRATED CIRCUIT CAPACITOR INCLUDING TAPERED PLUG
78
Patent #:
Issue Dt:
11/28/2000
Application #:
09364367
Filing Dt:
07/30/1999
Title:
INTEGRATED CIRCUIT CAPACITOR INCLUDING ANCHORED PLUG
79
Patent #:
Issue Dt:
06/19/2001
Application #:
09364603
Filing Dt:
07/30/1999
Title:
INTEGRATED CIRCUIT CAPACITOR INCLUDING TAPERED PLUG
80
Patent #:
Issue Dt:
09/18/2001
Application #:
09364767
Filing Dt:
07/30/1999
Title:
INTEGRATED CIRCUIT CAPACITOR INCLUDING ANCHORED PLUGS
81
Patent #:
Issue Dt:
08/27/2002
Application #:
09364858
Filing Dt:
07/30/1999
Title:
INTEGRATED CIRCUIT INCLUDING PASSIVATED COPPER INTERCONNECTION LINES AND ASSOCIATED MANUFACTURING METHODS
82
Patent #:
Issue Dt:
01/07/2003
Application #:
09365059
Filing Dt:
07/30/1999
Title:
FIELD EMITTING DEVICE COMPRISING METALLIZED NANOSTRUCTURES AND METHOD FOR MAKING THE SAME
83
Patent #:
Issue Dt:
07/18/2000
Application #:
09365440
Filing Dt:
08/02/1999
Title:
METHOD OF SINGLE STEP DAMASCENE PROCESS FOR DEPOSITION AND GLOBAL PLANARIZATION
84
Patent #:
Issue Dt:
10/09/2001
Application #:
09366362
Filing Dt:
08/03/1999
Title:
APPARATUS AND METHOD FOR REMOVING A POLISHING PAD FROM A PLATEN
85
Patent #:
Issue Dt:
05/06/2003
Application #:
09366388
Filing Dt:
08/03/1999
Title:
METHODS AND APPARATUS FOR TESTING INTEGRATED CIRCUITS
86
Patent #:
Issue Dt:
11/28/2000
Application #:
09369105
Filing Dt:
08/05/1999
Title:
PROCESS FOR FORMING DEVICE COMPRISING METALLIZED MAGNETIC SUBSTRATES
87
Patent #:
Issue Dt:
03/25/2003
Application #:
09369802
Filing Dt:
08/06/1999
Title:
FIELD EMITTING DEVICE COMPRISING FIELD-CONCENTRATING NANOCONDUCTOR ASSEMBLY AND METHOD FOR MAKING THE SAME
88
Patent #:
Issue Dt:
11/28/2000
Application #:
09370422
Filing Dt:
08/09/1999
Title:
HIGH DENSITY PLASMA PASSIVATION LAYER AND METHOD OF APPLICATION
89
Patent #:
Issue Dt:
02/25/2003
Application #:
09370501
Filing Dt:
08/09/1999
Title:
LOW THRESHOLD VOLTAGE MOS TRANSISTOR AND METHOD OF MANUFACTURE
90
Patent #:
Issue Dt:
09/10/2002
Application #:
09370856
Filing Dt:
08/09/1999
Title:
NON-DESTRUCTIVE METHOD OF DETECTING DIE CRACK PROBLEMS
91
Patent #:
Issue Dt:
09/11/2001
Application #:
09370912
Filing Dt:
08/06/1999
Title:
METHOD OF MAKING A SEMICONDUCTOR WITH COPPER PASSIVATING FILM
92
Patent #:
Issue Dt:
05/08/2001
Application #:
09370963
Filing Dt:
08/10/1999
Title:
USE OF A GETTER LAYER TO IMPROVE METAL TO METAL CONTACT RESISTANCE AT LOW RADIO FREQUENCY POWER
93
Patent #:
Issue Dt:
05/22/2001
Application #:
09375150
Filing Dt:
08/16/1999
Title:
SILICON-GERMANIUM TRANSISTOR AND ASSOCIATED METHODS
94
Patent #:
Issue Dt:
07/24/2001
Application #:
09375835
Filing Dt:
08/16/1999
Title:
SEMICONDUCTOR FLIP CHIP BALL GRID ARRAY PACKAGE
95
Patent #:
Issue Dt:
08/14/2001
Application #:
09376233
Filing Dt:
08/17/1999
Title:
INTEGRATED CIRCUIT DEVICE HAVING A PLANAR INTERLEVEL DIELECTRIC LAYER
96
Patent #:
Issue Dt:
03/27/2001
Application #:
09376696
Filing Dt:
08/18/1999
Title:
WAFER CARRIER HEAD FOR PREVENTION OF UNINTENTIONAL SEMICONDUCTOR WAFER ROTATION
97
Patent #:
Issue Dt:
04/27/2004
Application #:
09377386
Filing Dt:
08/19/1999
Title:
DIFFUSION PREVENTING BARRIER LAYER IN INTEGRATED CIRCUIT INTER-METAL LAYER DIELECTRICS
98
Patent #:
Issue Dt:
09/04/2001
Application #:
09377887
Filing Dt:
08/19/1999
Title:
MULTIPLE LAYER TAPE BALL GRID ARRAY PACKAGE
99
Patent #:
Issue Dt:
02/13/2001
Application #:
09378856
Filing Dt:
08/23/1999
Title:
PROCESS FOR DEUTERIUM PASSIVATION AND HOT CARRIER IMMUNITY
100
Patent #:
Issue Dt:
01/06/2004
Application #:
09379055
Filing Dt:
08/23/1999
Title:
DEUTERIUM PASSIVATED SEMICONDUCTOR DEVICE HAVING ENHANCED IMMUNITY TO HOT CARRIER EFFECTS
Assignors
1
Exec Dt:
01/24/2018
2
Exec Dt:
01/24/2018
3
Exec Dt:
01/24/2018
Assignee
1
225 W. WASHINGTON ST., 9TH FLOOR
CHICAGO, ILLINOIS 60606
Correspondence name and address
JAVIER J. RAMOS
1850 K STREET, NW, SUITE 1100
MILBANK, TWEED, HADLEY & MCCLOY, LLP
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