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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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10730554
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Filing Dt:
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12/08/2003
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Publication #:
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Pub Dt:
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06/09/2005
| | | | |
Title:
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HIGH PERFORMANCE DIODE IMPLANTED VOLTAGE CONTROLLED P-TYPE DIFFUSION RESISTOR
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Patent #:
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Issue Dt:
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02/05/2008
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Application #:
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10732395
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Filing Dt:
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12/09/2003
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Publication #:
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Pub Dt:
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06/09/2005
| | | | |
Title:
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CELL-BASED METHOD FOR CREATING SLOTTED METAL IN SEMICONDUCTOR DESIGNS
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Patent #:
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Issue Dt:
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12/12/2006
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Application #:
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10733034
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Filing Dt:
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12/11/2003
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Title:
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METHOD OF FABRICATING AN INTEGRAL CAPACITOR AND GATE TRANSISTOR HAVING NITRIDE AND OXIDE POLISH STOP LAYERS USING CHEMICAL MECHANICAL POLISHING ELIMINATION
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Patent #:
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Issue Dt:
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01/26/2010
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Application #:
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10736386
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Filing Dt:
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12/15/2003
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Publication #:
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Pub Dt:
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06/16/2005
| | | | |
Title:
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METHOD FOR CALCULATING HIGH-RESOLUTION WAFER PARAMETER PROFILES
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10738761
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Filing Dt:
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12/16/2003
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Publication #:
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Pub Dt:
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06/16/2005
| | | | |
Title:
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INCORPORATING DOPANTS TO ENHANCE THE DIELECTRIC PROPERTIES OF METAL SILICATES
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Patent #:
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Issue Dt:
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01/17/2006
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Application #:
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10739460
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Filing Dt:
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12/18/2003
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Publication #:
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Pub Dt:
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06/23/2005
| | | | |
Title:
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METHOD AND APPARATUS FOR OPTIMIZING FRAGMENTATION OF BOUNDARIES FOR OPTICAL PROXIMITY CORRECTION (OPC) PURPOSES
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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10740284
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Filing Dt:
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12/18/2003
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Publication #:
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Pub Dt:
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06/23/2005
| | | | |
Title:
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SYSTEM AND METHOD FOR MAPPING LOGICAL COMPONENTS TO PHYSICAL LOCATIONS IN AN INTEGRATED CIRCUIT DESIGN ENVIRONMENT
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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10740359
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Filing Dt:
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12/18/2003
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Publication #:
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Pub Dt:
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06/23/2005
| | | | |
Title:
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GRADIENT METHOD OF MASK EDGE CORRECTION
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Patent #:
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Issue Dt:
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02/12/2008
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Application #:
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10741155
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Filing Dt:
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12/19/2003
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Publication #:
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Pub Dt:
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09/23/2004
| | | | |
Title:
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STRUCTURE AND METHOD FOR BONDING TO COPPER INTERCONNECT STRUCTURES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10742916
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Filing Dt:
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12/23/2003
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Publication #:
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Pub Dt:
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08/26/2004
| | | | |
Title:
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Method of manufacturing and mounting electronic devices to limit the effects of parasitics
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Patent #:
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Issue Dt:
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08/29/2006
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Application #:
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10744363
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Filing Dt:
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12/22/2003
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Publication #:
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Pub Dt:
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06/23/2005
| | | | |
Title:
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EMBEDDED REDISTRIBUTION INTERPOSER FOR FOOTPRINT COMPATIBLE CHIP PACKAGE CONVERSION
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Patent #:
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Issue Dt:
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11/25/2008
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Application #:
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10746824
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Filing Dt:
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12/24/2003
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Publication #:
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Pub Dt:
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07/07/2005
| | | | |
Title:
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ELECTRICAL DEVICES HAVING ADJUSTABLE ELECTRICAL CHARACTERISTICS
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Patent #:
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Issue Dt:
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05/30/2006
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Application #:
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10748068
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Filing Dt:
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12/29/2003
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Publication #:
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Pub Dt:
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07/07/2005
| | | | |
Title:
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SYSTEM AND METHOD FOR DEBUGGING SYSTEM-ON-CHIPS USING SINGLE OR N-CYCLE STEPPING
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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10750348
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Filing Dt:
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12/31/2003
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Publication #:
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Pub Dt:
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08/19/2004
| | | | |
Title:
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METHOD OF PREVENTING RESIST POISONING IN DUAL DAMASCENE STRUCTURES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10755616
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Filing Dt:
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01/12/2004
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Publication #:
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Pub Dt:
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07/14/2005
| | | | |
Title:
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Method for electrical interconnection between printed wiring board layers using through holes with solid core conductive material
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10757752
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Filing Dt:
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01/14/2004
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Publication #:
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Pub Dt:
|
02/03/2005
| | | | |
Title:
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OPTIMIZED BOND OUT METHOD FOR FLIP CHIP WAFERS
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Patent #:
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Issue Dt:
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12/19/2006
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Application #:
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10762788
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Filing Dt:
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01/22/2004
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Publication #:
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Pub Dt:
|
08/05/2004
| | | | |
Title:
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MOS TRANSISTOR AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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10/02/2007
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Application #:
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10762962
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Filing Dt:
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01/22/2004
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Publication #:
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Pub Dt:
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02/24/2005
| | | | |
Title:
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THIN FILM RESISTOR DEVICE AND A METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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10767205
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Filing Dt:
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01/30/2004
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Publication #:
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Pub Dt:
|
08/04/2005
| | | | |
Title:
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CROSS-FILL PATTERN FOR METAL FILL LEVELS, POWER SUPPLY FILTERING, AND ANALOG CIRUCIT SHIELDING
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Patent #:
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Issue Dt:
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05/03/2005
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Application #:
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10767314
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Filing Dt:
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01/28/2004
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Title:
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METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUIT CORE MODULES
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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10768558
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Filing Dt:
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01/29/2004
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Publication #:
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Pub Dt:
|
02/10/2005
| | | | |
Title:
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METHOD AND APPARATUS FOR MAPPING PLATFORM-BASED DESIGN TO MULTIPLE FOUNDRY PROCESSES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10768588
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Filing Dt:
|
01/29/2004
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Publication #:
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Pub Dt:
|
02/10/2005
| | | | |
Title:
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Method and apparatus for mapping platform-based design to multiple foundry processes
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10768771
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Filing Dt:
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01/30/2004
|
Publication #:
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Pub Dt:
|
08/04/2005
| | | | |
Title:
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SEMICONDUCTOR RESISTOR
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|
Patent #:
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Issue Dt:
|
07/08/2008
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Application #:
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10769510
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Filing Dt:
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01/30/2004
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Publication #:
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Pub Dt:
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09/23/2004
| | | | |
Title:
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SYSTEM AND METHOD FOR OPTIMIZING AN INTEGRATED CIRCUIT DESIGN
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|
Patent #:
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Issue Dt:
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10/02/2007
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Application #:
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10771532
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Filing Dt:
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02/04/2004
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Publication #:
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Pub Dt:
|
11/04/2004
| | | | |
Title:
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LOW POWER PROTOCOL FOR WIRELESS TERMINAL PEER-TO-PEER COMMUNICATIONS
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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10772133
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Filing Dt:
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02/03/2004
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Publication #:
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Pub Dt:
|
08/12/2004
| | | | |
Title:
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MULTI-STEP PROCESS FOR FORMING A BARRIER FILM FOR USE IN COPPER LAYER FORMATION
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Patent #:
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Issue Dt:
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05/08/2007
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Application #:
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10773614
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Filing Dt:
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02/06/2004
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Publication #:
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Pub Dt:
|
08/11/2005
| | | | |
Title:
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SEMICONDUCTOR DEVICE CONFIGURED FOR REDUCING POST-FABRICATION DAMAGE
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10773900
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Filing Dt:
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02/06/2004
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Publication #:
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Pub Dt:
|
08/12/2004
| | | | |
Title:
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VERTICAL REPLACEMENT-GATE SILICON-ON-INSULATOR TRANSISTOR
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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10776752
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Filing Dt:
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02/11/2004
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Publication #:
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Pub Dt:
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08/19/2004
| | | | |
Title:
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INTERDIGITATED CAPACITOR AND METHOD OF MANUFACTURING THEREOF
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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10777250
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Filing Dt:
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02/12/2004
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Publication #:
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Pub Dt:
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08/19/2004
| | | | |
Title:
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INTEGRATED CIRCUIT EARLY LIFE FAILURE DETECTION BY MONITORING CHANGES IN CURRENT SIGNATURES
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Patent #:
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Issue Dt:
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02/28/2006
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Application #:
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10778454
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Filing Dt:
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02/13/2004
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Publication #:
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Pub Dt:
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08/18/2005
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
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12/06/2005
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Application #:
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10779966
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Filing Dt:
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02/17/2004
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Publication #:
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Pub Dt:
|
08/18/2005
| | | | |
Title:
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METHOD AND CONTROL SYSTEM FOR IMPROVING CMP PROCESS BY DETECTING AND REACTING TO HARMONIC OSCILLATION
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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10786182
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Filing Dt:
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02/25/2004
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Publication #:
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Pub Dt:
|
08/11/2005
| | | | |
Title:
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METHODS AND APPARATUS FOR INTEGRATED CIRCUIT BALL BONDING WITH SUBSTANTIALLY PERPENDICULAR WIRE BOND PROFILES
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Patent #:
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Issue Dt:
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08/08/2006
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Application #:
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10787010
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Filing Dt:
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02/25/2004
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Publication #:
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Pub Dt:
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08/25/2005
| | | | |
Title:
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METHODS AND APPARATUS FOR WIRE BONDING WITH WIRE LENGTH ADJUSTMENT IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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10788162
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Filing Dt:
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02/26/2004
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Publication #:
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Pub Dt:
|
09/01/2005
| | | | |
Title:
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SEMICONDUCTOR PACKAGING TECHNIQUES FOR USE WITH NON-CERAMIC PACKAGES
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Patent #:
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Issue Dt:
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01/16/2007
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Application #:
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10788678
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Filing Dt:
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02/27/2004
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Publication #:
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Pub Dt:
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09/01/2005
| | | | |
Title:
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TECHNIQUES FOR REDUCING BOWING IN POWER TRANSISTOR DEVICES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10791337
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Filing Dt:
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03/01/2004
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Publication #:
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Pub Dt:
|
09/01/2005
| | | | |
Title:
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Spacer-less transistor integration scheme for high-k gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe strained silicon schemes
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Patent #:
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Issue Dt:
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10/31/2006
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Application #:
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10793055
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Filing Dt:
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03/04/2004
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Publication #:
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Pub Dt:
|
09/08/2005
| | | | |
Title:
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CONDUCTOR STACK SHIFTING
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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10794225
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Filing Dt:
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03/05/2004
|
Publication #:
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Pub Dt:
|
09/08/2005
| | | | |
Title:
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FEATURE TARGETED INSPECTION
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Patent #:
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Issue Dt:
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09/04/2007
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Application #:
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10794683
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Filing Dt:
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03/05/2004
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Publication #:
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|
Pub Dt:
|
09/08/2005
| | | | |
Title:
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OPC BASED ILLUMINATION OPTIMIZATION WITH MASK ERROR CONSTRAINTS
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Patent #:
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Issue Dt:
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10/04/2005
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Application #:
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10799279
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Filing Dt:
|
03/12/2004
|
Publication #:
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|
Pub Dt:
|
09/15/2005
| | | | |
Title:
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CHEMICAL MECHANICAL POLISHING PAD WITH GROOVES ALTERNATING BETWEEN A LARGER GROOVE SIZE AND A SMALLER GROOVE SIZE
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Patent #:
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Issue Dt:
|
11/20/2007
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Application #:
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10799851
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Filing Dt:
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03/12/2004
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Publication #:
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Pub Dt:
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09/15/2005
| | | | |
Title:
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PROCESS CONTROL DATA COLLECTION
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Patent #:
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Issue Dt:
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01/29/2008
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Application #:
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10800219
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Filing Dt:
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03/12/2004
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Publication #:
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Pub Dt:
|
09/15/2005
| | | | |
Title:
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METHOD AND APPARATUS FOR VERIFYING THE POST-OPTICAL PROXIMITY CORRECTED MASK WAFER IMAGE SENSITIVITY TO RETICLE MANUFACTURING ERRORS
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Patent #:
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Issue Dt:
|
07/01/2008
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Application #:
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10801310
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Filing Dt:
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03/16/2004
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Publication #:
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Pub Dt:
|
10/13/2005
| | | | |
Title:
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YIELD PROFILE MANIPULATOR
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
10802522
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Filing Dt:
|
03/17/2004
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Publication #:
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Pub Dt:
|
12/02/2004
| | | | |
Title:
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Interconnect integration
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|
Patent #:
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|
Issue Dt:
|
07/08/2008
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Application #:
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10803516
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Filing Dt:
|
03/17/2004
|
Publication #:
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|
Pub Dt:
|
09/22/2005
| | | | |
Title:
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METHOD AND APPARATUS FOR PERFORMING LOGICAL TRANSFORMATIONS FOR GLOBAL ROUTING
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Patent #:
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Issue Dt:
|
07/25/2006
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Application #:
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10804980
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Filing Dt:
|
03/18/2004
|
Publication #:
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Pub Dt:
|
09/09/2004
| | | | |
Title:
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METHOD FOR GROWING THIN FILMS
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|
Patent #:
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|
Issue Dt:
|
09/26/2006
|
Application #:
|
10809939
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Filing Dt:
|
03/25/2004
|
Publication #:
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|
Pub Dt:
|
11/04/2004
| | | | |
Title:
|
BROKEN SYMMETRY FOR OPTIMIZATION OF RESOURCE FABRIC IN A SEA-OF-PLATFORM ARCHITECTURE
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|
Patent #:
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|
Issue Dt:
|
04/03/2007
|
Application #:
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10810294
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Filing Dt:
|
03/26/2004
|
Publication #:
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Pub Dt:
|
10/13/2005
| | | | |
Title:
|
MACRO CELL FOR INTEGRATED CIRCUIT PHYSICAL LAYER INTERFACE
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Patent #:
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Issue Dt:
|
05/09/2006
|
Application #:
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10814062
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Filing Dt:
|
03/31/2004
|
Publication #:
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Pub Dt:
|
10/06/2005
| | | | |
Title:
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ENHANCED SUBSTRATE CONTACT FOR A SEMICONDUCTOR DEVICE
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|
Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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10814680
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Filing Dt:
|
03/31/2004
|
Publication #:
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|
Pub Dt:
|
09/23/2004
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A DOPED LATTICE MATCHING LAYER AND A METHOD OF MANUFACTURE THEREFOR
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
10814682
|
Filing Dt:
|
03/31/2004
|
Publication #:
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|
Pub Dt:
|
09/23/2004
| | | | |
Title:
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Semiconductor device having a doped lattice matching layer and a method of manufacture therefor
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Patent #:
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|
Issue Dt:
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04/18/2006
|
Application #:
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10816060
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Filing Dt:
|
04/01/2004
|
Publication #:
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|
Pub Dt:
|
10/13/2005
| | | | |
Title:
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INTEGRATED CIRCUIT DEVICE HAVING FLEXIBLE LEADFRAME
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|
Patent #:
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|
Issue Dt:
|
11/17/2009
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Application #:
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10817419
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Filing Dt:
|
04/01/2004
|
Publication #:
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|
Pub Dt:
|
10/06/2005
| | | | |
Title:
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SYSTEM AND METHOD FOR IMPLEMENTING MULTIPLE INSTANTIATED CONFIGURABLE PERIPHERALS IN A CIRCUIT DESIGN
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|
Patent #:
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|
Issue Dt:
|
07/10/2007
|
Application #:
|
10819253
|
Filing Dt:
|
04/05/2004
|
Publication #:
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|
Pub Dt:
|
09/30/2004
| | | | |
Title:
|
STRUCTURE AND FABRICATION METHOD FOR CAPACITORS INTEGRATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS
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|
Patent #:
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|
Issue Dt:
|
02/27/2007
|
Application #:
|
10819254
|
Filing Dt:
|
04/06/2004
|
Publication #:
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|
Pub Dt:
|
10/13/2005
| | | | |
Title:
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GENERIC METHOD AND APPARATUS FOR IMPLEMENTING SOURCE SYNCHRONOUS INTERFACE IN PLATFORM ASIC
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|
Patent #:
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|
Issue Dt:
|
02/06/2007
|
Application #:
|
10819684
|
Filing Dt:
|
04/06/2004
|
Publication #:
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|
Pub Dt:
|
10/13/2005
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE AND METHOD HAVING WIRE-BONDED INTRA-DIE ELECTRICAL CONNECTIONS
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|
Patent #:
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|
Issue Dt:
|
10/10/2006
|
Application #:
|
10820494
|
Filing Dt:
|
04/07/2004
|
Publication #:
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|
Pub Dt:
|
10/13/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR ESTABLISHING IMPROVED THERMAL COMMUNICATION BETWEEN A DIE AND A HEATSPREADER IN A SEMICONDUCTOR PACKAGE
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10824509
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Filing Dt:
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04/14/2004
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Publication #:
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Pub Dt:
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10/20/2005
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Title:
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PROCESS AND APPARATUS FOR CHARACTERIZING INTELLECTUAL PROPERTY FOR INTEGRATION INTO AN IC PLATFORM ENVIRONMENT
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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10825342
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Filing Dt:
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04/14/2004
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Publication #:
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Pub Dt:
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04/28/2005
| | | | |
Title:
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OPTIMIZED MIRROR DESIGN FOR OPTICAL DIRECT WRITE
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Patent #:
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Issue Dt:
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05/15/2007
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Application #:
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10828408
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Filing Dt:
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04/19/2004
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Publication #:
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Pub Dt:
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10/20/2005
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Title:
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METHOD AND COMPUTER PROGRAM FOR VERIFYING AN INCREMENTAL CHANGE TO AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10828993
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Filing Dt:
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04/21/2004
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Publication #:
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Pub Dt:
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10/07/2004
| | | | |
Title:
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Method for making a radio frequency component and component produced thereby
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Patent #:
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Issue Dt:
|
03/15/2005
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Application #:
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10829408
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Filing Dt:
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04/20/2004
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Publication #:
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Pub Dt:
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10/07/2004
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Title:
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AUTOMATIC CALIBRATION OF A MASKING PROCESS SIMULATOR
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Patent #:
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Issue Dt:
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04/24/2007
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Application #:
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10830542
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Filing Dt:
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04/23/2004
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Publication #:
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Pub Dt:
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10/27/2005
| | | | |
Title:
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PROCESS AND APPARATUS FOR PLACING CELLS IN AN IC FLOORPLAN
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Patent #:
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Issue Dt:
|
05/15/2007
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Application #:
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10830739
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Filing Dt:
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04/25/2004
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Publication #:
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Pub Dt:
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10/27/2005
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Title:
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PROCESS AND APPARATUS FOR MEMORY MAPPING
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Patent #:
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Issue Dt:
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10/20/2009
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Application #:
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10832226
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Filing Dt:
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04/26/2004
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Publication #:
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Pub Dt:
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10/27/2005
| | | | |
Title:
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GATE-LEVEL NETLIST REDUCTION FOR SIMULATING TARGET MODULES OF A DESIGN
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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10838384
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Filing Dt:
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05/04/2004
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Publication #:
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Pub Dt:
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10/14/2004
| | | | |
Title:
|
Implementation of Si-Ge HBT module with CMOS process
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Patent #:
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Issue Dt:
|
09/01/2009
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Application #:
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10840534
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Filing Dt:
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05/06/2004
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Publication #:
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Pub Dt:
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11/10/2005
| | | | |
Title:
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ASSURING CORRECT DATA ENTRY TO GENERATE SHELLS FOR A SEMICONDUCTOR PLATFORM
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Patent #:
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Issue Dt:
|
01/02/2007
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Application #:
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10842139
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Filing Dt:
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05/10/2004
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Publication #:
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Pub Dt:
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11/10/2005
| | | | |
Title:
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SEMICONDUCTOR DEVICE HAVING A DUMMY CONDUCTIVE VIA AND A METHOD OF MANUFACTURE THEREFOR
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|
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Patent #:
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Issue Dt:
|
08/01/2006
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Application #:
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10844664
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Filing Dt:
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05/12/2004
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Publication #:
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Pub Dt:
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11/17/2005
| | | | |
Title:
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METHOD OF OPTIMIZING RTL CODE FOR MULTIPLEX STRUCTURES
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Patent #:
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Issue Dt:
|
04/15/2008
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Application #:
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10847691
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Filing Dt:
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05/18/2004
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Publication #:
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Pub Dt:
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11/24/2005
| | | | |
Title:
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METHOD FOR CREATING A JTAG TAP CONTROLLER IN A SLICE FOR USE DURING CUSTOM INSTANCE CREATION TO AVOID THE NEED OF A BOUNDARY SCAN SYNTHESIS TOOL
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|
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Patent #:
|
|
Issue Dt:
|
03/06/2007
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Application #:
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10847692
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Filing Dt:
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05/18/2004
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Publication #:
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Pub Dt:
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11/24/2005
| | | | |
Title:
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HANDLING OF UNUSED COREWARE WITH EMBEDDED BOUNDARY SCAN CHAINS TO AVOID THE NEED OF A BOUNDARY SCAN SYNTHESIS TOOL DURING CUSTOM INSTANCE CREATION
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Patent #:
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Issue Dt:
|
07/25/2006
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Application #:
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10847789
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Filing Dt:
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05/18/2004
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Publication #:
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Pub Dt:
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12/02/2004
| | | | |
Title:
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NOVEL GATE DIELECTRIC STRUCTURE FOR REDUCING BORON PENETRATION AND CURRENT LEAKAGE
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Patent #:
|
|
Issue Dt:
|
10/03/2006
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Application #:
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10848994
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Filing Dt:
|
05/18/2004
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Publication #:
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Pub Dt:
|
11/24/2005
| | | | |
Title:
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METHOD AND SYSTEM FOR UTILIZING AN ISOFOCAL CONTOUR TO PERFORM OPTICAL AND PROCESS CORRECTIONS
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|
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Patent #:
|
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Issue Dt:
|
06/26/2007
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Application #:
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10850812
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Filing Dt:
|
05/21/2004
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Publication #:
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Pub Dt:
|
11/24/2005
| | | | |
Title:
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DEVICE AND METHOD TO ELIMINATE SHORTING INDUCED BY VIA TO METAL MISALIGNMENT
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|
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Patent #:
|
|
Issue Dt:
|
05/09/2006
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Application #:
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10852902
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Filing Dt:
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05/25/2004
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Publication #:
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Pub Dt:
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12/01/2005
| | | | |
Title:
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BUILT-IN SELF TEST TECHNIQUE FOR PROGRAMMABLE IMPEDANCE DRIVERS FOR RAPIDCHIP AND ASIC DRIVERS
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|
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Patent #:
|
|
Issue Dt:
|
05/17/2005
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Application #:
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10853395
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Filing Dt:
|
05/25/2004
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Title:
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ROBUST ELECTRONIC DEVICE PACKAGES
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|
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Patent #:
|
|
Issue Dt:
|
05/06/2008
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Application #:
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10855148
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Filing Dt:
|
05/27/2004
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Publication #:
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Pub Dt:
|
07/14/2005
| | | | |
Title:
|
METHODS AND APPARATUS TO REDUCE GROWTH FORMATIONS ON PLATED CONDUCTIVE LEADS
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|
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Patent #:
|
|
Issue Dt:
|
07/22/2008
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Application #:
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10855458
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Filing Dt:
|
05/27/2004
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Publication #:
|
|
Pub Dt:
|
12/01/2005
| | | | |
Title:
|
INPUT DEVICE FOR PORTABLE HANDSET
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|
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Patent #:
|
|
Issue Dt:
|
02/14/2006
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Application #:
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10856213
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Filing Dt:
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05/28/2004
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Publication #:
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|
Pub Dt:
|
11/04/2004
| | | | |
Title:
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TEST STRUCTURE FOR DETECTING BONDING-INDUCED CRACKS
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|
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Patent #:
|
|
Issue Dt:
|
06/20/2006
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Application #:
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10859857
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Filing Dt:
|
06/02/2004
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Publication #:
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|
Pub Dt:
|
12/08/2005
| | | | |
Title:
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METHOD OF GENERATING MULTIPLE HARDWARE DESCRIPTION LANGUAGE CONFIGURATIONS FOR A PHASE LOCKED LOOP FROM A SINGLE GENETIC MODEL FOR INTEGRATED CIRCUIT DESIGN
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|
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Patent #:
|
|
Issue Dt:
|
08/12/2008
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Application #:
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10859874
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Filing Dt:
|
06/02/2004
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Publication #:
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Pub Dt:
|
12/08/2005
| | | | |
Title:
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METHOD AND COMPUTER PROGRAM FOR MANAGEMENT OF SYNCHRONOUS AND ASYNCHRONOUS CLOCK DOMAIN CROSSING IN INTEGRATED CIRCUIT DESIGN
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|
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Patent #:
|
|
Issue Dt:
|
05/29/2007
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Application #:
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10862049
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Filing Dt:
|
06/04/2004
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Publication #:
|
|
Pub Dt:
|
12/08/2005
| | | | |
Title:
|
TEST STRUCTURES IN UNUSED AREAS OF SEMICONDUCTOR INTEGRATED CIRCUITS AND METHODS FOR DESIGNING THE SAME
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|
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Patent #:
|
|
Issue Dt:
|
10/14/2008
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Application #:
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10865179
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Filing Dt:
|
06/09/2004
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Publication #:
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Pub Dt:
|
12/15/2005
| | | | |
Title:
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SEMICONDUCTOR PACKAGE AND PROCESS UTILIZING PRE-FORMED MOLD CAP AND HEATSPREADER ASSEMBLY
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|
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Patent #:
|
|
Issue Dt:
|
05/02/2006
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Application #:
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10867003
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Filing Dt:
|
06/14/2004
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Publication #:
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Pub Dt:
|
12/29/2005
| | | | |
Title:
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SUBSTRATE PROFILE ANALYSIS
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|
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Patent #:
|
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Issue Dt:
|
03/14/2006
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Application #:
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10867014
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Filing Dt:
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06/14/2004
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Publication #:
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Pub Dt:
|
12/15/2005
| | | | |
Title:
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SUBSTRATE CONTACT ANALYSIS
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
|
10870834
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Filing Dt:
|
06/17/2004
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Publication #:
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Pub Dt:
|
12/02/2004
| | | | |
Title:
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Process for semiconductor device fabrication in which a insulating layer is formed on a semiconductor substrate
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Patent #:
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Issue Dt:
|
10/27/2009
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Application #:
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10874834
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Filing Dt:
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06/23/2004
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Publication #:
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Pub Dt:
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05/26/2005
| | | | |
Title:
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METHOD AND APPARATUS FOR POWER MANAGEMENT USING TRANSMISSION MODE WITH REDUCED POWER
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Patent #:
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Issue Dt:
|
02/24/2009
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Application #:
|
10875029
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Filing Dt:
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06/23/2004
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Publication #:
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Pub Dt:
|
12/29/2005
| | | | |
Title:
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DEVICE AND METHOD USING ISOTOPICALLY ENRICHED SILICON
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Patent #:
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Issue Dt:
|
01/23/2007
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Application #:
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10875128
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Filing Dt:
|
06/23/2004
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Publication #:
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Pub Dt:
|
01/12/2006
| | | | |
Title:
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YIELD DRIVEN MEMORY PLACEMENT SYSTEM
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|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
10876183
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Filing Dt:
|
06/24/2004
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Publication #:
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Pub Dt:
|
11/25/2004
| | | | |
Title:
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PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN INSULATING LAYER FORMED OVER A SEMICONDUCTOR SUBSTRATE
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|
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Patent #:
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|
Issue Dt:
|
01/02/2007
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Application #:
|
10878157
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Filing Dt:
|
06/28/2004
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Publication #:
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|
Pub Dt:
|
01/19/2006
| | | | |
Title:
|
METHODS FOR PROCESSING INTEGRATED CIRCUIT PACKAGES FORMED USING ELECTROPLATING AND APPARATUS MADE THEREFROM
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|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
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Application #:
|
10878857
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Filing Dt:
|
06/28/2004
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Publication #:
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|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
GRADED CONDUCTIVE STRUCTURE FOR USE IN A METAL-OXIDE-SEMICONDUCTOR DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
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Application #:
|
10879629
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Filing Dt:
|
06/29/2004
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
METHOD TO MONITOR PAD WEAR IN CMP PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
10879768
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Filing Dt:
|
06/28/2004
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Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
DEVICE FOR ESTIMATING CELL DELAY FROM A TABLE WITH ADDED VOLTAGE SWING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2010
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Application #:
|
10879909
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Filing Dt:
|
06/29/2004
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
HEAT SINK FORMED OF MULTIPLE METAL LAYERS ON BACKSIDE OF INTEGRATED CIRCUIT DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
10880216
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Filing Dt:
|
06/29/2004
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Publication #:
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|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
SYMMETRIC SIGNAL DISTRIBUTION THROUGH ABUTMENT CONNECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10881191
|
Filing Dt:
|
06/30/2004
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
METHODS AND APPARATUS FOR INTEGRATED CIRCUIT BALL BONDING USING STACKED BALL BUMPS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10883137
|
Filing Dt:
|
07/01/2004
|
Title:
|
BIMETALLIC OXIDE COMPOSITIONS FOR GATE DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10886763
|
Filing Dt:
|
07/08/2004
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
INTERDIGITADED CAPACITORS
|
|