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02/20/2007
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10975981
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10/27/2004
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04/27/2006
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05/08/2007
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10976518
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10/29/2004
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05/04/2006
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11/27/2007
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10/29/2004
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05/04/2006
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10/09/2007
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10977732
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10/29/2004
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07/21/2005
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01/05/2010
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03/24/2005
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04/01/2008
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11/02/2004
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03/24/2005
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07/11/2006
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11/03/2004
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05/04/2006
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08/11/2009
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05/04/2006
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05/27/2008
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11/08/2004
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05/11/2006
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12/12/2006
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05/11/2006
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01/30/2007
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07/28/2005
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02/20/2007
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05/18/2006
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11/12/2004
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07/14/2005
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04/17/2007
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11/16/2004
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05/18/2006
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MEMORY TILING ARCHITECTURE
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12/26/2006
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11/17/2004
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05/18/2006
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MEMORY GENERATION AND PLACEMENT
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07/08/2008
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11/17/2004
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05/18/2006
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11/18/2004
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05/18/2006
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12/05/2006
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05/25/2006
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08/14/2007
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11/19/2004
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05/25/2006
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03/13/2007
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11/19/2004
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07/14/2005
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05/01/2007
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10994114
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11/19/2004
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05/25/2006
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10/07/2008
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11/23/2004
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05/25/2006
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12/04/2007
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11/23/2004
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05/25/2006
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05/22/2007
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11/24/2004
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05/25/2006
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01/01/2008
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11/30/2004
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06/01/2006
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05/08/2007
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11/30/2004
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07/13/2006
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08/28/2007
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11/30/2004
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06/01/2006
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SEMICONDUCTOR DEVICE HAVING IMPROVED POWER DENSITY
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02/12/2008
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11/30/2004
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06/01/2006
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DUAL-GATE METAL-OXIDE SEMICONDUCTOR DEVICE
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04/03/2007
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11000104
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11/30/2004
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06/01/2006
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RRAM MEMORY TIMING LEARNING TOOL
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08/22/2006
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11000772
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12/01/2004
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04/14/2005
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PROCESS INDEPENDENT ALIGNMENT MARKS
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02/17/2009
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11002576
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12/01/2004
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06/01/2006
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AUTOMATIC RECOGNITION OF GEOMETRIC POINTS IN A TARGET IC DESIGN FOR OPC MASK QUALITY CALCULATION
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07/17/2007
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11004309
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12/03/2004
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06/08/2006
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09/09/2008
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12/07/2004
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06/08/2006
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07/10/2007
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12/06/2004
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06/08/2006
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REDUCED CAPACITANCE RESISTORS
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05/13/2008
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12/06/2004
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06/08/2006
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07/17/2007
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12/08/2004
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06/08/2006
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11/17/2009
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12/07/2004
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06/08/2006
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10/23/2007
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12/07/2004
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04/22/2008
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12/09/2004
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06/15/2006
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ACCELERATING PCB DEVELOPMENT AND DEBUG IN ADVANCE OF PLATFORM ASIC PROTOTYPE SAMPLES
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02/19/2008
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11010745
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12/13/2004
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06/15/2006
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CELL BUILDER FOR DIFFERENT LAYER STACKS
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10/23/2007
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12/12/2004
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06/15/2006
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05/20/2008
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11011384
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12/14/2004
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05/12/2005
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METHOD FOR POST-OPC MULTI LAYER OVERLAY QUALITY INSPECTION
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11/15/2011
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12/14/2004
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12/15/2005
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MASKLESS VORTEX PHASE SHIFT OPTICAL DIRECT WRITE LITHOGRAPHY
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05/13/2008
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11012003
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12/14/2004
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10/27/2005
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PROCESS AND APPARATUS FOR ACHIEVING SINGLE EXPOSURE PATTERN TRANSFER USING MASKLESS OPTICAL DIRECT WRITE LITHOGRAPHY
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08/21/2007
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12/14/2004
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06/15/2006
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03/27/2007
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12/15/2004
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06/15/2006
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FLOORPLAN VISUALIZATION METHOD USING GATE COUNT AND GATE DENSITY ESTIMATIONS
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NONE
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11012838
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12/15/2004
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05/05/2005
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System and method for using film deposition techniques to provide an antenna within an integrated circuit package
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04/24/2007
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11013641
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12/16/2004
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07/13/2006
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SYSTEM AND METHOD FOR IMPLEMENTING POSTPONED QUASI-MASKING TEST OUTPUT COMPRESSION IN INTEGRATED CIRCUIT
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NONE
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11014476
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12/16/2004
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05/26/2005
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Method to use a laser to perform the edge clean operation on a semiconductor wafer
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02/27/2007
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12/17/2004
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06/22/2006
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METHOD OF PARASITIC EXTRACTION FROM A PREVIOUSLY CALCULATED CAPACITANCE SOLUTION
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06/12/2007
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11015123
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12/17/2004
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06/22/2006
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METHOD OF IMPLEMENTING AN ENGINEERING CHANGE ORDER IN AN INTEGRATED CIRCUIT DESIGN BY WINDOWS
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05/29/2007
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12/18/2004
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06/22/2006
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SEMICONDUCTOR DEVICE PACKAGE WITH REDUCED LEAKAGE
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06/07/2011
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12/18/2004
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06/22/2006
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PACKAGES FOR ENCAPSULATED SEMICONDUCTOR DEVICES AND METHOD OF MAKING SAME
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07/11/2006
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11016014
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12/17/2004
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06/22/2006
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SYSTEM FOR IMPLEMENTING A CONFIGURABLE INTEGRATED CIRCUIT
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10/30/2007
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12/17/2004
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07/13/2006
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SYSTEM FOR PERFORMING AUTOMATIC TEST PIN ASSIGNMENT FOR A PROGRAMMABLE DEVICE
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02/14/2006
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11016468
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12/16/2004
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05/12/2005
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DIAMOND METAL-FILLED PATTERNS ACHIEVING LOW PARASITIC COUPLING CAPACITANCE
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07/08/2008
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11017015
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12/20/2004
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12/08/2005
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RULES AND DIRECTIVES FOR VALIDATING CORRECT DATA USED IN THE DESIGN OF SEMICONDUCTOR PRODUCTS
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07/22/2008
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11017017
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12/20/2004
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12/08/2005
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LANGUAGE AND TEMPLATES FOR USE IN THE DESIGN OF SEMICONDUCTOR PRODUCTS
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03/04/2008
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Application #:
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11019885
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Filing Dt:
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12/22/2004
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Publication #:
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Pub Dt:
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06/22/2006
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Title:
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INTEGRATED COMPUTER-AIDED CIRCUIT DESIGN KIT FACILITATING VERIFICATION OF DESIGNS ACROSS DIFFERENT PROCESS TECHNOLOGIES
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Patent #:
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Issue Dt:
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10/09/2007
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11022159
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Filing Dt:
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12/23/2004
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Publication #:
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Pub Dt:
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06/29/2006
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Title:
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TECHNIQUES FOR MONITORING MOBILE TELECOMMUNICATIONS FOR SHARED ACCOUNTS
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Patent #:
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Issue Dt:
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10/30/2007
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11027266
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Filing Dt:
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12/31/2004
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Publication #:
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Pub Dt:
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12/08/2005
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Title:
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GUIDED CAPTURE, CREATION, AND SEAMLESS INTEGRATION WITH SCALABLE COMPLEXITY OF A CLOCK SPECIFICATION INTO A DESIGN FLOW OF AN INTEGRATED CIRCUIT
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02/20/2007
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11028403
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01/03/2005
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Publication #:
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Pub Dt:
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05/26/2005
| | | | |
Title:
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STATIC TIMING AND RISK ANALYSIS TOOL
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04/10/2007
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11028695
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01/04/2005
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Pub Dt:
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07/06/2006
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Title:
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FAILURE ANALYSIS AND TESTING OF SEMI-CONDUCTOR DEVICES USING INTELLIGENT SOFTWARE ON AUTOMATED TEST EQUIPMENT (ATE)
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06/24/2008
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11031564
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01/06/2005
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Pub Dt:
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07/07/2005
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Title:
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METHOD TO SELECTIVELY IDENTIFY RELIABILITY RISK DIE BASED ON CHARACTERISTICS OF LOCAL REGIONS ON THE WAFER
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06/19/2007
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11032720
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01/10/2005
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Pub Dt:
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10/20/2005
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Title:
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THREE-DIMENSIONAL INTERCONNECT RESISTANCE EXTRACTION USING VARIATIONAL METHOD
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04/17/2007
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11036822
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01/14/2005
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08/24/2006
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Title:
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METHOD FOR ESTIMATING A FREQUENCY-BASED RAMPTIME LIMIT
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11/20/2007
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11037306
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01/18/2005
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Publication #:
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Pub Dt:
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08/24/2006
| | | | |
Title:
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FREQUENCY DEPENDENT TIMING MARGIN
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07/10/2007
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11041489
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01/24/2005
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08/24/2006
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Title:
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METHOD OF BUFFER INSERTION TO ACHIEVE PIN SPECIFIC DELAYS
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08/21/2007
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11046150
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01/28/2005
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Pub Dt:
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08/03/2006
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Title:
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MULTI-LAYER REGISTRATION AND DIMENSIONAL TEST MARK FOR SCATTEROMETRICAL MEASUREMENT
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06/30/2009
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11046949
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01/31/2005
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Title:
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PROCESS AND APPARATUS FOR SIMULTANEOUS LIGHT AND RADICAL SURFACE TREATMENT OF INTEGRATED CIRCUIT STRUCTURE
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Patent #:
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06/26/2007
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11049246
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02/02/2005
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Pub Dt:
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08/03/2006
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Title:
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DEVICE PACKAGES
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Patent #:
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07/10/2007
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11049407
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02/02/2005
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Pub Dt:
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08/03/2006
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Title:
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DEVICE PACKAGE
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Patent #:
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04/07/2009
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11050505
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02/03/2005
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Pub Dt:
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10/13/2005
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Title:
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METHOD AND SYSTEM FOR A NEW PACKET PREAMBLE FOR WIDEBAND WIRELESS LOCAL AREA NETWORK (LAN) SYSTEMS
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07/21/2009
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11052353
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02/07/2005
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06/15/2006
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Title:
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METHOD AND SYSTEM FOR FRAME FORMATS FOR MIMO CHANNEL MEASUREMENT EXCHANGE
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06/06/2006
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11053505
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02/08/2005
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Pub Dt:
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07/07/2005
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Title:
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MIXED LVR AND HVR RETICLE SET DESIGN FOR THE PROCESSING OF GATE ARRAYS, EMBEDDED ARRAYS AND RAPID CHIP PRODUCTS
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04/11/2006
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11054460
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02/09/2005
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Title:
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RRAM BACKEND FLOW
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Patent #:
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NONE
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11054879
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02/10/2005
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Pub Dt:
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07/07/2005
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Title:
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System and method for coevolutionary circuit design
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10/07/2008
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11055712
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02/10/2005
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Pub Dt:
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06/29/2006
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Title:
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PACKAGING FOR ELECTRONIC MODULES
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02/05/2008
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11055752
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02/10/2005
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Pub Dt:
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07/07/2005
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Title:
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METHOD FOR EVALUATING LOGIC FUNCTIONS BY LOGIC CIRCUITS HAVING OPTIMIZED NUMBER OF AND/OR SWITCHES
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02/24/2009
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11056838
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02/11/2005
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Pub Dt:
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08/17/2006
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METHOD AND SYSTEMS FOR UTILIZING SIMPLIFIED RESIST PROCESS MODELS TO PERFORM OPTICAL AND PROCESS CORRECTIONS
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07/21/2009
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11057690
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02/14/2005
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08/17/2006
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Title:
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HIGH-DENSITY FIELD EMISSION ELEMENTS AND A METHOD FOR FORMING SAID EMISSION ELEMENTS
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07/25/2006
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11058498
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02/15/2005
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07/21/2005
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Title:
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LOCAL INTERCONNECT FOR INTEGRATED CIRCUIT
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04/10/2007
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11061292
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02/18/2005
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Title:
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METHODS AND STRUCTURE FOR IMPROVED HIGH-SPEED TDF TESTING USING ON-CHIP PLL
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06/05/2007
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11061581
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02/18/2005
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08/24/2006
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Title:
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NEGATIVE BIAS TEMPERATURE INSTABILITY MODELING
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04/10/2007
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11063384
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02/22/2005
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08/24/2006
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Title:
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SYSTEMS AND METHODS FOR WAFER POLISHING
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Issue Dt:
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03/09/2010
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11065838
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02/25/2005
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08/31/2006
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Title:
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INTEGRATED CIRCUIT WITH STAGGERED DIFFERENTIAL WIRE BOND PAIRS
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07/24/2007
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11068237
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02/28/2005
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08/31/2006
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Title:
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CONTROL OF WAFER WARPAGE DURING BACKEND PROCESSING
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02/12/2008
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11071623
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03/03/2005
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09/07/2006
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Title:
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METHOD FOR DESCRIBING AND DEPLOYING DESIGN PLATFORM SETS
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08/22/2006
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11071903
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03/02/2005
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Pub Dt:
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09/07/2006
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Title:
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REDUCED DRY ETCHING LAG
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Issue Dt:
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10/03/2006
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11072127
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03/04/2005
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08/18/2005
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INTEGRATED CIRCUIT PROCESS MONITORING AND METROLOGY SYSTEM
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03/11/2008
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11072158
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03/04/2005
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Pub Dt:
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09/07/2006
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Title:
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SUPERCONDUCTOR WIRES FOR BACK END INTERCONNECTS
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Issue Dt:
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07/25/2006
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11073802
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03/07/2005
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Title:
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SUBSTRATE VIA LAYOUT TO IMPROVE BIAS HUMIDITY TESTING RELIABILITY
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11/20/2007
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11074173
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03/07/2005
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Pub Dt:
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09/07/2006
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METHOD FOR TRACING PATHS WITHIN A CIRCUIT
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11/07/2006
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11074358
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03/07/2005
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Publication #:
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Pub Dt:
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09/07/2006
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Title:
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INTEGRATED CIRCUIT PACKAGE WITH LEAD FINGERS EXTENDING INTO A SLOT OF A DIE PADDLE
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Patent #:
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Issue Dt:
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03/09/2010
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11074456
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03/07/2005
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Title:
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FORMING COPPER INTERCONNECTS WITH SN COATINGS
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Issue Dt:
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08/29/2006
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11075195
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03/07/2005
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Title:
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OPTICAL ERROR MINIMIZATION IN A SEMICONDUCTOR MANUFACTURING APPARATUS
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Issue Dt:
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04/04/2006
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11075239
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03/07/2005
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Title:
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DUAL SOURCE LITHOGRAPHY FOR DIRECT WRITE APPLICATION
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Issue Dt:
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03/24/2009
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11078052
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03/11/2005
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Pub Dt:
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09/14/2006
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Title:
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PACKAGE CONFIGURATION AND MANUFACTURING METHOD ENABLING THE ADDITION OF DECOUPLING CAPACITORS TO STANDARD PACKAGE DESIGNS
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Issue Dt:
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01/05/2010
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11078179
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03/10/2005
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Pub Dt:
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09/14/2006
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Title:
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SYSTEM AND METHOD FOR INCREASING YIELD FROM SEMICONDUCTOR WAFER ELECTROPLATING
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Issue Dt:
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01/27/2009
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11078830
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03/11/2005
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Pub Dt:
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09/14/2006
| | | | |
Title:
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BIPOLAR TRANSISTORS HAVING CONTROLLABLE TEMPERATURE COEFFICIENT OF CURRENT GAIN
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