Total properties:
12
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2012
|
Application #:
|
12168383
|
Filing Dt:
|
07/07/2008
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
Title:
|
CALIBRATION AND VERIFICATAION STRUCTURES FOR USE IN OPTICAL PROXIMITY CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2012
|
Application #:
|
12341542
|
Filing Dt:
|
12/22/2008
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
Title:
|
METHODS OF FABRICATING SEMICONDUCTOR DEVICES AND STRUCTURES THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
12348331
|
Filing Dt:
|
01/05/2009
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
ADJUSTMENT OF MASK SHAPES FOR IMPROVING PRINTABILITY OF DENSE INTEGRATED CIRCUIT LAYOUT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2012
|
Application #:
|
12350251
|
Filing Dt:
|
01/08/2009
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
METHODOLOGY OF PLACING PRINTING ASSIST FEATURE FOR RANDOM MASK LAYOUT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12360599
|
Filing Dt:
|
01/27/2009
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
Contacts in Semiconductor Devices
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
12360767
|
Filing Dt:
|
01/27/2009
|
Title:
|
GRIDDED CONTACTS IN SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2017
|
Application #:
|
12363863
|
Filing Dt:
|
02/02/2009
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
Title:
|
Secure Manufacturing of Programmable Devices
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
12363880
|
Filing Dt:
|
02/02/2009
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
Title:
|
SECURE PARTITIONING OF PROGRAMMABLE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2015
|
Application #:
|
12363903
|
Filing Dt:
|
02/02/2009
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
Title:
|
Secure Operation of Programmable Devices
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
12364804
|
Filing Dt:
|
02/03/2009
|
Publication #:
|
|
Pub Dt:
|
08/05/2010
| | | | |
Title:
|
SILICIDED SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
12367719
|
Filing Dt:
|
02/09/2009
|
Publication #:
|
|
Pub Dt:
|
08/12/2010
| | | | |
Title:
|
POWER TRANSISTOR PACKAGE WITH INTEGRATED BUS BAR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
12371799
|
Filing Dt:
|
02/16/2009
|
Publication #:
|
|
Pub Dt:
|
08/19/2010
| | | | |
Title:
|
VOLTAGE LEVEL CONVERTER WITH MIXED SIGNAL CONTROLLER
|
|