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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054600/0031   Pages: 53
Recorded: 11/19/2020
Attorney Dkt #:0941-4477M
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 40
1
Patent #:
7655388
Issue Dt:
02/02/2010
Application #:
11028421
Filing Dt:
01/03/2005
Publication #:
US20060147813
Pub Dt:
07/06/2006
Title:
MASK AND METHOD TO PATTERN CHROMELESS PHASE LITHOGRAPHY CONTACT HOLE
2
Patent #:
7993997
Issue Dt:
08/09/2011
Application #:
11865563
Filing Dt:
10/01/2007
Publication #:
US20090085122
Pub Dt:
04/02/2009
Title:
POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT
3
Patent #:
8572524
Issue Dt:
10/29/2013
Application #:
11943591
Filing Dt:
11/21/2007
Publication #:
US20090132992
Pub Dt:
05/21/2009
Title:
STATISTICAL OPTICAL PROXIMITY CORRECTION
4
Patent #:
7879732
Issue Dt:
02/01/2011
Application #:
11959034
Filing Dt:
12/18/2007
Publication #:
US20090156010
Pub Dt:
06/18/2009
Title:
THIN FILM ETCHING METHOD AND SEMICONDUCTOR DEVICE FABRICATION USING SAME
5
Patent #:
7795104
Issue Dt:
09/14/2010
Application #:
12030598
Filing Dt:
02/13/2008
Publication #:
US20090203185
Pub Dt:
08/13/2009
Title:
METHOD FOR FABRICATING DEVICE STRUCTURES HAVING A VARIATION IN ELECTRICAL CONDUCTIVITY
6
Patent #:
7816274
Issue Dt:
10/19/2010
Application #:
12057072
Filing Dt:
03/27/2008
Publication #:
US20090246920
Pub Dt:
10/01/2009
Title:
METHODS FOR NORMALIZING STRAIN IN A SEMICONDUCTOR DEVICE
7
Patent #:
7745320
Issue Dt:
06/29/2010
Application #:
12124177
Filing Dt:
05/21/2008
Publication #:
US20090289309
Pub Dt:
11/26/2009
Title:
METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS
8
Patent #:
8668833
Issue Dt:
03/11/2014
Application #:
12125030
Filing Dt:
05/21/2008
Publication #:
US20090291311
Pub Dt:
11/26/2009
Title:
METHOD OF FORMING A NANOSTRUCTURE
9
Patent #:
8712569
Issue Dt:
04/29/2014
Application #:
12147489
Filing Dt:
06/27/2008
Publication #:
US20090326996
Pub Dt:
12/31/2009
Title:
SYSTEM FOR DETERMINING POTENTIAL LOT CONSOLIDATION DURING MANUFACTURING
10
Patent #:
7955936
Issue Dt:
06/07/2011
Application #:
12172756
Filing Dt:
07/14/2008
Publication #:
US20100009502
Pub Dt:
01/14/2010
Title:
SEMICONDUCTOR FABRICATION PROCESS INCLUDING AN SIGE REWORK METHOD
11
Patent #:
8450046
Issue Dt:
05/28/2013
Application #:
12392093
Filing Dt:
02/24/2009
Publication #:
US20090214984
Pub Dt:
08/27/2009
Title:
METHODS FOR ENHANCING PHOTOLITHOGRAPHY PATTERNING
12
Patent #:
8912102
Issue Dt:
12/16/2014
Application #:
12396441
Filing Dt:
03/02/2009
Publication #:
US20100221926
Pub Dt:
09/02/2010
Title:
LASER ANNEALING
13
Patent #:
8643401
Issue Dt:
02/04/2014
Application #:
12432162
Filing Dt:
04/29/2009
Publication #:
US20100276815
Pub Dt:
11/04/2010
Title:
INTEGRATED CIRCUIT COMMUNICATION SYSTEM WITH DIFFERENTIAL SIGNAL AND METHOD OF MANUFACTURE THEREOF
14
Patent #:
8413083
Issue Dt:
04/02/2013
Application #:
12465431
Filing Dt:
05/13/2009
Publication #:
US20100293516
Pub Dt:
11/18/2010
Title:
MASK SYSTEM EMPLOYING SUBSTANTIALLY CIRCULAR OPTICAL PROXIMITY CORRECTION TARGET AND METHOD OF MANUFACTURE THEREOF
15
Patent #:
8293546
Issue Dt:
10/23/2012
Application #:
12477448
Filing Dt:
06/03/2009
Publication #:
US20090309192
Pub Dt:
12/17/2009
Title:
INTEGRATED CIRCUIT SYSTEM WITH SUB-GEOMETRY REMOVAL AND METHOD OF MANUFACTURE THEREOF
16
Patent #:
8148221
Issue Dt:
04/03/2012
Application #:
12581207
Filing Dt:
10/19/2009
Publication #:
US20100041242
Pub Dt:
02/18/2010
Title:
DOUBLE ANNEAL WITH IMPROVED RELIABILITY FOR DUAL CONTACT ETCH STOP LINER SCHEME
17
Patent #:
8647946
Issue Dt:
02/11/2014
Application #:
12621527
Filing Dt:
11/19/2009
Publication #:
US20110115009
Pub Dt:
05/19/2011
Title:
CONTROL GATE
18
Patent #:
8415236
Issue Dt:
04/09/2013
Application #:
12648309
Filing Dt:
12/29/2009
Publication #:
US20100167505
Pub Dt:
07/01/2010
Title:
METHODS FOR REDUCING LOADING EFFECTS DURING FILM FORMATION
19
Patent #:
8896810
Issue Dt:
11/25/2014
Application #:
12649212
Filing Dt:
12/29/2009
Publication #:
US20110157567
Pub Dt:
06/30/2011
Title:
LIQUID IMMERSION SCANNING EXPOSURE SYSTEM USING AN IMMERSION LIQUID CONFINED WITHIN A LENS HOOD
20
Patent #:
8530310
Issue Dt:
09/10/2013
Application #:
12650561
Filing Dt:
12/31/2009
Publication #:
US20110156121
Pub Dt:
06/30/2011
Title:
MEMORY CELL WITH IMPROVED RETENTION
21
Patent #:
8008744
Issue Dt:
08/30/2011
Application #:
12790975
Filing Dt:
05/31/2010
Publication #:
US20100230777
Pub Dt:
09/16/2010
Title:
SELECTIVE STI STRESS RELAXATION THROUGH ION IMPLANTATION
22
Patent #:
8785287
Issue Dt:
07/22/2014
Application #:
12803754
Filing Dt:
07/06/2010
Publication #:
US20120007185
Pub Dt:
01/12/2012
Title:
NOVEL METHOD TO TUNE NARROW WIDTH EFFECT WITH RAISED S/D STRUCTURE
23
Patent #:
7960283
Issue Dt:
06/14/2011
Application #:
12825325
Filing Dt:
06/28/2010
Publication #:
US20100267236
Pub Dt:
10/21/2010
Title:
METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS
24
Patent #:
8912567
Issue Dt:
12/16/2014
Application #:
12852995
Filing Dt:
08/09/2010
Publication #:
US20100320503
Pub Dt:
12/23/2010
Title:
STRAINED CHANNEL TRANSISTOR AND METHOD OF FABRICATION THEREOF
25
Patent #:
8541273
Issue Dt:
09/24/2013
Application #:
12888434
Filing Dt:
09/23/2010
Publication #:
US20120074537
Pub Dt:
03/29/2012
Title:
DIELECTRIC STACK
26
Patent #:
8410553
Issue Dt:
04/02/2013
Application #:
12964753
Filing Dt:
12/10/2010
Publication #:
US20110079850
Pub Dt:
04/07/2011
Title:
SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE
27
Patent #:
8519445
Issue Dt:
08/27/2013
Application #:
13182455
Filing Dt:
07/14/2011
Publication #:
US20110266628
Pub Dt:
11/03/2011
Title:
POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT
28
Patent #:
8658543
Issue Dt:
02/25/2014
Application #:
13368055
Filing Dt:
02/07/2012
Publication #:
US20130203244
Pub Dt:
08/08/2013
Title:
METHODS FOR PFET FABRICATION USING APM SOLUTIONS
29
Patent #:
8879221
Issue Dt:
11/04/2014
Application #:
13406537
Filing Dt:
02/28/2012
Publication #:
US20130222952
Pub Dt:
08/29/2013
Title:
ESD PROTECTION WITHOUT LATCH-UP
30
Patent #:
8692380
Issue Dt:
04/08/2014
Application #:
13657797
Filing Dt:
10/22/2012
Publication #:
US20130043565
Pub Dt:
02/21/2013
Title:
INTEGRATED CIRCUIT SYSTEM WITH SUB-GEOMETRY REMOVAL AND METHOD OF MANUFACTURE THEREOF
31
Patent #:
8933435
Issue Dt:
01/13/2015
Application #:
13727547
Filing Dt:
12/26/2012
Publication #:
US20140175381
Pub Dt:
06/26/2014
Title:
TUNNELING TRANSISTOR
32
Patent #:
8898597
Issue Dt:
11/25/2014
Application #:
13835339
Filing Dt:
03/15/2013
Publication #:
US20140282286
Pub Dt:
09/18/2014
Title:
ETCH FAILURE PREDICTION BASED ON WAFER RESIST TOP LOSS
33
Patent #:
8664711
Issue Dt:
03/04/2014
Application #:
14019508
Filing Dt:
09/05/2013
Publication #:
US20140001538
Pub Dt:
01/02/2014
Title:
DIELECTRIC STACK
34
Patent #:
9024286
Issue Dt:
05/05/2015
Application #:
14087183
Filing Dt:
11/22/2013
Publication #:
US20140077148
Pub Dt:
03/20/2014
Title:
RRAM CELL WITH BOTTOM ELECTRODE(S) POSITIONED IN A SEMICONDUCTOR SUBSTRATE
35
Patent #:
9076735
Issue Dt:
07/07/2015
Application #:
14092217
Filing Dt:
11/27/2013
Publication #:
US20150147872
Pub Dt:
05/28/2015
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS USING CHEMICAL MECHANICAL POLISHING
36
Patent #:
9087813
Issue Dt:
07/21/2015
Application #:
14174804
Filing Dt:
02/06/2014
Publication #:
US20140151775
Pub Dt:
06/05/2014
Title:
CONTROL GATE
37
Patent #:
9660020
Issue Dt:
05/23/2017
Application #:
14285774
Filing Dt:
05/23/2014
Publication #:
US20150340428
Pub Dt:
11/26/2015
Title:
INTEGRATED CIRCUITS WITH LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR STRUCTURES AND METHODS FOR FABRICATING THE SAME
38
Patent #:
9653365
Issue Dt:
05/16/2017
Application #:
15093888
Filing Dt:
04/08/2016
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH LOW, MEDIUM, AND/OR HIGH VOLTAGE TRANSISTORS ON AN EXTREMELY THIN SILICON-ON-INSULATOR SUBSTRATE
39
Patent #:
10381826
Issue Dt:
08/13/2019
Application #:
15135585
Filing Dt:
04/22/2016
Publication #:
US20170310103
Pub Dt:
10/26/2017
Title:
INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTECTION
40
Patent #:
10395955
Issue Dt:
08/27/2019
Application #:
15432925
Filing Dt:
02/15/2017
Publication #:
US20180233388
Pub Dt:
08/16/2018
Title:
METHOD AND SYSTEM FOR DETECTING A COOLANT LEAK IN A DRY PROCESS CHAMBER WAFER CHUCK
Assignor
1
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Exec Dt:
05/15/2020
Assignee
1
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
NO. 8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK
HSINCHU, TAIWAN 300-78
Correspondence name and address
BIRCH, STEWART, KOLASCH & BIRCH, LLP
8110 GATEHOUSE ROAD, SUITE 100 EAST
FALLS CHURCH, VA 22042-1248

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