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Total properties:
64
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Issue Dt:
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08/19/1997
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08663493
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Filing Dt:
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06/14/1996
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Title:
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Patent #:
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07/13/1999
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08771302
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Filing Dt:
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12/20/1996
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Title:
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Patent #:
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05/04/1999
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Application #:
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08825446
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Filing Dt:
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03/28/1997
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Title:
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ASYNCHRONOUS INTERFACE
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Patent #:
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12/07/1999
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08948842
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Filing Dt:
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10/10/1997
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Title:
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Patent #:
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03/26/2002
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Filing Dt:
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06/16/1998
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Title:
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METHOD FOR TESTABILITY ANALYSIS AND TEST POINT INSERTION AT THE RT-LEVEL OF A HARDWARE DEVELOPMENT LANGUAGE (HDL) SPECIFICATION
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Patent #:
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05/28/2002
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09184516
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Filing Dt:
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11/02/1998
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Title:
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Patent #:
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Issue Dt:
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04/03/2001
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09191154
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Filing Dt:
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11/12/1998
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Title:
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09192839
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Filing Dt:
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11/16/1998
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Title:
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METHOD AND APPARATUS FOR SCAN TESTING DIGITAL CIRCUITS
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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09209790
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Filing Dt:
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12/11/1998
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Title:
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CLOCK SKEW MANAGEMENT METHOD AND APPARATUS
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09218764
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12/22/1998
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Title:
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Patent #:
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12/04/2001
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Application #:
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09309827
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Filing Dt:
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05/11/1999
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Title:
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METHOD OF TESTING AT-SPEED CIRCUITS HAVING ASYNCHRONOUS CLOCKS AND CONTROLLER FOR USE THEREWITH
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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09316197
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Filing Dt:
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05/21/1999
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Title:
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PROGRAMMABLE CLOCK SIGNAL GENERATION CIRCUITS AND METHODS FOR GENERATING ACCURATE, HIGH FREQUENCY, CLOCK SIGNALS
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Patent #:
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08/27/2002
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10/29/1999
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Title:
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Patent #:
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11/26/2002
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09472386
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12/23/1999
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Title:
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Patent #:
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07/01/2003
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09570412
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05/12/2000
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Title:
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METHOD AND CIRCUIT FOR TESTING DC PARAMETERS OF CIRCUIT INPUT AND OUTPUT NODES
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Patent #:
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01/21/2003
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09607128
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Filing Dt:
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06/29/2000
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Title:
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Patent #:
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09/02/2003
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09626877
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Filing Dt:
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07/27/2000
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Title:
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HIERARCHICAL DESIGN AND TEST METHOD AND SYSTEM, PROGRAM PRODUCT EMBODYING THE METHOD AND INTEGRATED CIRCUIT PRODUCED THEREBY
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Patent #:
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02/10/2004
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09768501
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01/25/2001
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Pub Dt:
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07/25/2002
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Title:
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METHOD FOR SCAN CONTROLLED SEQUENTIAL SAMPLING OF ANALOG SIGNALS AND CIRCUIT FOR USE THEREWITH
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Patent #:
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07/13/2004
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09773541
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02/02/2001
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10/10/2002
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Title:
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METHOD FOR SCAN TESTING OF DIGITAL CIRCUIT, DIGITAL CIRCUIT FOR USE THEREWITH AND PROGRAM PRODUCT FOR INCORPORATING TEST METHODOLOGY INTO CIRCUIT DESCRIPTION
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04/19/2005
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09817299
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03/27/2001
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Pub Dt:
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10/03/2002
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Title:
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METHOD AND PROGRAM PRODUCT FOR DETECTING BUS CONFLICT AND FLOATING BUS CONDITIONS IN CIRCUIT DESIGNS
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Patent #:
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12/10/2002
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Application #:
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09842700
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Filing Dt:
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04/27/2001
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Publication #:
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Pub Dt:
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10/31/2002
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Title:
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Patent #:
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12/07/2004
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09843307
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Filing Dt:
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04/27/2001
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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METHOD OF DESIGNING CIRCUIT HAVING MULTIPLE TEST ACCESS PORTS, CIRCUIT PRODUCED THEREBY AND METHOD OF USING SAME
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Patent #:
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07/08/2003
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09888605
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Filing Dt:
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06/26/2001
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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CIRCUIT AND METHOD FOR DETECTING TRANSIENT VOLTAGES ON A DC POWER SUPPLY RAIL
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Patent #:
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12/21/2004
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09888607
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06/26/2001
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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METHOD OF TESTING EMBEDDED MEMORY ARRAY AND EMBEDDED MEMORY CONTROLLER FOR USE THEREWITH
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09896170
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06/29/2001
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01/03/2002
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Title:
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Method and system for collecting diverse data types within a manufacturing environment and accessing the diverse data types through a network portal
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11/01/2005
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09954078
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09/18/2001
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06/13/2002
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Title:
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METHOD,SYSTEM AND PROGRAM PRODUCT FOR TESTING AND/OR DIAGNOSING CIRCUITS USING EMBEDDED TEST CONTROLLER ACCESS DATA
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03/15/2005
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10011128
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12/10/2001
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06/12/2003
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Title:
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METHOD AND PROGRAM PRODUCT FOR DESIGNING HIERARCHICAL CIRCUIT FOR QUIESCENT CURRENT TESTING AND CIRCUIT PRODUCED THEREBY
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03/01/2005
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10015751
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12/17/2001
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Pub Dt:
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06/19/2003
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Title:
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METHOD AND PROGRAM PRODUCT FOR DESIGNING HIERARCHICAL CIRCUIT FOR QUIESCENT CURRENT TESTING
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05/20/2003
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10021810
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12/20/2001
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Title:
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CIRCUIT SYNTHESIS METHOD USING TECHNOLOGY PARAMETERS EXTRACTING CIRCUIT
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NONE
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10100620
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03/18/2002
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09/19/2002
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Title:
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Circuit and method for compensating for non-linear distortion
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09/02/2003
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10125384
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04/19/2002
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08/07/2003
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Title:
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METHOD AND CIRCUITRY FOR CONTROLLING CLOCKS OF EMBEDDED BLOCKS DURING LOGIC BIST TEST MODE
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07/06/2004
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10139294
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05/07/2002
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11/13/2003
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Title:
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TEST ACCESS CIRCUIT AND METHOD OF ACCESSING EMBEDDED TEST CONTROLLERS IN INTEGRATED CIRCUIT MODULES
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05/18/2004
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10156117
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05/29/2002
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12/04/2003
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Title:
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METHOD FOR COLLECTING FAILURE INFORMATION FOR A MEMORY USING AN EMBEDDED TEST CONTROLLER
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04/06/2004
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10162916
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06/06/2002
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08/07/2003
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CIRCUIT AND METHOD FOR DETERMINING THE LOCATION OF DEFECT IN A CIRCUIT
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06/01/2004
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10162917
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06/06/2002
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12/11/2003
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METHOD OF MASKING CORRUPT BITS DURING SIGNATURE ANALYSIS AND CIRCUIT FOR USE THEREWITH
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12/30/2003
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10180116
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06/27/2002
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01/01/2004
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SCAN TEST METHOD FOR PROVIDING REAL TIME IDENTIFICATION OF FAILING TEST PATTERNS AND TEST BIST CONTROLLER FOR USE THEREWITH
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04/13/2004
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10262737
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10/02/2002
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SEMICONDUCTOR CHARACTERIZATION AND PRODUCTION INFORMATION SYSTEM
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03/09/2004
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10300620
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11/21/2002
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04/17/2003
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Title:
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METHOD AND CIRCUIT FOR TESTING HIGH FREQUENCY MIXED SIGNAL CIRCUITS WITH LOW FREQUENCY SIGNALS
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04/20/2004
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10323815
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12/20/2002
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07/31/2003
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Title:
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METHOD AND PROGRAM PRODUCT FOR COMPLETING A CIRCUIT DESIGN HAVING EMBEDDED TEST STRUCTURES
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01/13/2004
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10323979
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12/20/2002
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07/31/2003
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SELF-CONTAINED EMBEDDED TEST DESIGN ENVORONMENT AND ENVIRONMENT SETUP UTILITY
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09/05/2006
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10349452
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01/23/2003
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08/07/2003
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Title:
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VERIFICATION OF EMBEDDED TEST STRUCTURES IN CIRCUIT DESIGNS
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NONE
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10357203
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02/04/2003
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08/07/2003
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Method and system for licensing intellectual property circuits
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01/02/2007
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10414309
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04/16/2003
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11/06/2003
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CIRCUIT AND METHOD FOR ADDING PARAMETRIC TEST CAPABILITY TO DIGITAL BOUNDARY SCAN
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03/13/2007
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10435094
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05/12/2003
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11/20/2003
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METHOD OF AND PROGRAM PRODUCT FOR PERFORMING GATE-LEVEL DIAGNOSIS OF FAILING VECTORS
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04/26/2005
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10634902
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08/06/2003
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03/18/2004
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CIRCUIT AND METHOD FOR ACCURATELY APPLYING A VOLTAGE TO A NODE OF AN INTEGRATED CIRCUIT
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11/21/2006
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10638388
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08/12/2003
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06/24/2004
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METHOD AND TEST CIRCUIT FOR TESTING MEMORY INTERNAL WRITE ENABLE
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05/06/2008
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10690594
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10/23/2003
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03/03/2005
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METHOD AND CIRCUIT FOR COLLECTING MEMORY FAILURE INFORMATION
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09/20/2005
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10/23/2003
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04/28/2005
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CEILING LAMP JUNCTION BOX/LAMP ROD FOLDING INSTALLATION STRUCTURE
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05/15/2007
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11/06/2003
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05/20/2004
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BOUNDARY SCAN WITH STROBED PAD DRIVER ENABLE
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NONE
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10724193
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12/01/2003
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06/24/2004
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Method for testing parameters of high speed data signals
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05/17/2005
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12/05/2003
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06/24/2004
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CIRCUIT AND METHOD FOR TESTING HIGH SPEED DATA CIRCUITS
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03/20/2007
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10739055
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12/19/2003
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08/19/2004
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03/06/2007
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10774512
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02/10/2004
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08/19/2004
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MEMORY REPAIR ANALYSIS METHOD AND CIRCUIT
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08/14/2007
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10868208
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06/16/2004
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12/23/2004
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MEMORY REPAIR CIRCUIT AND METHOD
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NONE
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10892203
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07/16/2004
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02/03/2005
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Processor interface for test access port
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NONE
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10895356
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07/21/2004
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10/13/2005
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Circuit and method for low frequency testing of high frequency signal waveforms
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01/02/2007
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10947189
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09/23/2004
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03/31/2005
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CIRCUIT AND METHOD FOR MEASURING JITTER OF HIGH SPEED SIGNALS
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11/18/2008
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10991365
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11/19/2004
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Pub Dt:
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05/26/2005
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Title:
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CIRCUIT AND METHOD FOR MEASURING DELAY OF HIGH SPEED SIGNALS
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Patent #:
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Issue Dt:
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12/26/2006
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Application #:
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11013319
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Filing Dt:
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12/17/2004
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Publication #:
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Pub Dt:
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10/27/2005
| | | | |
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Title:
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CLOCK CONTROLLER FOR AT-SPEED TESTING OF SCAN CIRCUITS
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Patent #:
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Issue Dt:
|
09/09/2008
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Application #:
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11060407
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Filing Dt:
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02/18/2005
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Publication #:
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Pub Dt:
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10/27/2005
| | | | |
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Title:
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CLOCKING METHODOLOGY FOR AT-SPEED TESTING OF SCAN CIRCUITS WITH SYNCHRONOUS CLOCKS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11109844
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Filing Dt:
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04/20/2005
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Publication #:
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Pub Dt:
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10/27/2005
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Title:
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Masking circuit and method of masking corrupted bits
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11144764
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Filing Dt:
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06/06/2005
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Publication #:
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Pub Dt:
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12/08/2005
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Title:
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Insertion of embedded test in RTL to GDSII flow
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|
|
|
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Patent #:
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Issue Dt:
|
11/10/2009
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Application #:
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11439497
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Filing Dt:
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05/24/2006
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Publication #:
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Pub Dt:
|
11/15/2007
| | | | |
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Title:
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METHOD FOR AT-SPEED TESTING OF MEMORY INTERFACE USING SCAN
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|
|
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Patent #:
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|
Issue Dt:
|
07/13/2010
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Application #:
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11853383
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Filing Dt:
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09/11/2007
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|
Publication #:
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|
Pub Dt:
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03/13/2008
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Title:
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METHOD AND APPARATUS FOR STORING AND DISTRIBUTING MEMORY REPAIR INFORMATION
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