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Patent #:
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Issue Dt:
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11/14/1989
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Application #:
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05973822
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Filing Dt:
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12/27/1978
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Title:
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RADIATION HARD, HIGH EMITTER-BASE BREAKDOWN BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
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08/11/1981
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Application #:
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06077234
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Filing Dt:
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09/19/1979
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Title:
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METHOD OF FABRICATING LATERAL PNP TRANSISTORS ULIZING SELECTIVE DIFFUSION AND COUNTER DOPING
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Patent #:
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Issue Dt:
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01/19/1982
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Application #:
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06081978
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Filing Dt:
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10/04/1979
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Title:
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VERTICAL FUSE AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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11/17/1981
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Application #:
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06082185
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Filing Dt:
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10/05/1979
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Title:
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COMPLEMENTARY IGFET BUFFER WITH IMPROVED BIPOLAR OUTPUT
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Patent #:
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Issue Dt:
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11/25/1980
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Application #:
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06082505
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Filing Dt:
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10/09/1979
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Title:
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PROGRAMMABLE THRESHOLD SWITCHABLES RESISTIVE MEMORY CELL ARRAY
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Patent #:
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Issue Dt:
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06/09/1981
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Application #:
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06082506
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Filing Dt:
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10/09/1979
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Title:
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TWO SWITCHABLE RESISTIVE ELEMENT PER CELL MEMORY ARRAY
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Patent #:
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Issue Dt:
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09/15/1981
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Application #:
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06106127
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Filing Dt:
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12/21/1979
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Title:
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METHOD FOR QUALIFYING BIASED INTEGRATED CIRCUITS ON A WAFER LEVEL
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Patent #:
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Issue Dt:
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04/07/1981
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Application #:
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06106128
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Filing Dt:
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12/21/1979
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Title:
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METHOD OF MAKING SCHOTTKY BARRIER DIODE BY IONIMPLANTATION AND IMPURITY DIFFUSION
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Patent #:
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Issue Dt:
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08/04/1981
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Application #:
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06106339
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Filing Dt:
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12/21/1979
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Title:
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METHOD FOR QUALIFYING BIASED BURN-IN INTEGRATED CIRCUITS ON A WAFER LEVEL
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Patent #:
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Issue Dt:
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03/09/1982
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Application #:
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06112618
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Filing Dt:
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01/16/1980
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Title:
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LOW THERMAL COEFFICIENT SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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12/08/1981
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Application #:
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06113430
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Filing Dt:
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01/18/1980
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Title:
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SYSTEM FOR SHORT CIRCUIT PROTECTION USING ELECTRONIC LOGIC IN A FEED BACK ARRANGEMENT
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Patent #:
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Issue Dt:
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11/10/1981
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Application #:
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06124201
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Filing Dt:
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02/25/1980
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Title:
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FABRICATION OF COMPLEMENTARY BIPOLAR TRANSISTORS AND CMOS DEVICES WITH POLY GATES
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Patent #:
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Issue Dt:
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10/06/1981
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Application #:
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06129913
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Filing Dt:
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03/12/1980
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Title:
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METHOD OF FABRICATING MESA BIPOLAR MEMORY CELL UTILIZING EPITAXIAL DEPOSITION, SUBSTRATE REMOVAL AND SPECIAL METALLIZATION
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Patent #:
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Issue Dt:
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06/15/1982
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Application #:
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06141100
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Filing Dt:
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04/17/1980
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Title:
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METHOD OF SOLDER REFLOW ASSEMBLY
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Patent #:
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Issue Dt:
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09/22/1981
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Application #:
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06141504
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Filing Dt:
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04/18/1980
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Title:
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METHOD OF FABRICATING SURFACE CONTACTS FOR BURIED LAYER INTO DIELECTRIC ISOLATED ISLANDS
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Patent #:
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Issue Dt:
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10/11/1983
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Application #:
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06159750
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Filing Dt:
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06/16/1980
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Title:
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METHOD OF SERIALIZATION OF DICE
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Patent #:
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Issue Dt:
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01/11/1983
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Application #:
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06170291
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Filing Dt:
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07/18/1980
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Title:
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DIFFERENTIAL LINEAR TO DIGITAL TRANSLATOR
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Patent #:
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Issue Dt:
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08/30/1983
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Application #:
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06190515
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Filing Dt:
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09/25/1980
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Title:
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RADIATION HARDENED-SELF ALIGNED CMOS AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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06/02/1987
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Application #:
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06200386
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Filing Dt:
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10/24/1980
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Title:
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FABRICATION OF ISOLATED REGIONS FOR USE IN SELF - ALIGNING DEVICE PROCESS UTILIZING SELECTIVE OXIDATION
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Patent #:
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Issue Dt:
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01/12/1982
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Application #:
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06212799
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Filing Dt:
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12/04/1980
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Title:
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MASK ALIGNMENT SCHEME FOR LATERALLY AND TOTALLY DIELECTRICALLY ISOLATED INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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09/11/1984
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Application #:
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06224931
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Filing Dt:
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01/14/1981
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Title:
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AMORPHOUS DEVICES AND INTERCONNECT SYSTEM AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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04/19/1983
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Application #:
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06231671
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Filing Dt:
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02/05/1981
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Title:
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TTL TO CMOS INTERFACE CIRCUIT
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Patent #:
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Issue Dt:
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05/01/1984
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Application #:
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06231672
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Filing Dt:
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02/05/1981
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Title:
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CMOS AMPLIFIER
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Patent #:
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Issue Dt:
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12/13/1983
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Application #:
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06232520
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Filing Dt:
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02/09/1981
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Title:
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REVERSIBLY PROGRAMMABLE POLYCRYSTALLINE SILICON MEMORY ELEMENT
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Patent #:
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Issue Dt:
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08/30/1983
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Application #:
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06242658
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Filing Dt:
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03/11/1981
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Title:
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INTEGRATED RAM/EAROM MEMORY SYSTEM
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Patent #:
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Issue Dt:
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06/21/1983
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Application #:
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06278990
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Filing Dt:
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06/30/1981
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Title:
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TIME-DIVISION MULTIPLEX SERIAL LOOP
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Patent #:
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Issue Dt:
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07/24/1984
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Application #:
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06296191
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Filing Dt:
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08/25/1981
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Title:
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MINIATURE RESISTIVE TEMPERATURE DETECTOR AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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09/18/1984
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Application #:
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06296192
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Filing Dt:
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08/25/1981
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Title:
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TRANSISTOR CIRCUIT FOR REDUCING GATE LEAKAGE CURRENT IN A JFET
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Patent #:
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Issue Dt:
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06/12/1984
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Application #:
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06300617
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Filing Dt:
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09/09/1981
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Title:
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POWER EFFICIENT TTL BUFFER FOR DRIVING LARGE CAPACITIVE LOADS
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Patent #:
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Issue Dt:
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07/21/1987
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Application #:
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06301761
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Filing Dt:
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09/14/1981
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Title:
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CIRCUIT DESIGN TECHNIQUE TO PREVENT CURRENT HOGGING WHEN MINIMIZING INTERCONNECT STRIPES BY PARALLELING STL OR ISL GATE INPUTS
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Patent #:
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Issue Dt:
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09/13/1983
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Application #:
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06306226
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Filing Dt:
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09/28/1981
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Title:
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VERTICAL FUSE AND METHOD OF FABRICATION
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Patent #:
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|
Issue Dt:
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06/26/1984
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Application #:
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06309194
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Filing Dt:
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10/06/1981
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Title:
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ISOLATED GATE JFET STRUCTURE
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Patent #:
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Issue Dt:
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08/09/1983
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Application #:
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06310035
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Filing Dt:
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10/09/1981
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Title:
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KELVIN-CONNECTED BURIED ZENER VOLTAGE REFERENCE CIRCUIT
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Patent #:
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Issue Dt:
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08/07/1984
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Application #:
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06326345
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Filing Dt:
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12/01/1981
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Title:
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CIRCUIT FOR TRIMMING FET DIFFERENTIAL PAIR OFFSET VOLTAGE WITHOUT INCREASING THE OFFSET VOLTAGE TEMPERATURE COEFFICIENT
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Patent #:
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Issue Dt:
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09/11/1984
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Application #:
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06351442
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Filing Dt:
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02/23/1982
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Title:
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HIGH TEMPERATURE BIAS LINE STABILIZED CURRENT SOURCES
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Patent #:
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Issue Dt:
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05/22/1984
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Application #:
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06351443
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Filing Dt:
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02/23/1982
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Title:
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HIGH TEMPERATURE CURRENT MIRROR AMPLIFIER
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Patent #:
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Issue Dt:
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07/17/1984
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Application #:
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06353604
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Filing Dt:
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03/01/1982
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Title:
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ROM/PLA STRUCTURE AND METHOD OF TESTING
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Patent #:
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Issue Dt:
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04/30/1985
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Application #:
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06363815
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Filing Dt:
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03/31/1982
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Title:
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INTEGRATED PROGRAM COUNTER MEMORY MANAGEMENT REGISTER AND INCREMENTER
|
|
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Patent #:
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Issue Dt:
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10/30/1984
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Application #:
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06372812
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Filing Dt:
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04/28/1982
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Title:
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PHASE-TO-VOLTAGE CONVERTER
|
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Patent #:
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Issue Dt:
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07/09/1985
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Application #:
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06382603
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Filing Dt:
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05/27/1982
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Title:
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PULSED LINEAR INTEGRATED CIRCUIT TESTER
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Patent #:
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Issue Dt:
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06/18/1985
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Application #:
|
06396072
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Filing Dt:
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07/07/1982
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Title:
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SLIC II - COMMON MODE CURRENT REJECTION
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|
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Patent #:
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Issue Dt:
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07/30/1985
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Application #:
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06406333
|
Filing Dt:
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08/09/1982
|
Title:
|
METHOD OF FABRICATION BIPOLAR TRANSISTOR WITH IMPROVED BASE COLLECTOR BREAKDOWN VOLTAGE AND COLLECTOR SERIES RESISTANCE
|
|
|
Patent #:
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|
Issue Dt:
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07/09/1985
|
Application #:
|
06414862
|
Filing Dt:
|
09/03/1982
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Title:
|
INTEGRATED CIRCUIT SWITCH USING STACKED SCRS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/1986
|
Application #:
|
06416034
|
Filing Dt:
|
09/08/1982
|
Title:
|
CACHE MEMORY FLUSH SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
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08/30/1983
|
Application #:
|
06431229
|
Filing Dt:
|
09/30/1982
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Title:
|
VOLTAGE EQUALIZER BRIDGE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/1984
|
Application #:
|
06435221
|
Filing Dt:
|
10/19/1982
|
Title:
|
METHOD FOR PROVIDING POLYSILICON THIN FILMS OF IMPROVED UNIFORMITY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/1985
|
Application #:
|
06447946
|
Filing Dt:
|
12/08/1982
|
Title:
|
I2L STRUCTURE AND FABRICATION PROCESS COMPATIBLE WITH HIGH VOLTAGE BIPOLAR TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/1986
|
Application #:
|
06447947
|
Filing Dt:
|
12/08/1982
|
Title:
|
FORMANT-BASED SPEECH SYNTHESIZER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/1985
|
Application #:
|
06454533
|
Filing Dt:
|
12/30/1982
|
Title:
|
A. C. TESTING OF LOGIC ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/1985
|
Application #:
|
06460020
|
Filing Dt:
|
01/21/1983
|
Title:
|
INTEGRATED CIRCUIT SWITCH USING STACKED SCRS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/1985
|
Application #:
|
06460061
|
Filing Dt:
|
01/21/1983
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Title:
|
ARITHMETIC LOGIC UNIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/1984
|
Application #:
|
06467295
|
Filing Dt:
|
02/17/1983
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Title:
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PROCESS FOR FABRICATION OF HIGH-SPEED RADIATION HARD BIPOLAR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/1986
|
Application #:
|
06475618
|
Filing Dt:
|
03/15/1983
|
Title:
|
ADDRESS DECODER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/1985
|
Application #:
|
06493234
|
Filing Dt:
|
05/10/1983
|
Title:
|
CONTROLLED CURRENT LIMITER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/1986
|
Application #:
|
06500910
|
Filing Dt:
|
06/03/1983
|
Title:
|
BINARILY WEIGHTED D TO A CONVERTER LADDER WITH INHERENTLY REDUCED LADDER SWITCHING NOISE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/1985
|
Application #:
|
06504312
|
Filing Dt:
|
06/14/1983
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Title:
|
HIGH VOLTAGE CURRENT MIRROR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/1986
|
Application #:
|
06506793
|
Filing Dt:
|
06/22/1983
|
Title:
|
REDUCTION OF SERIES PROPAGATION DELAY AND IMPEDANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/1986
|
Application #:
|
06506794
|
Filing Dt:
|
06/22/1983
|
Title:
|
POWER SWITCHED LOGIC GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/1986
|
Application #:
|
06518598
|
Filing Dt:
|
07/29/1983
|
Title:
|
METHOD OF FABRICATING LOW NOISE REFERENCE DIODES AND TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/1984
|
Application #:
|
06518725
|
Filing Dt:
|
07/29/1983
|
Title:
|
DIELECTRIC ISOLATION FABRICATION FOR LASER TRIMMING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/1987
|
Application #:
|
06526065
|
Filing Dt:
|
08/24/1983
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Title:
|
SPEECH DATA ECONDING SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/1986
|
Application #:
|
06526066
|
Filing Dt:
|
08/24/1983
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Title:
|
METHOD OF DETERMINING POSITION ON A WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/1986
|
Application #:
|
06566400
|
Filing Dt:
|
12/28/1983
|
Title:
|
PROCESS FOR MINIMIZING BORON DEPLETION IN N-CHANNEL FET AT THE SILICON-SILICON OXIDE INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/1986
|
Application #:
|
06593516
|
Filing Dt:
|
03/26/1984
|
Title:
|
HIGH DENSITY PACKAGING TECHNIQUE FOR ELECTRONIC SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/1986
|
Application #:
|
06598985
|
Filing Dt:
|
04/11/1984
|
Title:
|
CURRENT COMPENSATION FOR LOGIC GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/1985
|
Application #:
|
06599817
|
Filing Dt:
|
04/13/1984
|
Title:
|
METHOD OF FABRICATING AN ISOLATED GATE JFET
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/1986
|
Application #:
|
06610583
|
Filing Dt:
|
05/15/1984
|
Title:
|
LASER TRIMMING OF RESISTORS OVER DIELECTRICALLY ISOLATED ISLANDS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/1985
|
Application #:
|
06612877
|
Filing Dt:
|
05/22/1984
|
Title:
|
POLYSILICON THIN FILMS OF IMPROVED ELECTRICAL UNIFORMITY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/1986
|
Application #:
|
06620728
|
Filing Dt:
|
06/14/1984
|
Title:
|
GREY CODE DAC LADDER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/1986
|
Application #:
|
06620835
|
Filing Dt:
|
06/15/1984
|
Title:
|
A PROCESS OF MAKING TWIN WILL VLSI CMOS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/1987
|
Application #:
|
06625222
|
Filing Dt:
|
06/27/1984
|
Title:
|
CURRENT TO VOLTAGE INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/1985
|
Application #:
|
06630280
|
Filing Dt:
|
07/12/1984
|
Title:
|
CIRCUIT FOR INCREASING VOLTAGE GAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/1986
|
Application #:
|
06643362
|
Filing Dt:
|
08/22/1984
|
Title:
|
IMPLANT MASK REVERSAL PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/1987
|
Application #:
|
06668864
|
Filing Dt:
|
11/06/1984
|
Title:
|
DIFFERENTIAL INPUT STAGE FOR THE REALIZATION OF LOW NOISE AND HIGH PRECISION BIPOLAR TRANSISTOR AMPLIFIERS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/1986
|
Application #:
|
06669787
|
Filing Dt:
|
11/09/1984
|
Title:
|
METHOD FOR SELECTIVE DEPOSITION OF TUNGSTEN ON SILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/1986
|
Application #:
|
06669788
|
Filing Dt:
|
11/09/1984
|
Title:
|
PROGRAMMABLE CURRENT MIRROR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/1986
|
Application #:
|
06673386
|
Filing Dt:
|
11/20/1984
|
Title:
|
CMOS POWER-UP RESET CIRCUIT FOR GATE ARRAYS AND STANDARD CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/1986
|
Application #:
|
06675222
|
Filing Dt:
|
11/27/1984
|
Title:
|
MONOLITHIC TRANSIENT PROTECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/1987
|
Application #:
|
06676846
|
Filing Dt:
|
11/30/1984
|
Title:
|
REDUNDANT ROW DECODING FOR PROGRAMMABLE DEVICES
|
|
|
Patent #:
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|
Issue Dt:
|
11/19/1985
|
Application #:
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06678075
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Filing Dt:
|
12/04/1984
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Title:
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ELECTROCHEMICAL DIELECTRIC ISOLATION TECHNIQUE
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|
|
Patent #:
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|
Issue Dt:
|
12/30/1986
|
Application #:
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06694096
|
Filing Dt:
|
01/23/1985
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Title:
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ALIGNMENT TARGET IMAGE ENHANCEMENT FOR MICROLITHOGRAPHY PROCESS
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|
|
Patent #:
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|
Issue Dt:
|
09/15/1987
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Application #:
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06702601
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Filing Dt:
|
02/19/1985
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Title:
|
CONDUCTIVITY MODULATED SEMICONDUCTOR STRUCTURE
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|
|
Patent #:
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|
Issue Dt:
|
02/17/1987
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Application #:
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06720679
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Filing Dt:
|
04/08/1985
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Title:
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SUBCOLLECTOR FOR OXIDE AND JUNCTION ISOLATED IC'S
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|
|
Patent #:
|
|
Issue Dt:
|
11/10/1987
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Application #:
|
06723238
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Filing Dt:
|
04/15/1985
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Title:
|
SIMULTANEOUS PLASMA SCULPTURING AND DUAL TAPERED APERTURE ETCH
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1987
|
Application #:
|
06723239
|
Filing Dt:
|
04/15/1985
|
Title:
|
PHOTORESIST TAPERING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/1986
|
Application #:
|
06723581
|
Filing Dt:
|
04/12/1985
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Title:
|
STRESS FREE DIELECTRIC ISOLATION TECHNOLOGY
|
|
|
Patent #:
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|
Issue Dt:
|
01/05/1988
|
Application #:
|
06728271
|
Filing Dt:
|
04/29/1985
|
Title:
|
TTL COMPATIBLE CMOS INPUT BUFFER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/1988
|
Application #:
|
06739843
|
Filing Dt:
|
05/31/1985
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Title:
|
BIT ADDRESSABLE PROGRAMMING ARRANGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/1986
|
Application #:
|
06744336
|
Filing Dt:
|
06/13/1985
|
Title:
|
PULSED LINEAR INTEGRATED CIRCUIT TESTER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/1987
|
Application #:
|
06754711
|
Filing Dt:
|
07/15/1985
|
Title:
|
DIRECT COUPLED SWITHCING POWER SUPPLY WITH GTO SCR SWITCHING ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/1987
|
Application #:
|
06763861
|
Filing Dt:
|
08/09/1985
|
Title:
|
FUSE PROGRAMMABLE DC LEVEL GENERATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/1987
|
Application #:
|
06768326
|
Filing Dt:
|
08/22/1985
|
Title:
|
METHOD OF ENSURING ADHESION OF CHEMICALLY VAPOR DEPOSITED OXIDE TO GOLD INTEGRATED CIRCUIT INTERCONNECT LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/1986
|
Application #:
|
06771160
|
Filing Dt:
|
08/30/1985
|
Title:
|
METHOD FOR SUCCESSIVE APPROXIMATION A/D CONVERSION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/1986
|
Application #:
|
06771712
|
Filing Dt:
|
09/03/1985
|
Title:
|
ELECTRODEPOSITION OF SUBMICROMETER METALLIC INTERCONNECT FOR INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/1987
|
Application #:
|
06771846
|
Filing Dt:
|
09/09/1985
|
Title:
|
METHOD OF SELECTIVELY SOLDERING THE UNDERSIDE OF A SUBSTRATE HAVING LEADS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/1987
|
Application #:
|
06774474
|
Filing Dt:
|
09/10/1985
|
Title:
|
TTL COMPATIBLE INPUT BUFFER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/1989
|
Application #:
|
06777269
|
Filing Dt:
|
09/18/1985
|
Title:
|
IC WHICH ELIMINATES SUPPORT BIAS INFLUENCE ON DIELECTRICALLY ISOLATED COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/1987
|
Application #:
|
06777685
|
Filing Dt:
|
09/19/1985
|
Title:
|
PROGRAMMABLE ARRAY LOGIC WITH SHARED PRODUCT TERMS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/1987
|
Application #:
|
06777686
|
Filing Dt:
|
09/19/1985
|
Title:
|
PROGRAMMABLE ARRAY LOGIC WITH SHARED PRODUCT TERMS AND J-K REGISTERED OUTPUTS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/1987
|
Application #:
|
06782192
|
Filing Dt:
|
09/30/1985
|
Title:
|
ZENER STRUCTURES WITH CONNECTIONS TO BURIED LAYER
|
|