Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 029018/0043 | |
| Pages: | 20 |
| | Recorded: | 09/20/2012 | | |
Attorney Dkt #: | 1434.0112C |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
2
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Patent #:
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Issue Dt:
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05/04/2010
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Application #:
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11850218
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Filing Dt:
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09/05/2007
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Publication #:
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Pub Dt:
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03/05/2009
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Title:
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INTEGRATED CIRCUIT WITH DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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12106741
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Filing Dt:
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04/21/2008
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Publication #:
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Pub Dt:
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10/22/2009
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Title:
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INTEGRATED CIRCUIT INCLUDING A FERROELECTRIC MEMORY CELL AND METHOD OF MANUFACTURING THE SAME
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Assignee
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NOETHNITZER STR. 64 |
DRESDEN, GERMANY 01187 |
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Correspondence name and address
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PATRICK J. FINNAN
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1901 RESEARCH BOULEVARD
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SUITE 400
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ROCKVILLE, MD 20850
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