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Patent #:
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Issue Dt:
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03/06/2012
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Application #:
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12130570
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Filing Dt:
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05/30/2008
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Publication #:
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Pub Dt:
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12/03/2009
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Title:
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UTILIZATION OF A STORE BUFFER FOR ERROR RECOVERY ON A STORE ALLOCATION CACHE MISS
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Patent #:
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Issue Dt:
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09/25/2012
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Application #:
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12130579
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Filing Dt:
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05/30/2008
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Publication #:
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Pub Dt:
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12/03/2009
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Title:
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HIGH FREQUENCY INTERCONNECT PAD STRUCTURE
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Patent #:
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Issue Dt:
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10/19/2010
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Application #:
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12130918
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Filing Dt:
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05/30/2008
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Publication #:
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Pub Dt:
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04/02/2009
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Title:
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SEMICONDUCTOR ARRAY INCLUDING A MATRIX OF CELLS AND A METHOD OF MAKING A SEMICONDUCTOR ARRAY HAVING A MATRIX OF CELLS
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Patent #:
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Issue Dt:
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08/30/2011
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Application #:
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12139106
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Filing Dt:
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06/13/2008
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Publication #:
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Pub Dt:
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12/17/2009
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Title:
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METHOD AND CIRCUIT FOR EFUSE PROTECTION
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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12142115
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Filing Dt:
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06/19/2008
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Publication #:
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Pub Dt:
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12/24/2009
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Title:
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ADJUSTABLE BIPOLAR TRANSISTORS FORMED USING A CMOS PROCESS
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Patent #:
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Issue Dt:
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04/20/2010
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Application #:
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12144332
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Filing Dt:
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06/23/2008
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Publication #:
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Pub Dt:
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12/24/2009
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Title:
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MEMORY WITH HIGH SPEED SENSING
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Patent #:
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Issue Dt:
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10/19/2010
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Application #:
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12147230
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Filing Dt:
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06/26/2008
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Publication #:
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Pub Dt:
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12/31/2009
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Title:
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DIELECTRIC LEDGE FOR HIGH FREQUENCY DEVICES
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Patent #:
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Issue Dt:
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09/28/2010
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Application #:
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12147236
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Filing Dt:
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06/26/2008
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Publication #:
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Pub Dt:
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12/31/2009
| | | | |
Title:
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SILICIDED BASE STRUCTURE FOR HIGH FREQUENCY TRANSISTORS
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Patent #:
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Issue Dt:
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10/04/2011
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Application #:
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12147313
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Filing Dt:
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06/26/2008
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Publication #:
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Pub Dt:
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12/31/2009
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Title:
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SEMICONDUCTOR PACKAGE WITH REDUCED INDUCTIVE COUPLING BETWEEN ADJACENT BONDWIRE ARRAYS
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Patent #:
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Issue Dt:
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12/06/2011
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Application #:
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12163633
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Filing Dt:
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06/27/2008
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Publication #:
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Pub Dt:
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12/31/2009
| | | | |
Title:
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SYSTEM AND METHOD FOR EVALUATING A DYNAMIC POWER CONSUMPTION OF A BLOCK
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Patent #:
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Issue Dt:
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05/01/2012
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Application #:
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12163638
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Filing Dt:
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06/27/2008
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Publication #:
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Pub Dt:
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12/31/2009
| | | | |
Title:
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DEVICE HAVING TURBO DECODING CAPABILITIES AND A METHOD FOR TURBO DECODING
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Patent #:
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Issue Dt:
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10/29/2013
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Application #:
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12164444
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Filing Dt:
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06/30/2008
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Publication #:
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Pub Dt:
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12/31/2009
| | | | |
Title:
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METHOD FOR IMPLEMENTING A BIT-REVERSED INCREMENT IN A DATA PROCESSING SYSTEM
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Patent #:
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Issue Dt:
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03/30/2010
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Application #:
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12164622
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Filing Dt:
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06/30/2008
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Publication #:
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Pub Dt:
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12/31/2009
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Title:
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INTEGRATED CIRCUIT AND A METHOD FOR MEASURING A QUIESCENT CURRENT OF A MODULE
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Patent #:
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Issue Dt:
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12/14/2010
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Application #:
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12164755
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Filing Dt:
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06/30/2008
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Publication #:
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Pub Dt:
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12/31/2009
| | | | |
Title:
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MEMORY OPERATION TESTING
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Patent #:
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Issue Dt:
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10/18/2011
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Application #:
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12164760
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Filing Dt:
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06/30/2008
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Publication #:
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Pub Dt:
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12/31/2009
| | | | |
Title:
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CIRCUIT AND METHOD FOR AVOIDING SOFT ERRORS IN STORAGE DEVICES
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Patent #:
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Issue Dt:
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08/13/2013
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Application #:
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12169888
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Filing Dt:
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07/09/2008
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Publication #:
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Pub Dt:
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01/14/2010
| | | | |
Title:
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MULTI-EXPOSURE LITHOGRAPHY EMPLOYING A SINGLE ANTI-REFLECTIVE COATING LAYER
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Patent #:
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Issue Dt:
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07/19/2011
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Application #:
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12169964
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Filing Dt:
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07/09/2008
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Publication #:
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Pub Dt:
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01/14/2010
| | | | |
Title:
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INTEGRATED CONFORMAL SHIELDING METHOD AND PROCESS USING REDISTRIBUTED CHIP PACKAGING
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Patent #:
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Issue Dt:
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01/11/2011
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Application #:
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12176634
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Filing Dt:
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07/21/2008
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Publication #:
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Pub Dt:
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01/21/2010
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Title:
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METHOD TO REDUCE THRESHOLD VOLTAGE (VT) IN SILICON GERMANIUM (SIGE), HIGH-K DIELECTRIC-METAL GATE, P-TYPE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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02/01/2011
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Application #:
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12177986
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Filing Dt:
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07/23/2008
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Publication #:
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Pub Dt:
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01/28/2010
| | | | |
Title:
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SEMICONDUCTOR RESISTOR FORMED IN METAL GATE STACK
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Patent #:
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Issue Dt:
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05/25/2010
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Application #:
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12178800
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Filing Dt:
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07/24/2008
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Publication #:
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Pub Dt:
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01/28/2010
| | | | |
Title:
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BURIED ASYMMETRIC JUNCTION ESD PROTECTION DEVICE
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Patent #:
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Issue Dt:
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09/20/2011
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Application #:
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12179629
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Filing Dt:
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07/25/2008
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Publication #:
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Pub Dt:
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01/28/2010
| | | | |
Title:
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DYNAMIC ADDRESS-TYPE SELECTION CONTROL IN A DATA PROCESSING SYSTEM
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Patent #:
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Issue Dt:
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06/07/2011
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Application #:
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12179631
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Filing Dt:
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07/25/2008
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Publication #:
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Pub Dt:
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01/28/2010
| | | | |
Title:
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DEBUG TRACE MESSAGING WITH ONE OR MORE CHARACTERISTIC INDICATORS
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Patent #:
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Issue Dt:
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03/19/2013
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Application #:
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12179632
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Filing Dt:
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07/25/2008
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Publication #:
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Pub Dt:
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01/28/2010
| | | | |
Title:
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DEBUG MESSAGE GENERATION USING A SELECTED ADDRESS TYPE
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Patent #:
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|
Issue Dt:
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12/11/2012
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Application #:
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12179791
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Filing Dt:
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07/25/2008
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Publication #:
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Pub Dt:
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01/28/2010
| | | | |
Title:
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SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR EXECUTING A HIGH LEVEL PROGRAMMING LANGUAGE CONDITIONAL STATEMENT
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Patent #:
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|
Issue Dt:
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02/07/2012
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Application #:
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12179792
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Filing Dt:
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07/25/2008
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Publication #:
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Pub Dt:
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01/28/2010
| | | | |
Title:
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SYSTEM AND METHOD FOR PROVIDING A BLENDED PICTURE
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Patent #:
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Issue Dt:
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11/23/2010
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Application #:
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12179828
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Filing Dt:
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07/25/2008
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Publication #:
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Pub Dt:
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01/28/2010
| | | | |
Title:
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INTEGRATED CIRCUIT AND A METHOD FOR RECOVERING FROM A LOW-POWER PERIOD
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Patent #:
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Issue Dt:
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12/06/2011
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Application #:
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12179839
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Filing Dt:
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07/25/2008
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Publication #:
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Pub Dt:
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01/28/2010
| | | | |
Title:
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DEVICE AND METHOD FOR EVALUATING A TEMPERATURE
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Patent #:
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|
Issue Dt:
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01/10/2012
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Application #:
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12180166
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Filing Dt:
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07/25/2008
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Publication #:
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Pub Dt:
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01/28/2010
| | | | |
Title:
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PHASE-LOCKED LOOP SYSTEM WITH A PHASE-ERROR SPREADING CIRCUIT
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Patent #:
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Issue Dt:
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10/18/2011
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Application #:
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12181701
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Filing Dt:
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07/29/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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SYSTEM AND METHOD FOR FETCHING INFORMATION TO A CACHE MODULE USING A WRITE BACK ALLOCATE ALGORITHM
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Patent #:
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Issue Dt:
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03/08/2011
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Application #:
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12181766
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Filing Dt:
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07/29/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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SELF-ALIGNED IN-LAID SPLIT GATE MEMORY AND METHOD OF MAKING
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Patent #:
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Issue Dt:
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01/31/2012
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Application #:
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12182349
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Filing Dt:
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07/30/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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METHOD FOR FORMING AN INSULATED GATE FIELD EFFECT DEVICE
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Patent #:
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Issue Dt:
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11/22/2011
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Application #:
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12182421
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Filing Dt:
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07/30/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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SEMICONDUCTOR DEVICES WITH EXTENDED ACTIVE REGIONS
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Patent #:
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|
Issue Dt:
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07/27/2010
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Application #:
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12183550
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Filing Dt:
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07/31/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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SQUARE TO PSEUDO-SINUSOIDAL CLOCK CONVERSION CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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06/14/2011
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Application #:
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12183755
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Filing Dt:
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07/31/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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BALUN SIGNAL TRANSFORMER AND METHOD OF FORMING
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Patent #:
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|
Issue Dt:
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09/11/2012
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Application #:
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12183767
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Filing Dt:
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07/31/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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INTEGRATED CIRCUIT HAVING AN ARRAY SUPPLY VOLTAGE CONTROL CIRCUIT
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|
|
Patent #:
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|
Issue Dt:
|
08/07/2012
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Application #:
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12184377
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Filing Dt:
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08/01/2008
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Publication #:
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|
Pub Dt:
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02/04/2010
| | | | |
Title:
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PACKAGING AN INTEGRATED CIRCUIT DIE WITH BACKSIDE METALLIZATION
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Patent #:
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|
Issue Dt:
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02/08/2011
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Application #:
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12184438
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Filing Dt:
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08/01/2008
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Publication #:
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|
Pub Dt:
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02/04/2010
| | | | |
Title:
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LITHOGRAPHY FOR PITCH REDUCTION
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Patent #:
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Issue Dt:
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10/23/2012
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Application #:
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12188819
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Filing Dt:
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08/08/2008
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Publication #:
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Pub Dt:
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02/11/2010
| | | | |
Title:
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ECHO CANCELLER WITH HEAVY DOUBLE-TALK ESTIMATION
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Patent #:
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Issue Dt:
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11/15/2011
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Application #:
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12192513
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Filing Dt:
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08/15/2008
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Publication #:
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Pub Dt:
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02/18/2010
| | | | |
Title:
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PROVISION OF EXTENDED ADDRESSING MODES IN A SINGLE INSTRUCTION MULTIPLE DATA (SIMD) DATA PROCESSOR
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Patent #:
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|
Issue Dt:
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07/19/2011
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Application #:
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12194131
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Filing Dt:
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08/19/2008
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Publication #:
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Pub Dt:
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02/25/2010
| | | | |
Title:
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TRANSISTOR WITH GAIN VARIATION COMPENSATION
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Patent #:
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Issue Dt:
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01/10/2012
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Application #:
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12194273
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Filing Dt:
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08/19/2008
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Publication #:
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Pub Dt:
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02/25/2010
| | | | |
Title:
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METHOD FOR ADDRESS COMPARISON AND A DEVICE HAVING ADDRESS COMPARISON CAPABILITIES
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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12194286
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Filing Dt:
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08/19/2008
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Publication #:
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Pub Dt:
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02/25/2010
| | | | |
Title:
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METHOD FOR EXECUTING AN INSTRUCTION LOOP AND A DEVICE HAVING INSTRUCTION LOOP EXECUTION CAPABILITIES
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Patent #:
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|
Issue Dt:
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07/19/2016
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Application #:
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12195220
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Filing Dt:
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08/20/2008
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Publication #:
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Pub Dt:
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02/25/2010
| | | | |
Title:
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DEBUG INSTRUCTION FOR EXECUTION BY A FIRST THREAD TO GENERATE A DEBUG EVENT IN A SECOND THREAD TO CAUSE A HALTING OPERATION
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Patent #:
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Issue Dt:
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02/28/2012
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Application #:
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12196730
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Filing Dt:
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08/22/2008
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Publication #:
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Pub Dt:
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02/25/2010
| | | | |
Title:
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DATA PROCESSING DEVICE DESIGN TOOL AND METHODS
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Patent #:
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|
Issue Dt:
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12/28/2010
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Application #:
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12199093
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Filing Dt:
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08/27/2008
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Publication #:
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Pub Dt:
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03/04/2010
| | | | |
Title:
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MEMORY DEVICE AND METHOD THEREOF
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Patent #:
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Issue Dt:
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03/06/2012
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Application #:
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12201216
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Filing Dt:
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08/29/2008
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Publication #:
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Pub Dt:
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03/04/2010
| | | | |
Title:
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CACHE SNOOP LIMITING WITHIN A MULTIPLE MASTER DATA PROCESSING SYSTEM
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Patent #:
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Issue Dt:
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10/26/2010
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Application #:
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12201623
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Filing Dt:
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08/29/2008
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Publication #:
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Pub Dt:
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03/04/2010
| | | | |
Title:
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PACKAGE DEVICE HAVING CRACK ARREST FEATURE AND METHOD OF FORMING
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Patent #:
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Issue Dt:
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10/26/2010
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Application #:
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12201932
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Filing Dt:
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08/29/2008
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Publication #:
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|
Pub Dt:
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03/04/2010
| | | | |
Title:
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SYSTEM AND METHOD FOR COOLING USING IMPINGING JET CONTROL
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|
|
Patent #:
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|
Issue Dt:
|
03/27/2012
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Application #:
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12205210
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Filing Dt:
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09/05/2008
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Publication #:
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|
Pub Dt:
|
03/11/2010
| | | | |
Title:
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ERROR DETECTION SCHEMES FOR A UNIFIED CACHE IN A DATA PROCESSING SYSTEM
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|
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Patent #:
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|
Issue Dt:
|
05/17/2011
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Application #:
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12205438
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Filing Dt:
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09/05/2008
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Publication #:
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|
Pub Dt:
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03/11/2010
| | | | |
Title:
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POWER MOSFET WITH A GATE STRUCTURE OF DIFFERENT MATERIAL
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Patent #:
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Issue Dt:
|
06/08/2010
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Application #:
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12206332
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Filing Dt:
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09/08/2008
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Publication #:
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|
Pub Dt:
|
03/11/2010
| | | | |
Title:
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CIRCUIT AND METHOD FOR OPTIMIZING MEMORY SENSE AMPLIFIER TIMING
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|
Patent #:
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|
Issue Dt:
|
04/05/2011
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Application #:
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12207120
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Filing Dt:
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09/09/2008
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Publication #:
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Pub Dt:
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03/11/2010
| | | | |
Title:
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METHODS FOR FORMING VARACTOR DIODES
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Patent #:
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Issue Dt:
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10/26/2010
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Application #:
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12207127
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Filing Dt:
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09/09/2008
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Publication #:
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Pub Dt:
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03/11/2010
| | | | |
Title:
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COUNTER-DOPED VARACTOR STRUCTURE AND METHOD
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Patent #:
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Issue Dt:
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09/21/2010
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Application #:
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12233922
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Filing Dt:
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09/19/2008
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Publication #:
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Pub Dt:
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03/25/2010
| | | | |
Title:
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MEMORY HAVING SELF-TIMED BIT LINE BOOST CIRCUIT AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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06/29/2010
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Application #:
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12234709
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Filing Dt:
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09/22/2008
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Publication #:
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Pub Dt:
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03/25/2010
| | | | |
Title:
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METHOD OF FORMING SEMICONDUCTOR PACKAGE
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Patent #:
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Issue Dt:
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10/23/2012
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Application #:
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12237834
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Filing Dt:
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09/25/2008
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Publication #:
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Pub Dt:
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03/25/2010
| | | | |
Title:
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EFFECTIVE EFUSE STRUCTURE
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Patent #:
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Issue Dt:
|
10/26/2010
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Application #:
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12240513
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Filing Dt:
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09/29/2008
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Publication #:
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Pub Dt:
|
04/01/2010
| | | | |
Title:
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METHOD OF FORMING A PACKAGE WITH EXPOSED COMPONENT SURFACES
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Patent #:
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Issue Dt:
|
07/19/2011
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Application #:
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12241139
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Filing Dt:
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09/30/2008
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Publication #:
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Pub Dt:
|
04/01/2010
| | | | |
Title:
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METHOD OF FORMING A GATE DIELECTRIC BY IN-SITU PLASMA
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10/11/2011
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04/01/2010
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10/26/2010
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04/01/2010
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05/08/2012
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04/22/2010
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03/19/2013
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04/29/2010
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01/03/2012
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05/06/2010
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05/06/2010
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06/07/2011
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11/12/2008
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05/13/2010
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04/13/2010
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05/27/2010
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07/05/2011
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05/27/2010
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06/21/2011
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05/27/2010
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05/27/2010
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05/07/2013
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01/29/2009
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02/05/2013
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02/17/2011
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11/22/2011
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12/24/2009
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10/04/2011
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11/19/2008
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08/06/2009
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08/07/2012
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07/28/2015
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06/23/2011
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08/10/2010
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05/27/2010
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02/03/2015
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06/10/2010
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06/17/2010
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06/17/2010
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07/01/2010
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07/27/2010
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07/08/2010
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07/22/2010
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07/22/2010
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07/29/2010
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09/09/2010
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09/24/2009
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09/23/2010
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09/23/2010
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