Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 032445/0056 | |
| Pages: | 4 |
| | Recorded: | 03/14/2014 | | |
| Attorney Dkt #: | 1026-RT-1 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
12
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08552996
|
Filing Dt:
|
11/03/1995
|
|
Title:
|
METHOD FOR THE ANTICIPATED READING OF SERIAL ACCESS MEMORY, AND MEMORY PERTAINING THERETO
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
09121466
|
Filing Dt:
|
07/23/1998
|
|
Title:
|
EXTERNALLY CONTROLLED POWER ON RESET DEVICE FOR NON-VOLATILE MEMORY IN INTEGRATED CIRCUIT FORM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2004
|
Application #:
|
09710089
|
Filing Dt:
|
11/10/2000
|
|
Title:
|
APPARATUS FOR VERIFYING THE DATA RETENTION IN NON-VOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
11420422
|
Filing Dt:
|
05/25/2006
|
|
Publication #:
|
|
Pub Dt:
|
03/29/2007
| | | | |
|
Title:
|
EMBEDDED PROTOCOL SELECTION TECHNIQUE, RELATED INTERFACE AND COMPUTER PROGRAM PRODUCT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
11460071
|
Filing Dt:
|
07/26/2006
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
|
Title:
|
SHARED REDUNDANT MEMORY ARCHITECTURE AND MEMORY SYSTEM INCORPORATING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
|
Application #:
|
11592735
|
Filing Dt:
|
11/03/2006
|
|
Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
|
Title:
|
MEMORY ACCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
11724046
|
Filing Dt:
|
03/14/2007
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
|
Title:
|
SELF-UPDATING MEMORY CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
11780441
|
Filing Dt:
|
07/19/2007
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
|
Title:
|
FLASH MEMORY INTERFACE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2011
|
Application #:
|
11801745
|
Filing Dt:
|
05/09/2007
|
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
|
Title:
|
MEMORY BLOCK COMPACTION METHOD, CIRCUIT, AND SYSTEM IN STORAGE DEVICES BASED ON FLASH MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
12075991
|
Filing Dt:
|
05/09/2007
|
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
|
Title:
|
WEAR LEVELING IN STORAGE DEVICES BASED ON FLASH MEMORIES AND RELATED CIRCUIT, SYSTEM, AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2012
|
Application #:
|
12973305
|
Filing Dt:
|
12/20/2010
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2011
| | | | |
|
Title:
|
WEAR LEVELING IN STORAGE DEVICES BASED ON FLASH MEMORIES AND RELATED CIRCUIT, SYSTEM, AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2015
|
Application #:
|
13196820
|
Filing Dt:
|
08/02/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
|
Title:
|
GARBAGE COLLECTION IN STORAGE DEVICES BASED ON FLASH MEMORIES
|
|
|
Assignee
|
|
|
|
|
| 2091, GYEONGCHUNG-DAERO, BUBAL-EUB, ICHEON-SI |
| GYEONGGI-DO, KOREA, REPUBLIC OF |
|
|
Correspondence name and address
|
| |
IP&T GROUP LLP
|
| |
8230 LEESBURG PIKE
|
| |
SUITE 650
|
| |
VIENNA, VA 22182
|
Search Results as of:
06/16/2024 01:26 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
